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[NDS32] Implement e8 pipeline.

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gcc/
	* config.gcc (nds32*-*-*): Check that e8 is valid to --with-cpu.
	* config/nds32/nds32-e8.md: New file.
	* config/nds32/nds32-opts.h (nds32-cpu_type): Add CPU_E8.
	* config/nds32/nds32-pipelines-auxiliary.c: Implementation for e8
	pipeline.
	* config/nds32/nds32-protos.h: More declarations for e8 pipeline.
	* config/nds32/nds32.md (pipeline_model): Add e8.
	* config/nds32/nds32.opt (mcpu): Support e8 pipeline cpus.
	* config/nds32/pipelines.md: Include e8 settings.

Co-Authored-By: Chung-Ju Wu <jasonwucj@gmail.com>

From-SVN: r259220
This commit is contained in:
Kito Cheng 2018-04-08 09:02:31 +00:00 committed by Chung-Ju Wu
parent 8fd5214127
commit 7c1583bdd8
9 changed files with 514 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
gcc/ChangeLog
View File

@ -1,3 +1,16 @@
2018-04-08 Kito Cheng <kito.cheng@gmail.com>
Chung-Ju Wu <jasonwucj@gmail.com>
* config.gcc (nds32*-*-*): Check that e8 is valid to --with-cpu.
* config/nds32/nds32-e8.md: New file.
* config/nds32/nds32-opts.h (nds32-cpu_type): Add CPU_E8.
* config/nds32/nds32-pipelines-auxiliary.c: Implementation for e8
pipeline.
* config/nds32/nds32-protos.h: More declarations for e8 pipeline.
* config/nds32/nds32.md (pipeline_model): Add e8.
* config/nds32/nds32.opt (mcpu): Support e8 pipeline cpus.
* config/nds32/pipelines.md: Include e8 settings.
2018-04-08 Kito Cheng <kito.cheng@gmail.com>
Chung-Ju Wu <jasonwucj@gmail.com>

4
gcc/config.gcc
View File

@ -4315,11 +4315,11 @@ case "${target}" in
"")
with_cpu=n9
;;
n6 | n8 | s8 | n9)
n6 | n8 | e8 | s8 | n9)
# OK
;;
*)
echo "Cannot accept --with-cpu=$with_cpu, available values are: n6 n8 s8 n9" 1>&2
echo "Cannot accept --with-cpu=$with_cpu, available values are: n6 n8 e8 s8 n9" 1>&2
exit 1
;;
esac

329
gcc/config/nds32/nds32-e8.md Normal file
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@ -0,0 +1,329 @@
;; Pipeline descriptions of Andes NDS32 cpu for GNU compiler
;; Copyright (C) 2012-2018 Free Software Foundation, Inc.
;; Contributed by Andes Technology Corporation.
;;
;; This file is part of GCC.
;;
;; GCC is free software; you can redistribute it and/or modify it
;; under the terms of the GNU General Public License as published
;; by the Free Software Foundation; either version 3, or (at your
;; option) any later version.
;;
;; GCC is distributed in the hope that it will be useful, but WITHOUT
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
;; License for more details.
;;
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
;; ------------------------------------------------------------------------
;; Define E8 pipeline settings.
;; ------------------------------------------------------------------------
(define_automaton "nds32_e8_machine")
;; ------------------------------------------------------------------------
;; Pipeline Stages
;; ------------------------------------------------------------------------
;; IF - Instruction Fetch
;; II - Instruction Issue / Address Generation
;; EX - Instruction Execution
;; EXD - Psuedo Stage / Load Data Completion
(define_cpu_unit "e8_ii" "nds32_e8_machine")
(define_cpu_unit "e8_ex" "nds32_e8_machine")
(define_insn_reservation "nds_e8_unknown" 1
(and (eq_attr "type" "unknown")
(eq_attr "pipeline_model" "e8"))
"e8_ii, e8_ex")
(define_insn_reservation "nds_e8_misc" 1
(and (eq_attr "type" "misc")
(eq_attr "pipeline_model" "e8"))
"e8_ii, e8_ex")
(define_insn_reservation "nds_e8_alu" 1
(and (eq_attr "type" "alu")
(eq_attr "pipeline_model" "e8"))
"e8_ii, e8_ex")
(define_insn_reservation "nds_e8_load" 1
(and (match_test "nds32::load_single_p (insn)")
(eq_attr "pipeline_model" "e8"))
"e8_ii, e8_ex")
(define_insn_reservation "nds_e8_store" 1
(and (match_test "nds32::store_single_p (insn)")
(eq_attr "pipeline_model" "e8"))
"e8_ii, e8_ex")
(define_insn_reservation "nds_e8_load_multiple_1" 1
(and (and (eq_attr "type" "load_multiple")
(eq_attr "combo" "1"))
(eq_attr "pipeline_model" "e8"))
"e8_ii, e8_ex")
(define_insn_reservation "nds_e8_load_multiple_2" 1
(and (ior (and (eq_attr "type" "load_multiple")
(eq_attr "combo" "2"))
(match_test "nds32::load_double_p (insn)"))
(eq_attr "pipeline_model" "e8"))
"e8_ii, e8_ii+e8_ex, e8_ex")
(define_insn_reservation "nds_e8_load_multiple_3" 1
(and (and (eq_attr "type" "load_multiple")
(eq_attr "combo" "3"))
(eq_attr "pipeline_model" "e8"))
"e8_ii, (e8_ii+e8_ex)*2, e8_ex")
(define_insn_reservation "nds_e8_load_multiple_4" 1
(and (and (eq_attr "type" "load_multiple")
(eq_attr "combo" "4"))
(eq_attr "pipeline_model" "e8"))
"e8_ii, (e8_ii+e8_ex)*3, e8_ex")
(define_insn_reservation "nds_e8_load_multiple_5" 1
(and (and (eq_attr "type" "load_multiple")
(eq_attr "combo" "5"))
(eq_attr "pipeline_model" "e8"))
"e8_ii, (e8_ii+e8_ex)*4, e8_ex")
(define_insn_reservation "nds_e8_load_multiple_6" 1
(and (and (eq_attr "type" "load_multiple")
(eq_attr "combo" "6"))
(eq_attr "pipeline_model" "e8"))
"e8_ii, (e8_ii+e8_ex)*5, e8_ex")
(define_insn_reservation "nds_e8_load_multiple_7" 1
(and (and (eq_attr "type" "load_multiple")
(eq_attr "combo" "7"))
(eq_attr "pipeline_model" "e8"))
"e8_ii, (e8_ii+e8_ex)*6, e8_ex")
(define_insn_reservation "nds_e8_load_multiple_8" 1
(and (and (eq_attr "type" "load_multiple")
(eq_attr "combo" "8"))
(eq_attr "pipeline_model" "e8"))
"e8_ii, (e8_ii+e8_ex)*7, e8_ex")
(define_insn_reservation "nds_e8_load_multiple_12" 1
(and (and (eq_attr "type" "load_multiple")
(eq_attr "combo" "12"))
(eq_attr "pipeline_model" "e8"))
"e8_ii, (e8_ii+e8_ex)*11, e8_ex")
(define_insn_reservation "nds_e8_store_multiple_1" 1
(and (and (eq_attr "type" "store_multiple")
(eq_attr "combo" "1"))
(eq_attr "pipeline_model" "e8"))
"e8_ii, e8_ex")
(define_insn_reservation "nds_e8_store_multiple_2" 1
(and (ior (and (eq_attr "type" "store_multiple")
(eq_attr "combo" "2"))
(match_test "nds32::store_double_p (insn)"))
(eq_attr "pipeline_model" "e8"))
"e8_ii, e8_ii+e8_ex, e8_ex")
(define_insn_reservation "nds_e8_store_multiple_3" 1
(and (and (eq_attr "type" "store_multiple")
(eq_attr "combo" "3"))
(eq_attr "pipeline_model" "e8"))
"e8_ii, (e8_ii+e8_ex)*2, e8_ex")
(define_insn_reservation "nds_e8_store_multiple_4" 1
(and (and (eq_attr "type" "store_multiple")
(eq_attr "combo" "4"))
(eq_attr "pipeline_model" "e8"))
"e8_ii, (e8_ii+e8_ex)*3, e8_ex")
(define_insn_reservation "nds_e8_store_multiple_5" 1
(and (and (eq_attr "type" "store_multiple")
(eq_attr "combo" "5"))
(eq_attr "pipeline_model" "e8"))
"e8_ii, (e8_ii+e8_ex)*4, e8_ex")
(define_insn_reservation "nds_e8_store_multiple_6" 1
(and (and (eq_attr "type" "store_multiple")
(eq_attr "combo" "6"))
(eq_attr "pipeline_model" "e8"))
"e8_ii, (e8_ii+e8_ex)*5, e8_ex")
(define_insn_reservation "nds_e8_store_multiple_7" 1
(and (and (eq_attr "type" "store_multiple")
(eq_attr "combo" "7"))
(eq_attr "pipeline_model" "e8"))
"e8_ii, (e8_ii+e8_ex)*6, e8_ex")
(define_insn_reservation "nds_e8_store_multiple_8" 1
(and (and (eq_attr "type" "store_multiple")
(eq_attr "combo" "8"))
(eq_attr "pipeline_model" "e8"))
"e8_ii, (e8_ii+e8_ex)*7, e8_ex")
(define_insn_reservation "nds_e8_store_multiple_12" 1
(and (and (eq_attr "type" "store_multiple")
(eq_attr "combo" "12"))
(eq_attr "pipeline_model" "e8"))
"e8_ii, (e8_ii+e8_ex)*11, e8_ex")
(define_insn_reservation "nds_e8_mul_fast" 1
(and (match_test "nds32_mul_config != MUL_TYPE_SLOW")
(and (eq_attr "type" "mul")
(eq_attr "pipeline_model" "e8")))
"e8_ii, e8_ex")
(define_insn_reservation "nds_e8_mul_slow" 1
(and (match_test "nds32_mul_config == MUL_TYPE_SLOW")
(and (eq_attr "type" "mul")
(eq_attr "pipeline_model" "e8")))
"e8_ii, e8_ex*16")
(define_insn_reservation "nds_e8_mac_fast" 1
(and (match_test "nds32_mul_config != MUL_TYPE_SLOW")
(and (eq_attr "type" "mac")
(eq_attr "pipeline_model" "e8")))
"e8_ii, e8_ii+e8_ex, e8_ex")
(define_insn_reservation "nds_e8_mac_slow" 1
(and (match_test "nds32_mul_config == MUL_TYPE_SLOW")
(and (eq_attr "type" "mac")
(eq_attr "pipeline_model" "e8")))
"e8_ii, (e8_ii+e8_ex)*16, e8_ex")
(define_insn_reservation "nds_e8_div" 1
(and (eq_attr "type" "div")
(eq_attr "pipeline_model" "e8"))
"e8_ii, (e8_ii+e8_ex)*36, e8_ex")
(define_insn_reservation "nds_e8_branch" 1
(and (eq_attr "type" "branch")
(eq_attr "pipeline_model" "e8"))
"e8_ii, e8_ex")
;; ------------------------------------------------------------------------
;; Comment Notations and Bypass Rules
;; ------------------------------------------------------------------------
;; Producers (LHS)
;; LD
;; Load data from the memory and produce the loaded data. The result is
;; ready at EXD.
;; LMW(N, M)
;; There are N micro-operations within an instruction that loads multiple
;; words. The result produced by the M-th micro-operation is sent to
;; consumers. The result is ready at EXD.
;; ADDR_OUT
;; Most load/store instructions can produce an address output if updating
;; the base register is required. The result is ready at EX, which is
;; produced by ALU.
;; ALU, MOVD44, MUL, MAC
;; The result is ready at EX.
;; DIV_Rs
;; A division instruction saves the quotient result to Rt and saves the
;; remainder result to Rs. The instruction is separated into two micro-
;; operations. The first micro-operation writes to Rt, and the seconde
;; one writes to Rs. Each of the results is ready at EX.
;;
;; Consumers (RHS)
;; ALU, MUL, DIV
;; Require operands at EX.
;; ADDR_IN_MOP(N)
;; N denotes the address input is required by the N-th micro-operation.
;; Such operand is required at II.
;; ST
;; A store instruction requires its data at EX.
;; SMW(N, M)
;; There are N micro-operations within an instruction that stores multiple
;; words. Each M-th micro-operation requires its data at EX.
;; BR_COND
;; If a branch instruction is conditional, its input data is required at EX.
;; LD -> ADDR_IN_MOP(1)
(define_bypass 2
"nds_e8_load"
"nds_e8_branch,\
nds_e8_load, nds_e8_store,\
nds_e8_load_multiple_1,nds_e8_load_multiple_2, nds_e8_load_multiple_3,\
nds_e8_load_multiple_4,nds_e8_load_multiple_5, nds_e8_load_multiple_6,\
nds_e8_load_multiple_7,nds_e8_load_multiple_8, nds_e8_load_multiple_12,\
nds_e8_store_multiple_1,nds_e8_store_multiple_2, nds_e8_store_multiple_3,\
nds_e8_store_multiple_4,nds_e8_store_multiple_5, nds_e8_store_multiple_6,\
nds_e8_store_multiple_7,nds_e8_store_multiple_8, nds_e8_store_multiple_12"
"nds32_e8_load_to_ii_p"
)
;; LD -> ALU, MUL, MAC, DIV, BR_COND, ST, SMW(N, 1)
(define_bypass 2
"nds_e8_load"
"nds_e8_alu,
nds_e8_mul_fast, nds_e8_mul_slow,\
nds_e8_mac_fast, nds_e8_mac_slow,\
nds_e8_div,\
nds_e8_branch,\
nds_e8_store,\
nds_e8_store_multiple_1,nds_e8_store_multiple_2, nds_e8_store_multiple_3,\
nds_e8_store_multiple_4,nds_e8_store_multiple_5, nds_e8_store_multiple_6,\
nds_e8_store_multiple_7,nds_e8_store_multiple_8, nds_e8_store_multiple_12"
"nds32_e8_load_to_ex_p"
)
;; ALU, MOVD44, MUL, MAC, DIV_Rs, LD_bi, ADDR_OUT -> ADDR_IN_MOP(1)
(define_bypass 2
"nds_e8_alu,
nds_e8_mul_fast, nds_e8_mul_slow,\
nds_e8_mac_fast, nds_e8_mac_slow,\
nds_e8_div,\
nds_e8_load, nds_e8_store,\
nds_e8_load_multiple_1,nds_e8_load_multiple_2, nds_e8_load_multiple_3,\
nds_e8_load_multiple_4,nds_e8_load_multiple_5, nds_e8_load_multiple_6,\
nds_e8_load_multiple_7,nds_e8_load_multiple_8, nds_e8_load_multiple_12,\
nds_e8_store_multiple_1,nds_e8_store_multiple_2, nds_e8_store_multiple_3,\
nds_e8_store_multiple_4,nds_e8_store_multiple_5, nds_e8_store_multiple_6,\
nds_e8_store_multiple_7,nds_e8_store_multiple_8, nds_e8_store_multiple_12"
"nds_e8_branch,\
nds_e8_load, nds_e8_store,\
nds_e8_load_multiple_1,nds_e8_load_multiple_2, nds_e8_load_multiple_3,\
nds_e8_load_multiple_4,nds_e8_load_multiple_5, nds_e8_load_multiple_6,\
nds_e8_load_multiple_7,nds_e8_load_multiple_8, nds_e8_load_multiple_12,\
nds_e8_store_multiple_1,nds_e8_store_multiple_2, nds_e8_store_multiple_3,\
nds_e8_store_multiple_4,nds_e8_store_multiple_5, nds_e8_store_multiple_6,\
nds_e8_store_multiple_7,nds_e8_store_multiple_8, nds_e8_store_multiple_12"
"nds32_e8_ex_to_ii_p"
)
;; LMW(N, N) -> ADDR_IN_MOP(1)
(define_bypass 2
"nds_e8_load_multiple_1,nds_e8_load_multiple_2, nds_e8_load_multiple_3,\
nds_e8_load_multiple_4,nds_e8_load_multiple_5, nds_e8_load_multiple_6,\
nds_e8_load_multiple_7,nds_e8_load_multiple_8, nds_e8_load_multiple_12"
"nds_e8_branch,\
nds_e8_load, nds_e8_store,\
nds_e8_load_multiple_1,nds_e8_load_multiple_2, nds_e8_load_multiple_3,\
nds_e8_load_multiple_4,nds_e8_load_multiple_5, nds_e8_load_multiple_6,\
nds_e8_load_multiple_7,nds_e8_load_multiple_8, nds_e8_load_multiple_12,\
nds_e8_store_multiple_1,nds_e8_store_multiple_2, nds_e8_store_multiple_3,\
nds_e8_store_multiple_4,nds_e8_store_multiple_5, nds_e8_store_multiple_6,\
nds_e8_store_multiple_7,nds_e8_store_multiple_8, nds_e8_store_multiple_12"
"nds32_e8_last_load_to_ii_p"
)
;; LMW(N, N) -> ALU, MUL, MAC, DIV, BR_COND, ST, SMW(N, 1)
(define_bypass 2
"nds_e8_load_multiple_1,nds_e8_load_multiple_2, nds_e8_load_multiple_3,\
nds_e8_load_multiple_4,nds_e8_load_multiple_5, nds_e8_load_multiple_6,\
nds_e8_load_multiple_7,nds_e8_load_multiple_8, nds_e8_load_multiple_12"
"nds_e8_alu,
nds_e8_mul_fast, nds_e8_mul_slow,\
nds_e8_mac_fast, nds_e8_mac_slow,\
nds_e8_div,\
nds_e8_branch,\
nds_e8_store,\
nds_e8_store_multiple_1,nds_e8_store_multiple_2, nds_e8_store_multiple_3,\
nds_e8_store_multiple_4,nds_e8_store_multiple_5, nds_e8_store_multiple_6,\
nds_e8_store_multiple_7,nds_e8_store_multiple_8, nds_e8_store_multiple_12"
"nds32_e8_last_load_to_ex_p"
)

1
gcc/config/nds32/nds32-opts.h
View File

@ -39,6 +39,7 @@ enum nds32_cpu_type
{
CPU_N6,
CPU_N8,
CPU_E8,
CPU_N9,
CPU_SIMPLE
};

138
gcc/config/nds32/nds32-pipelines-auxiliary.c
View File

@ -445,6 +445,42 @@ n8_consumed_by_ex_p (rtx_insn *consumer, rtx def_reg)
return reg_overlap_p (def_reg, use_rtx);
}
/* Check the dependency between the producer defining DEF_REG and CONSUMER
requiring input operand at AG (II). */
bool
e8_consumed_by_addr_in_p (rtx_insn *consumer, rtx def_reg)
{
return n8_consumed_by_addr_in_p (consumer, def_reg);
}
/* Check the dependency between the producer defining DEF_REG and CONSUMER
requiring input operand at EX. */
bool
e8_consumed_by_ex_p (rtx_insn *consumer, rtx def_reg)
{
rtx use_rtx;
switch (get_attr_type (consumer))
{
case TYPE_ALU:
case TYPE_STORE:
use_rtx = SET_SRC (PATTERN (consumer));
break;
case TYPE_MUL:
case TYPE_MAC:
case TYPE_DIV:
case TYPE_BRANCH:
case TYPE_STORE_MULTIPLE:
return n8_consumed_by_ex_p (consumer, def_reg);
default:
gcc_unreachable ();
}
return reg_overlap_p (def_reg, use_rtx);
}
/* Check the dependency between the producer defining DEF_REG and CONSUMER
requiring input operand at EX. */
bool
@ -762,6 +798,108 @@ nds32_n8_last_load_to_ex_p (rtx_insn *producer, rtx_insn *consumer)
return n8_consumed_by_ex_p (consumer, last_def_reg);
}
/* Guard functions for E8 cores. */
bool
nds32_e8_load_to_ii_p (rtx_insn *producer, rtx_insn *consumer)
{
rtx def_reg = SET_DEST (PATTERN (producer));
return e8_consumed_by_addr_in_p (consumer, def_reg);
}
bool
nds32_e8_load_to_ex_p (rtx_insn *producer, rtx_insn *consumer)
{
rtx def_reg = SET_DEST (PATTERN (producer));
return e8_consumed_by_ex_p (consumer, def_reg);
}
bool
nds32_e8_ex_to_ii_p (rtx_insn *producer, rtx_insn *consumer)
{
rtx def_reg;
switch (get_attr_type (producer))
{
case TYPE_ALU:
/* No data hazards if AGEN's input is produced by MOVI or SETHI. */
if (GET_CODE (PATTERN (producer)) == SET)
{
rtx dest = SET_DEST (PATTERN (producer));
rtx src = SET_SRC (PATTERN (producer));
if ((REG_P (dest) || GET_CODE (dest) == SUBREG)
&& (GET_CODE (src) == CONST_INT || GET_CODE (src) == HIGH))
return false;
}
def_reg = SET_DEST (PATTERN (producer));
break;
case TYPE_MUL:
case TYPE_MAC:
def_reg = SET_DEST (PATTERN (producer));
break;
case TYPE_DIV:
if (INSN_CODE (producer) == CODE_FOR_divmodsi4
|| INSN_CODE (producer) == CODE_FOR_udivmodsi4)
{
rtx def_reg1 = SET_DEST (parallel_element (producer, 0));
rtx def_reg2 = SET_DEST (parallel_element (producer, 1));
return (e8_consumed_by_addr_in_p (consumer, def_reg1)
|| e8_consumed_by_addr_in_p (consumer, def_reg2));
}
def_reg = SET_DEST (PATTERN (producer));
break;
case TYPE_LOAD:
case TYPE_STORE:
case TYPE_LOAD_MULTIPLE:
case TYPE_STORE_MULTIPLE:
if (!post_update_insn_p (producer))
return false;
def_reg = extract_base_reg (producer);
break;
default:
gcc_unreachable ();
}
return e8_consumed_by_addr_in_p (consumer, def_reg);
}
bool
nds32_e8_last_load_to_ii_p (rtx_insn *producer, rtx_insn *consumer)
{
rtx last_def_reg = extract_nth_access_reg (producer, -1);
if (last_def_reg == NULL_RTX)
return false;
gcc_assert (REG_P (last_def_reg) || GET_CODE (last_def_reg) == SUBREG);
return e8_consumed_by_addr_in_p (consumer, last_def_reg);
}
bool
nds32_e8_last_load_to_ex_p (rtx_insn *producer, rtx_insn *consumer)
{
rtx last_def_reg = extract_nth_access_reg (producer, -1);
if (last_def_reg == NULL_RTX)
return false;
gcc_assert (REG_P (last_def_reg) || GET_CODE (last_def_reg) == SUBREG);
return e8_consumed_by_ex_p (consumer, last_def_reg);
}
/* Guard functions for N9 cores. */
/* Check dependencies from MM to EX. */

6
gcc/config/nds32/nds32-protos.h
View File

@ -107,6 +107,12 @@ extern bool nds32_n8_last_load_to_ii_p (rtx_insn *, rtx_insn *);
extern bool nds32_n8_last_load_two_to_ii_p (rtx_insn *, rtx_insn *);
extern bool nds32_n8_last_load_to_ex_p (rtx_insn *, rtx_insn *);
extern bool nds32_e8_load_to_ii_p (rtx_insn *, rtx_insn *);
extern bool nds32_e8_load_to_ex_p (rtx_insn *, rtx_insn *);
extern bool nds32_e8_ex_to_ii_p (rtx_insn *, rtx_insn *);
extern bool nds32_e8_last_load_to_ii_p (rtx_insn *, rtx_insn *);
extern bool nds32_e8_last_load_to_ex_p (rtx_insn *, rtx_insn *);
extern bool nds32_n9_2r1w_mm_to_ex_p (rtx_insn *, rtx_insn *);
extern bool nds32_n9_3r2w_mm_to_ex_p (rtx_insn *, rtx_insn *);
extern bool nds32_n9_last_load_to_ex_p (rtx_insn *, rtx_insn *);

5
gcc/config/nds32/nds32.md
View File

@ -56,9 +56,10 @@
;; ------------------------------------------------------------------------
;; CPU pipeline model.
(define_attr "pipeline_model" "n8,n9,simple"
(define_attr "pipeline_model" "n8,e8,n9,simple"
(const
(cond [(match_test "nds32_cpu_option == CPU_N6 || nds32_cpu_option == CPU_N8") (const_string "n8")
(cond [(match_test "nds32_cpu_option == CPU_E8") (const_string "e8")
(match_test "nds32_cpu_option == CPU_N6 || nds32_cpu_option == CPU_N8") (const_string "n8")
(match_test "nds32_cpu_option == CPU_N9") (const_string "n9")
(match_test "nds32_cpu_option == CPU_SIMPLE") (const_string "simple")]
(const_string "n9"))))

15
gcc/config/nds32/nds32.opt
View File

@ -198,6 +198,21 @@ Enum(nds32_cpu_type) String(s8) Value(CPU_N8)
EnumValue
Enum(nds32_cpu_type) String(s801) Value(CPU_N8)
EnumValue
Enum(nds32_cpu_type) String(e8) Value(CPU_E8)
EnumValue
Enum(nds32_cpu_type) String(e801) Value(CPU_E8)
EnumValue
Enum(nds32_cpu_type) String(n820) Value(CPU_E8)
EnumValue
Enum(nds32_cpu_type) String(s830) Value(CPU_E8)
EnumValue
Enum(nds32_cpu_type) String(e830) Value(CPU_E8)
EnumValue
Enum(nds32_cpu_type) String(n9) Value(CPU_N9)

7
gcc/config/nds32/pipelines.md
View File

@ -23,6 +23,13 @@
;; ------------------------------------------------------------------------
(include "nds32-n8.md")
;; ------------------------------------------------------------------------
;; Include E8 pipeline settings.
;; ------------------------------------------------------------------------
(include "nds32-e8.md")
;; ------------------------------------------------------------------------
;; Include N9/N10 pipeline settings.
;; ------------------------------------------------------------------------