re PR target/92841 (Optimize -fstack-protector-strong code generation a bit)
PR target/92841 * config/i386/i386.md (@stack_protect_set_1_<mode>, @stack_protect_test_1_<mode>): Use output_asm_insn. (*stack_protect_set_2_<mode>, *stack_protect_set_3): New define_insns and corresponding define_peephole2s. * gcc.target/i386/pr92841.c: New test. From-SVN: r279468
This commit is contained in:
Jakub Jelinek
Jakub Jelinek
parent
7ec85098eb
commit
7c32b0d5cc
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@ -1,3 +1,11 @@
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2019-12-17 Jakub Jelinek <jakub@redhat.com>
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PR target/92841
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* config/i386/i386.md (@stack_protect_set_1_<mode>,
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@stack_protect_test_1_<mode>): Use output_asm_insn.
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(*stack_protect_set_2_<mode>, *stack_protect_set_3): New define_insns
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and corresponding define_peephole2s.
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2019-12-17 Jan Hubicka <hubicka@ucw.cz>
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* symtab.c (symtab_node::get_partitioning_class): Aliases of external
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@ -19768,9 +19768,104 @@
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(set (match_scratch:PTR 2 "=&r") (const_int 0))
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(clobber (reg:CC FLAGS_REG))]
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""
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"mov{<imodesuffix>}\t{%1, %2|%2, %1}\;mov{<imodesuffix>}\t{%2, %0|%0, %2}\;xor{l}\t%k2, %k2"
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{
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output_asm_insn ("mov{<imodesuffix>}\t{%1, %2|%2, %1}", operands);
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output_asm_insn ("mov{<imodesuffix>}\t{%2, %0|%0, %2}", operands);
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return "xor{l}\t%k2, %k2";
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}
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[(set_attr "type" "multi")])
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;; Patterns and peephole2s to optimize stack_protect_set_1_<mode>
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;; immediately followed by *mov{s,d}i_internal to the same register,
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;; where we can avoid the xor{l} above. We don't split this, so that
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;; scheduling or anything else doesn't separate the *stack_protect_set*
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;; pattern from the set of the register that overwrites the register
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;; with a new value.
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(define_insn "*stack_protect_set_2_<mode>"
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[(set (match_operand:PTR 0 "memory_operand" "=m")
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(unspec:PTR [(match_operand:PTR 3 "memory_operand" "m")]
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UNSPEC_SP_SET))
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(set (match_operand:SI 1 "register_operand" "=&r")
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(match_operand:SI 2 "general_operand" "g"))
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(clobber (reg:CC FLAGS_REG))]
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"reload_completed
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&& !reg_overlap_mentioned_p (operands[1], operands[2])"
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{
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output_asm_insn ("mov{<imodesuffix>}\t{%3, %<k>1|%<k>1, %3}", operands);
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output_asm_insn ("mov{<imodesuffix>}\t{%<k>1, %0|%0, %<k>1}", operands);
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if (pic_32bit_operand (operands[2], SImode)
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|| ix86_use_lea_for_mov (insn, operands + 1))
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return "lea{l}\t{%E2, %1|%1, %E2}";
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else
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return "mov{l}\t{%2, %1|%1, %2}";
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}
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[(set_attr "type" "multi")
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(set_attr "length" "24")])
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(define_peephole2
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[(parallel [(set (match_operand:PTR 0 "memory_operand")
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(unspec:PTR [(match_operand:PTR 1 "memory_operand")]
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UNSPEC_SP_SET))
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(set (match_operand:PTR 2 "general_reg_operand") (const_int 0))
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(clobber (reg:CC FLAGS_REG))])
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(set (match_operand:SI 3 "general_reg_operand")
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(match_operand:SI 4))]
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"REGNO (operands[2]) == REGNO (operands[3])
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&& (general_reg_operand (operands[4], SImode)
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|| memory_operand (operands[4], SImode)
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|| immediate_operand (operands[4], SImode))
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&& !reg_overlap_mentioned_p (operands[3], operands[4])"
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[(parallel [(set (match_dup 0)
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(unspec:PTR [(match_dup 1)] UNSPEC_SP_SET))
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(set (match_dup 3) (match_dup 4))
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(clobber (reg:CC FLAGS_REG))])])
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(define_insn "*stack_protect_set_3"
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[(set (match_operand:DI 0 "memory_operand" "=m,m,m")
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(unspec:DI [(match_operand:DI 3 "memory_operand" "m,m,m")]
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UNSPEC_SP_SET))
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(set (match_operand:DI 1 "register_operand" "=&r,r,r")
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(match_operand:DI 2 "general_operand" "Z,rem,i"))
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(clobber (reg:CC FLAGS_REG))]
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"TARGET_64BIT
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&& reload_completed
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&& !reg_overlap_mentioned_p (operands[1], operands[2])"
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{
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output_asm_insn ("mov{q}\t{%3, %1|%1, %3}", operands);
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output_asm_insn ("mov{q}\t{%1, %0|%0, %1}", operands);
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if (which_alternative == 0)
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return "mov{l}\t{%k2, %k1|%k1, %k2}";
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else if (which_alternative == 2)
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return "movabs{q}\t{%2, %1|%1, %2}";
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else if (pic_32bit_operand (operands[2], DImode)
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|| ix86_use_lea_for_mov (insn, operands + 1))
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return "lea{q}\t{%E2, %1|%1, %E2}";
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else
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return "mov{q}\t{%2, %1|%1, %2}";
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}
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[(set_attr "type" "multi")
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(set_attr "length" "24")])
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(define_peephole2
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[(parallel [(set (match_operand:DI 0 "memory_operand")
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(unspec:DI [(match_operand:DI 1 "memory_operand")]
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UNSPEC_SP_SET))
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(set (match_operand:DI 2 "general_reg_operand") (const_int 0))
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(clobber (reg:CC FLAGS_REG))])
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(set (match_dup 2) (match_operand:DI 3))]
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"TARGET_64BIT
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&& (general_reg_operand (operands[3], DImode)
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|| memory_operand (operands[3], DImode)
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|| x86_64_zext_immediate_operand (operands[3], DImode)
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|| x86_64_immediate_operand (operands[3], DImode)
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|| (CONSTANT_P (operands[3])
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&& (!flag_pic || LEGITIMATE_PIC_OPERAND_P (operands[3]))))
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&& !reg_overlap_mentioned_p (operands[2], operands[3])"
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[(parallel [(set (match_dup 0)
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(unspec:PTR [(match_dup 1)] UNSPEC_SP_SET))
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(set (match_dup 2) (match_dup 3))
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(clobber (reg:CC FLAGS_REG))])])
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(define_expand "stack_protect_test"
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[(match_operand 0 "memory_operand")
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(match_operand 1 "memory_operand")
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@ -19794,7 +19889,10 @@
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UNSPEC_SP_TEST))
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(clobber (match_scratch:PTR 3 "=&r"))]
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""
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"mov{<imodesuffix>}\t{%1, %3|%3, %1}\;sub{<imodesuffix>}\t{%2, %3|%3, %2}"
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{
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output_asm_insn ("mov{<imodesuffix>}\t{%1, %3|%3, %1}", operands);
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return "sub{<imodesuffix>}\t{%2, %3|%3, %2}";
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}
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[(set_attr "type" "multi")])
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(define_insn "sse4_2_crc32<mode>"
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@ -1,3 +1,8 @@
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2019-12-17 Jakub Jelinek <jakub@redhat.com>
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PR target/92841
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* gcc.target/i386/pr92841.c: New test.
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2019-12-17 Christophe Lyon <christophe.lyon@linaro.org>
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* gcc.target/arm/pr45701-1.c: Adjust for -mpure-code.
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@ -0,0 +1,17 @@
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/* PR target/92841 */
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/* { dg-do compile { target fstack_protector } } */
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/* { dg-options "-O2 -fstack-protector-strong -masm=att" } */
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/* { dg-final { scan-assembler-not "xor\[lq]\t%(\[re]\[a-z0-9]*), %\\1\[\n\r]*\tmov\[lq]\t\[^\n\r]*, %\\1" } } */
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const struct S { int b; } c[] = {30, 12, 20, 0, 11};
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void bar (int *);
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void
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foo (void)
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{
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int e[4];
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const struct S *a;
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for (a = c; a < c + sizeof (c) / sizeof (c[0]); a++)
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if (a->b)
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bar (e);
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}
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