i386.md (QImode patterns): Remove '*' before the 'r' constraints.
* i386.md (QImode patterns): Remove '*' before the 'r' constraints. * i386.h (procesor_costs): Add movzbl_load field. (HARD_REGNO_MODE_OK): Accept QImode on non PARTIAL_REGISTER_STALL in non-Q registers, accept DImode registers anywhere. (Q_CLASS_P): New. (MEMORY_MOVE_COST): Calculate QImode moves correctly. * i386.c (*_cost): Set value for movxbl_load field. From-SVN: r30746
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@ -1,5 +1,13 @@
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Fri Nov 26 10:59:12 CET 1999 Jan Hubicka <hubicka@freesoft.cz>
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* i386.md (QImode patterns): Remove '*' before the 'r' constraints.
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* i386.h (procesor_costs): Add movzbl_load field.
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(HARD_REGNO_MODE_OK): Accept QImode on non PARTIAL_REGISTER_STALL in
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non-Q registers, accept DImode registers anywhere.
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(Q_CLASS_P): New.
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(MEMORY_MOVE_COST): Calculate QImode moves correctly.
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* i386.c (*_cost): Set value for movxbl_load field.
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* (addsi): New add to lea splitter.
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(ashlsi): Likewise.
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(lea to add/shift peep2): New.
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@ -64,6 +64,7 @@ struct processor_costs i386_cost = { /* 386 specific costs */
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1, /* cost of multiply per each bit set */
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23, /* cost of a divide/mod */
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15, /* "large" insn */
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4, /* cost for loading QImode using movzbl */
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{2, 4, 2}, /* cost of loading integer registers
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in QImode, HImode and SImode.
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Relative to reg-reg move (2). */
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@ -83,6 +84,7 @@ struct processor_costs i486_cost = { /* 486 specific costs */
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1, /* cost of multiply per each bit set */
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40, /* cost of a divide/mod */
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15, /* "large" insn */
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4, /* cost for loading QImode using movzbl */
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{2, 4, 2}, /* cost of loading integer registers
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in QImode, HImode and SImode.
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Relative to reg-reg move (2). */
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@ -102,6 +104,7 @@ struct processor_costs pentium_cost = {
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0, /* cost of multiply per each bit set */
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25, /* cost of a divide/mod */
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8, /* "large" insn */
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6, /* cost for loading QImode using movzbl */
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{2, 4, 2}, /* cost of loading integer registers
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in QImode, HImode and SImode.
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Relative to reg-reg move (2). */
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@ -121,6 +124,7 @@ struct processor_costs pentiumpro_cost = {
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0, /* cost of multiply per each bit set */
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17, /* cost of a divide/mod */
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8, /* "large" insn */
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2, /* cost for loading QImode using movzbl */
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{4, 4, 4}, /* cost of loading integer registers
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in QImode, HImode and SImode.
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Relative to reg-reg move (2). */
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@ -140,6 +144,7 @@ struct processor_costs k6_cost = {
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0, /* cost of multiply per each bit set */
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18, /* cost of a divide/mod */
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8, /* "large" insn */
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3, /* cost for loading QImode using movzbl */
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{4, 5, 4}, /* cost of loading integer registers
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in QImode, HImode and SImode.
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Relative to reg-reg move (2). */
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@ -62,6 +62,7 @@ struct processor_costs {
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int mult_bit; /* cost of multiply per each bit set */
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int divide; /* cost of a divide/mod */
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int large_insn; /* insns larger than this cost more */
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int movzbl_load; /* cost of loading using movzbl */
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int int_load[3]; /* cost of loading integer registers
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in QImode, HImode and SImode relative
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to reg-reg move (2). */
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@ -704,13 +705,11 @@ extern int ix86_arch;
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? ((GET_MODE_CLASS (MODE) == MODE_FLOAT \
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|| GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
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&& GET_MODE_UNIT_SIZE (MODE) <= (LONG_DOUBLE_TYPE_SIZE == 96 ? 12 : 8))\
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/* Only allow DImode in even registers. */ \
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: (MODE) == DImode && ((REGNO) & 1) ? 0 \
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/* The first four integer regs can hold any mode. */ \
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: (REGNO) < 4 ? 1 \
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/* Other regs cannot do byte accesses. */ \
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: (MODE) != QImode ? 1 \
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: reload_in_progress || reload_completed)
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: reload_in_progress || reload_completed \
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|| !TARGET_PARTIAL_REG_STALL)
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/* Value is 1 if it is a good idea to tie two pseudo registers
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when one has mode MODE1 and one has mode MODE2.
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@ -843,6 +842,8 @@ enum reg_class
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#define FLOAT_CLASS_P(CLASS) (reg_class_subset_p (CLASS, FLOAT_REGS))
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#define Q_CLASS_P(CLASS) (reg_class_subset_p (CLASS, Q_REGS))
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/* Give names of register classes as strings for dump file. */
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#define REG_CLASS_NAMES \
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@ -1993,7 +1994,11 @@ while (0)
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If moving between registers and memory is more expensive than
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between two registers, you should define this macro to express the
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relative cost. */
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relative cost.
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Model also increased moving costs of QImode registers in non
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Q_REGS classes.
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*/
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#define MEMORY_MOVE_COST(MODE,CLASS,IN) \
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(FLOAT_CLASS_P (CLASS) \
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@ -2003,7 +2008,10 @@ while (0)
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? (IN ? ix86_cost->fp_load[1] : ix86_cost->fp_store[1]) \
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: (IN ? ix86_cost->fp_load[2] : ix86_cost->fp_store[2]))) \
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: (GET_MODE_SIZE (MODE)==1 \
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? (IN ? ix86_cost->int_load[0] : ix86_cost->int_store[0]) \
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? (IN ? (Q_CLASS_P (CLASS) ? ix86_cost->int_load[0] \
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: ix86_cost->movzbl_load) \
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: (Q_CLASS_P (CLASS) ? ix86_cost->int_store[0] \
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: ix86_cost->int_store[0] + 4)) \
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: (GET_MODE_SIZE (MODE)==2 \
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? (IN ? ix86_cost->int_load[1] : ix86_cost->int_store[1]) \
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: ((IN ? ix86_cost->int_load[2] : ix86_cost->int_store[2]) \
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@ -1348,8 +1348,8 @@
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(set_attr "length_prefix" "1")])
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(define_insn "*movqi_1"
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[(set (match_operand:QI 0 "nonimmediate_operand" "=q,q,*r,*r,m")
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(match_operand:QI 1 "general_operand" "qn,qm,*rn,qm,qn"))]
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[(set (match_operand:QI 0 "nonimmediate_operand" "=q,q,r,?r,m")
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(match_operand:QI 1 "general_operand" "qn,qm,rn,qm,qn"))]
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"GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
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"*
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{
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@ -1454,8 +1454,8 @@
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[(set_attr "type" "imovx")])
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(define_insn "*movqi_extv_1"
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[(set (match_operand:QI 0 "nonimmediate_operand" "=qm*r")
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(sign_extract:QI (match_operand:SI 1 "register_operand" "q")
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[(set (match_operand:QI 0 "nonimmediate_operand" "=qm,?r")
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(sign_extract:QI (match_operand:SI 1 "register_operand" "q,q")
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(const_int 8)
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(const_int 8)))]
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""
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[(set_attr "type" "imovx")])
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(define_insn "*movqi_extzv_1"
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[(set (match_operand:QI 0 "nonimmediate_operand" "=qm*r")
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(subreg:QI (zero_extract:SI (match_operand 1 "ext_register_operand" "q")
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[(set (match_operand:QI 0 "nonimmediate_operand" "=qm,?r")
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(subreg:QI (zero_extract:SI (match_operand 1 "ext_register_operand" "q,q")
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(const_int 8)
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(const_int 8)) 0))]
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""
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@ -3295,9 +3295,9 @@
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;; %%% Potential partial reg stall on alternative 2. What to do?
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(define_insn "*addqi_1"
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[(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,*r")
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[(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,r")
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(plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
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(match_operand:QI 2 "general_operand" "qn,qmn,*rn")))
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(match_operand:QI 2 "general_operand" "qn,qmn,rn")))
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(clobber (reg:CC 17))]
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"ix86_binary_operator_ok (PLUS, QImode, operands)"
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"*
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@ -4366,9 +4366,9 @@
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;; %%% Potential partial reg stall on alternative 2. What to do?
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(define_insn "*andqi_1"
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[(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,*r")
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[(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,r")
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(and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
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(match_operand:QI 2 "general_operand" "qi,qmi,*ri")))
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(match_operand:QI 2 "general_operand" "qi,qmi,ri")))
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(clobber (reg:CC 17))]
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"ix86_binary_operator_ok (AND, QImode, operands)"
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"@
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;; %%% Potential partial reg stall on alternative 2. What to do?
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(define_insn "*iorqi_1"
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[(set (match_operand:QI 0 "nonimmediate_operand" "=q,m,*r")
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[(set (match_operand:QI 0 "nonimmediate_operand" "=q,m,r")
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(ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
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(match_operand:QI 2 "general_operand" "qmi,qi,*ri")))
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(match_operand:QI 2 "general_operand" "qmi,qi,ri")))
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(clobber (reg:CC 17))]
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"ix86_binary_operator_ok (IOR, QImode, operands)"
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"@
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@ -4659,9 +4659,9 @@
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;; %%% Potential partial reg stall on alternative 2. What to do?
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(define_insn "*xorqi_1"
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[(set (match_operand:QI 0 "nonimmediate_operand" "=q,m,*r")
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[(set (match_operand:QI 0 "nonimmediate_operand" "=q,m,r")
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(xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
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(match_operand:QI 2 "general_operand" "qmi,qi,*ri")))
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(match_operand:QI 2 "general_operand" "qmi,qi,ri")))
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(clobber (reg:CC 17))]
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"ix86_binary_operator_ok (XOR, QImode, operands)"
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"@
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"ix86_expand_unary_operator (NOT, QImode, operands); DONE;")
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(define_insn "*one_cmplqi2_1"
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[(set (match_operand:QI 0 "nonimmediate_operand" "=qm,*r")
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[(set (match_operand:QI 0 "nonimmediate_operand" "=qm,r")
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(not:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")))]
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"ix86_unary_operator_ok (NEG, QImode, operands)"
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"@
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