Generate 'fone' and 'fones' sparc instructions when possible.
* config/sparc/constraints.md (C, P, Z): New constraints for const_doube, const_int, and const_vector "all ones" values. Make unused constraint letters comment match reality. * config/sparc/predicates.md (const_all_ones_operand, register_or_zero_or_all_ones_operand): New predicates. * config/sparc/sparc.c (sparc_expand_move): Allow all ones as well as zero constants when VIS. (sparc_legitimate_constant_p): Likewise. * config/sparc/sparc.md (movsi_insn): Add fones alternative. (movsf_insn): Likewise (movdi_insn_sp64): Add fone alternative. (movdf_insn_sp32_v9): Likewise. (movdf_insn_sp64): Likewise. From-SVN: r179173
This commit is contained in:
David S. Miller
David S. Miller
parent
a0ce4616fb
commit
7cbcf85bf9
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@ -1,3 +1,19 @@
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2011-09-25 David S. Miller <davem@davemloft.net>
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* config/sparc/constraints.md (C, P, Z): New constraints for
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const_doube, const_int, and const_vector "all ones" values.
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Make unused constraint letters comment match reality.
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* config/sparc/predicates.md (const_all_ones_operand,
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register_or_zero_or_all_ones_operand): New predicates.
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* config/sparc/sparc.c (sparc_expand_move): Allow all ones
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as well as zero constants when VIS.
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(sparc_legitimate_constant_p): Likewise.
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* config/sparc/sparc.md (movsi_insn): Add fones alternative.
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(movsf_insn): Likewise
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(movdi_insn_sp64): Add fone alternative.
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(movdf_insn_sp32_v9): Likewise.
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(movdf_insn_sp64): Likewise.
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2011-09-25 Jakub Jelinek <jakub@redhat.com>
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* tree-ssa-structalias.c (intra_create_variable_infos): Treat
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@ -18,7 +18,7 @@
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;; <http://www.gnu.org/licenses/>.
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;;; Unused letters:
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;;; ABCD P Z
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;;; AB
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;;; a jkl q tuvwxyz
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@ -52,6 +52,10 @@
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(and (match_code "const_double")
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(match_test "const_zero_operand (op, mode)")))
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(define_constraint "C"
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"The floating-point all-ones constant"
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(and (match_code "const_double")
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(match_test "const_all_ones_operand (op, mode)")))
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;; Integer constant constraints
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@ -95,6 +99,10 @@
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(and (match_code "const_int")
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(match_test "ival == 4096")))
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(define_constraint "P"
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"The integer constant -1"
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(and (match_code "const_int")
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(match_test "ival == -1")))
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;; Extra constraints
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;; Our memory extra constraints have to emulate the behavior of 'm' and 'o',
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@ -146,3 +154,8 @@
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"The vector zero constant"
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(and (match_code "const_vector")
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(match_test "const_zero_operand (op, mode)")))
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(define_constraint "Z"
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"The vector all ones constant"
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(and (match_code "const_vector")
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(match_test "const_all_ones_operand (op, mode)")))
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@ -29,6 +29,35 @@
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(and (match_code "const_int,const_double,const_vector")
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(match_test "op == CONST1_RTX (mode)")))
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;; Return true if the integer representation of OP is
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;; all-ones.
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(define_predicate "const_all_ones_operand"
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(match_code "const_int,const_double,const_vector")
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{
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if (GET_CODE (op) == CONST_INT && INTVAL (op) == -1)
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return true;
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#if HOST_BITS_PER_WIDE_INT == 32
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if (GET_CODE (op) == CONST_DOUBLE
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&& GET_MODE (op) == VOIDmode
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&& CONST_DOUBLE_HIGH (op) == ~(HOST_WIDE_INT)0
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&& CONST_DOUBLE_LOW (op) == ~(HOST_WIDE_INT)0)
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return true;
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#endif
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if (GET_CODE (op) == CONST_VECTOR)
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{
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int i, num_elem = CONST_VECTOR_NUNITS (op);
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for (i = 0; i < num_elem; i++)
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{
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rtx n = CONST_VECTOR_ELT (op, i);
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if (! const_all_ones_operand (n, mode))
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return false;
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}
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return true;
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}
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return false;
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})
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;; Return true if OP is the integer constant 4096.
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(define_predicate "const_4096_operand"
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(and (match_code "const_int")
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@ -211,6 +240,12 @@
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(ior (match_operand 0 "register_operand")
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(match_operand 0 "const_zero_operand")))
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;; Return true if OP is either the zero constant, the all-ones
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;; constant, or a register.
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(define_predicate "register_or_zero_or_all_ones_operand"
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(ior (match_operand 0 "register_or_zero_operand")
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(match_operand 0 "const_all_ones_operand")))
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;; Return true if OP is a register operand in a floating point register.
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(define_predicate "fp_register_operand"
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(match_operand 0 "register_operand")
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@ -1170,9 +1170,11 @@ sparc_expand_move (enum machine_mode mode, rtx *operands)
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if (operands [1] == const0_rtx)
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operands[1] = CONST0_RTX (mode);
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/* We can clear FP registers if TARGET_VIS, and always other regs. */
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/* We can clear or set to all-ones FP registers if TARGET_VIS, and
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always other regs. */
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if ((TARGET_VIS || REGNO (operands[0]) < SPARC_FIRST_FP_REG)
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&& const_zero_operand (operands[1], mode))
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&& (const_zero_operand (operands[1], mode)
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|| const_all_ones_operand (operands[1], mode)))
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return false;
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if (REGNO (operands[0]) < SPARC_FIRST_FP_REG
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@ -3096,19 +3098,21 @@ sparc_legitimate_constant_p (enum machine_mode mode, rtx x)
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return true;
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/* Floating point constants are generally not ok.
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The only exception is 0.0 in VIS. */
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The only exception is 0.0 and all-ones in VIS. */
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if (TARGET_VIS
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&& SCALAR_FLOAT_MODE_P (mode)
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&& const_zero_operand (x, mode))
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&& (const_zero_operand (x, mode)
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|| const_all_ones_operand (x, mode)))
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return true;
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return false;
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case CONST_VECTOR:
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/* Vector constants are generally not ok.
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The only exception is 0 in VIS. */
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The only exception is 0 or -1 in VIS. */
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if (TARGET_VIS
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&& const_zero_operand (x, mode))
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&& (const_zero_operand (x, mode)
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|| const_all_ones_operand (x, mode)))
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return true;
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return false;
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@ -1303,10 +1303,10 @@
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})
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(define_insn "*movsi_insn"
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[(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,m,!f,!f,!m,d")
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(match_operand:SI 1 "input_operand" "rI,K,m,rJ,f,m,f,J"))]
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[(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,m,!f,!f,!m,d,d")
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(match_operand:SI 1 "input_operand" "rI,K,m,rJ,f,m,f,J,P"))]
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"(register_operand (operands[0], SImode)
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|| register_or_zero_operand (operands[1], SImode))"
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|| register_or_zero_or_all_ones_operand (operands[1], SImode))"
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"@
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mov\t%1, %0
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sethi\t%%hi(%a1), %0
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@ -1315,8 +1315,9 @@
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fmovs\t%1, %0
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ld\t%1, %0
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st\t%1, %0
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fzeros\t%0"
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[(set_attr "type" "*,*,load,store,fpmove,fpload,fpstore,fga")])
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fzeros\t%0
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fones\t%0"
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[(set_attr "type" "*,*,load,store,fpmove,fpload,fpstore,fga,fga")])
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(define_insn "*movsi_lo_sum"
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[(set (match_operand:SI 0 "register_operand" "=r")
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@ -1505,11 +1506,11 @@
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(set_attr "fptype" "*,*,*,*,*,*,*,*,*,*,*,*,double,*,*")])
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(define_insn "*movdi_insn_sp64"
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[(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,m,?e,?e,?W,b")
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(match_operand:DI 1 "input_operand" "rI,N,m,rJ,e,W,e,J"))]
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[(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,m,?e,?e,?W,b,b")
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(match_operand:DI 1 "input_operand" "rI,N,m,rJ,e,W,e,J,P"))]
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"TARGET_ARCH64
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&& (register_operand (operands[0], DImode)
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|| register_or_zero_operand (operands[1], DImode))"
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|| register_or_zero_or_all_ones_operand (operands[1], DImode))"
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"@
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mov\t%1, %0
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sethi\t%%hi(%a1), %0
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@ -1518,9 +1519,10 @@
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fmovd\t%1, %0
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ldd\t%1, %0
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std\t%1, %0
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fzero\t%0"
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[(set_attr "type" "*,*,load,store,fpmove,fpload,fpstore,fga")
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(set_attr "fptype" "*,*,*,*,double,*,*,double")])
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fzero\t%0
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fone\t%0"
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[(set_attr "type" "*,*,load,store,fpmove,fpload,fpstore,fga,fga")
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(set_attr "fptype" "*,*,*,*,double,*,*,double,double")])
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(define_expand "movdi_pic_label_ref"
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[(set (match_dup 3) (high:DI
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@ -1918,16 +1920,16 @@
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})
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(define_insn "*movsf_insn"
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[(set (match_operand:V32 0 "nonimmediate_operand" "=d,f,*r,*r,*r,f,*r,m,m")
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(match_operand:V32 1 "input_operand" "GY,f,*rRY,Q,S,m,m,f,*rGY"))]
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[(set (match_operand:V32 0 "nonimmediate_operand" "=d,d,f,*r,*r,*r,f,*r,m,m")
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(match_operand:V32 1 "input_operand" "GY,ZC,f,*rRY,Q,S,m,m,f,*rGY"))]
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"TARGET_FPU
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&& (register_operand (operands[0], <V32:MODE>mode)
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|| register_or_zero_operand (operands[1], <V32:MODE>mode))"
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|| register_or_zero_or_all_ones_operand (operands[1], <V32:MODE>mode))"
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{
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if (GET_CODE (operands[1]) == CONST_DOUBLE
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&& (which_alternative == 2
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|| which_alternative == 3
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|| which_alternative == 4))
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&& (which_alternative == 3
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|| which_alternative == 4
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|| which_alternative == 5))
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{
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REAL_VALUE_TYPE r;
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long i;
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@ -1942,24 +1944,26 @@
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case 0:
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return "fzeros\t%0";
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case 1:
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return "fmovs\t%1, %0";
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return "fones\t%0";
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case 2:
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return "mov\t%1, %0";
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return "fmovs\t%1, %0";
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case 3:
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return "sethi\t%%hi(%a1), %0";
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return "mov\t%1, %0";
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case 4:
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return "#";
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return "sethi\t%%hi(%a1), %0";
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case 5:
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return "#";
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case 6:
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return "ld\t%1, %0";
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case 7:
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return "ld\t%1, %0";
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case 8:
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case 9:
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return "st\t%r1, %0";
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default:
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gcc_unreachable ();
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}
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}
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[(set_attr "type" "fga,fpmove,*,*,*,fpload,load,fpstore,store")])
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[(set_attr "type" "fga,fga,fpmove,*,*,*,fpload,load,fpstore,store")])
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;; Exactly the same as above, except that all `f' cases are deleted.
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;; This is necessary to prevent reload from ever trying to use a `f' reg
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@ -2091,15 +2095,16 @@
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;; We have available v9 double floats but not 64-bit integer registers.
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(define_insn "*movdf_insn_sp32_v9"
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[(set (match_operand:V64 0 "nonimmediate_operand" "=b,e,e,T,W,U,T,f,*r,o")
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(match_operand:V64 1 "input_operand" "GY,e,W#F,GY,e,T,U,o#F,*roGYDF,*rGYf"))]
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[(set (match_operand:V64 0 "nonimmediate_operand" "=b,b,e,e,T,W,U,T,f,*r,o")
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(match_operand:V64 1 "input_operand" "GY,ZC,e,W#F,GY,e,T,U,o#F,*roGYDF,*rGYf"))]
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"TARGET_FPU
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&& TARGET_V9
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&& ! TARGET_ARCH64
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&& (register_operand (operands[0], <V64:MODE>mode)
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|| register_or_zero_operand (operands[1], <V64:MODE>mode))"
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|| register_or_zero_or_all_ones_operand (operands[1], <V64:MODE>mode))"
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"@
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fzero\t%0
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fone\t%0
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fmovd\t%1, %0
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ldd\t%1, %0
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stx\t%r1, %0
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@ -2109,9 +2114,9 @@
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#
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#
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#"
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[(set_attr "type" "fga,fpmove,load,store,store,load,store,*,*,*")
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(set_attr "length" "*,*,*,*,*,*,*,2,2,2")
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(set_attr "fptype" "double,double,*,*,*,*,*,*,*,*")])
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[(set_attr "type" "fga,fga,fpmove,load,store,store,load,store,*,*,*")
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(set_attr "length" "*,*,*,*,*,*,*,*,2,2,2")
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(set_attr "fptype" "double,double,double,*,*,*,*,*,*,*,*")])
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(define_insn "*movdf_insn_sp32_v9_no_fpu"
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[(set (match_operand:DF 0 "nonimmediate_operand" "=U,T,T,r,o")
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@ -2132,14 +2137,15 @@
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;; We have available both v9 double floats and 64-bit integer registers.
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(define_insn "*movdf_insn_sp64"
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[(set (match_operand:V64 0 "nonimmediate_operand" "=b,e,e,W,*r,*r,m,*r")
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(match_operand:V64 1 "input_operand" "GY,e,W#F,e,*rGY,m,*rGY,DF"))]
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[(set (match_operand:V64 0 "nonimmediate_operand" "=b,b,e,e,W,*r,*r,m,*r")
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(match_operand:V64 1 "input_operand" "GY,ZC,e,W#F,e,*rGY,m,*rGY,DF"))]
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"TARGET_FPU
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&& TARGET_ARCH64
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&& (register_operand (operands[0], <V64:MODE>mode)
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|| register_or_zero_operand (operands[1], <V64:MODE>mode))"
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|| register_or_zero_or_all_ones_operand (operands[1], <V64:MODE>mode))"
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"@
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fzero\t%0
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fone\t%0
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fmovd\t%1, %0
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ldd\t%1, %0
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std\t%1, %0
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@ -2147,9 +2153,9 @@
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ldx\t%1, %0
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stx\t%r1, %0
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#"
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[(set_attr "type" "fga,fpmove,load,store,*,load,store,*")
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(set_attr "length" "*,*,*,*,*,*,*,2")
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(set_attr "fptype" "double,double,*,*,*,*,*,*")])
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[(set_attr "type" "fga,fga,fpmove,load,store,*,load,store,*")
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(set_attr "length" "*,*,*,*,*,*,*,*,2")
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(set_attr "fptype" "double,double,double,*,*,*,*,*,*")])
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(define_insn "*movdf_insn_sp64_no_fpu"
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[(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m")
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