I6400 scheduling.
gcc/
* config/mips/i6400.md: New file.
* config/mips/mips-cpus.def (mips32r6): Change to PROCESSOR_I6400.
(mips64r6): Likewise.
(i6400): Define.
* config/mips/mips-tables.opt: Regenerate.
* config/mips/mips.c (mips_rtx_cost_data): Add I6400 processor.
(mips_issue_rate): Add support for i6400.
(mips_multipass_dfa_lookahead): Likewise.
* config/mips/mips.h (TUNE_I6400): Define.
* config/mips/mips.md: Include i6400.md.
(processor): Add i6400.
* doc/invoke.texi (-march=@var{arch}): Add i6400.
From-SVN: r226090
This commit is contained in:
Prachi Godbole
Robert Suchanek
parent
2fde61e3ca
commit
7ccb4e4e6a
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@ -1,3 +1,18 @@
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2015-07-23 Prachi Godbole <prachi.godbole@imgtec.com>
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* config/mips/i6400.md: New file.
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* config/mips/mips-cpus.def (mips32r6): Change to PROCESSOR_I6400.
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(mips64r6): Likewise.
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(i6400): Define.
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* config/mips/mips-tables.opt: Regenerate.
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* config/mips/mips.c (mips_rtx_cost_data): Add I6400 processor.
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(mips_issue_rate): Add support for i6400.
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(mips_multipass_dfa_lookahead): Likewise.
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* config/mips/mips.h (TUNE_I6400): Define.
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* config/mips/mips.md: Include i6400.md.
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(processor): Add i6400.
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* doc/invoke.texi (-march=@var{arch}): Add i6400.
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2015-07-23 Richard Biener <rguenther@suse.de>
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PR middle-end/66916
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@ -0,0 +1,142 @@
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;; DFA-based pipeline description for I6400.
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;;
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;; Copyright (C) 2015 Free Software Foundation, Inc.
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;;
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;; This file is part of GCC.
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;;
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;; GCC is free software; you can redistribute it and/or modify it
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;; under the terms of the GNU General Public License as published
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;; by the Free Software Foundation; either version 3, or (at your
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;; option) any later version.
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;; GCC is distributed in the hope that it will be useful, but WITHOUT
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;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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;; License for more details.
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3. If not see
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;; <http://www.gnu.org/licenses/>.
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(define_automaton "i6400_int_pipe, i6400_mdu_pipe, i6400_fpu_short_pipe,
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i6400_fpu_long_pipe")
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(define_cpu_unit "i6400_gpmuldiv" "i6400_mdu_pipe")
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(define_cpu_unit "i6400_agen, i6400_alu1, i6400_lsu" "i6400_int_pipe")
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(define_cpu_unit "i6400_control, i6400_ctu, i6400_alu0" "i6400_int_pipe")
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;; Short FPU pipeline.
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(define_cpu_unit "i6400_fpu_short" "i6400_fpu_short_pipe")
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;; Long FPU pipeline.
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(define_cpu_unit "i6400_fpu_long, i6400_fpu_apu" "i6400_fpu_long_pipe")
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(define_reservation "i6400_control_ctu" "i6400_control, i6400_ctu")
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(define_reservation "i6400_control_alu0" "i6400_control, i6400_alu0")
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(define_reservation "i6400_agen_lsu" "i6400_agen, i6400_lsu")
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(define_reservation "i6400_agen_alu1" "i6400_agen, i6400_alu1")
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;;
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;; FPU pipe
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;;
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;; fabs, fneg
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(define_insn_reservation "i6400_fpu_fabs" 1
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(and (eq_attr "cpu" "i6400")
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(eq_attr "type" "fabs,fneg,fmove"))
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"i6400_fpu_short, i6400_fpu_apu")
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;; fadd, fsub, fcvt
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(define_insn_reservation "i6400_fpu_fadd" 4
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(and (eq_attr "cpu" "i6400")
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(eq_attr "type" "fadd, fcvt"))
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"i6400_fpu_long, i6400_fpu_apu")
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;; fmul
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(define_insn_reservation "i6400_fpu_fmul" 5
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(and (eq_attr "cpu" "i6400")
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(eq_attr "type" "fmul"))
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"i6400_fpu_long, i6400_fpu_apu")
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;; div, sqrt (Double Precision)
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(define_insn_reservation "i6400_fpu_div_df" 30
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(and (eq_attr "cpu" "i6400")
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(and (eq_attr "mode" "DF")
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(eq_attr "type" "fdiv,frdiv,fsqrt,frsqrt")))
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"i6400_fpu_long+i6400_fpu_apu*30")
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;; div, sqrt (Single Precision)
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(define_insn_reservation "i6400_fpu_div_sf" 22
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(and (eq_attr "cpu" "i6400")
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(eq_attr "type" "fdiv,frdiv,fsqrt,frsqrt"))
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"i6400_fpu_long+i6400_fpu_apu*22")
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;;
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;; Integer pipe
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;;
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;; and, lui, shifts, seb, seh
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(define_insn_reservation "i6400_int_logical" 1
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(and (eq_attr "cpu" "i6400")
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(eq_attr "move_type" "logical,const,andi,sll0,signext"))
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"i6400_control_alu0 | i6400_agen_alu1")
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;; addi, addiu, ori, xori, add, addu, sub, nor
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(define_insn_reservation "i6400_int_add" 1
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(and (eq_attr "cpu" "i6400")
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(eq_attr "alu_type" "add,sub,or,xor,nor"))
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"i6400_control_alu0 | i6400_agen_alu1")
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;; shifts, clo, clz, cond move, arith
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(define_insn_reservation "i6400_int_arith" 1
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(and (eq_attr "cpu" "i6400")
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(eq_attr "type" "shift,slt,move,clz,condmove,arith"))
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"i6400_control_alu0 | i6400_agen_alu1")
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;; nop
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(define_insn_reservation "i6400_int_nop" 0
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(and (eq_attr "cpu" "i6400")
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(eq_attr "type" "nop"))
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"nothing")
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;; mult, multu, mul
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(define_insn_reservation "i6400_int_mult" 4
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(and (eq_attr "cpu" "i6400")
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(eq_attr "type" "imul3,imul"))
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"i6400_gpmuldiv")
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;; divide
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(define_insn_reservation "i6400_int_div" 32
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(and (eq_attr "cpu" "i6400")
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(eq_attr "type" "idiv"))
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"i6400_gpmuldiv*32")
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;; Load lb, lbu, lh, lhu, lq, lw, lw_i2f, lwxs
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(define_insn_reservation "i6400_int_load" 3
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(and (eq_attr "cpu" "i6400")
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(eq_attr "move_type" "load"))
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"i6400_agen_lsu")
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;; store
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(define_insn_reservation "i6400_int_store" 1
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(and (eq_attr "cpu" "i6400")
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(eq_attr "move_type" "store"))
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"i6400_agen_lsu")
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;; prefetch
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(define_insn_reservation "i6400_int_prefetch" 3
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(and (eq_attr "cpu" "i6400")
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(eq_attr "type" "prefetch"))
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"i6400_agen_lsu")
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;; branch and jump
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(define_insn_reservation "i6400_int_branch" 1
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(and (eq_attr "cpu" "i6400")
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(eq_attr "type" "branch,jump"))
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"i6400_control_ctu")
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;; call
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(define_insn_reservation "i6400_int_call" 1
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(and (eq_attr "cpu" "i6400")
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(eq_attr "jal" "indirect,direct"))
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"i6400_control_ctu")
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@ -50,13 +50,13 @@ MIPS_CPU ("mips32r2", PROCESSOR_74KF2_1, 33, PTF_AVOID_BRANCHLIKELY)
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as mips32r2. */
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MIPS_CPU ("mips32r3", PROCESSOR_M4K, 34, PTF_AVOID_BRANCHLIKELY)
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MIPS_CPU ("mips32r5", PROCESSOR_P5600, 36, PTF_AVOID_BRANCHLIKELY)
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MIPS_CPU ("mips32r6", PROCESSOR_W32, 37, PTF_AVOID_BRANCHLIKELY)
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MIPS_CPU ("mips32r6", PROCESSOR_I6400, 37, 0)
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MIPS_CPU ("mips64", PROCESSOR_5KC, 64, PTF_AVOID_BRANCHLIKELY)
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/* ??? For now just tune the generic MIPS64r2 and above for 5KC as well. */
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MIPS_CPU ("mips64r2", PROCESSOR_5KC, 65, PTF_AVOID_BRANCHLIKELY)
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MIPS_CPU ("mips64r3", PROCESSOR_5KC, 66, PTF_AVOID_BRANCHLIKELY)
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MIPS_CPU ("mips64r5", PROCESSOR_5KC, 68, PTF_AVOID_BRANCHLIKELY)
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MIPS_CPU ("mips64r6", PROCESSOR_W64, 69, PTF_AVOID_BRANCHLIKELY)
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MIPS_CPU ("mips64r6", PROCESSOR_I6400, 69, 0)
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/* MIPS I processors. */
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MIPS_CPU ("r3000", PROCESSOR_R3000, 1, 0)
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@ -170,3 +170,6 @@ MIPS_CPU ("octeon+", PROCESSOR_OCTEON, 65, PTF_AVOID_BRANCHLIKELY)
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MIPS_CPU ("octeon2", PROCESSOR_OCTEON2, 65, PTF_AVOID_BRANCHLIKELY)
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MIPS_CPU ("octeon3", PROCESSOR_OCTEON3, 65, PTF_AVOID_BRANCHLIKELY)
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MIPS_CPU ("xlp", PROCESSOR_XLP, 65, PTF_AVOID_BRANCHLIKELY)
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/* MIPS64 Release 6 processors. */
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MIPS_CPU ("i6400", PROCESSOR_I6400, 69, 0)
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@ -693,3 +693,5 @@ Enum(mips_arch_opt_value) String(octeon3) Value(100) Canonical
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EnumValue
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Enum(mips_arch_opt_value) String(xlp) Value(101) Canonical
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EnumValue
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Enum(mips_arch_opt_value) String(i6400) Value(102) Canonical
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@ -1293,6 +1293,19 @@ static const struct mips_rtx_cost_data
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COSTS_N_INSNS (68), /* int_div_di */
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1, /* branch_cost */
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4 /* memory_latency */
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},
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{ /* I6400 */
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COSTS_N_INSNS (4), /* fp_add */
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COSTS_N_INSNS (5), /* fp_mult_sf */
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COSTS_N_INSNS (5), /* fp_mult_df */
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COSTS_N_INSNS (32), /* fp_div_sf */
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COSTS_N_INSNS (32), /* fp_div_df */
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COSTS_N_INSNS (5), /* int_mult_si */
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COSTS_N_INSNS (5), /* int_mult_di */
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COSTS_N_INSNS (36), /* int_div_si */
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COSTS_N_INSNS (36), /* int_div_di */
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2, /* branch_cost */
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4 /* memory_latency */
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}
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};
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@ -13687,6 +13700,7 @@ mips_issue_rate (void)
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case PROCESSOR_OCTEON:
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case PROCESSOR_OCTEON2:
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case PROCESSOR_OCTEON3:
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case PROCESSOR_I6400:
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return 2;
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case PROCESSOR_SB1:
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@ -13836,7 +13850,7 @@ mips_multipass_dfa_lookahead (void)
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if (TUNE_OCTEON)
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return 2;
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if (TUNE_P5600)
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if (TUNE_P5600 || TUNE_I6400)
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return 4;
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return 0;
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@ -277,6 +277,7 @@ struct mips_cpu_info {
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#define TUNE_SB1 (mips_tune == PROCESSOR_SB1 \
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|| mips_tune == PROCESSOR_SB1A)
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#define TUNE_P5600 (mips_tune == PROCESSOR_P5600)
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#define TUNE_I6400 (mips_tune == PROCESSOR_I6400)
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/* Whether vector modes and intrinsics for ST Microelectronics
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Loongson-2E/2F processors should be enabled. In o32 pairs of
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@ -732,7 +733,7 @@ struct mips_cpu_info {
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%{march=mips64r2|march=loongson3a|march=octeon|march=xlp: -mips64r2} \
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%{march=mips64r3: -mips64r3} \
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%{march=mips64r5: -mips64r5} \
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%{march=mips64r6: -mips64r6}}"
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%{march=mips64r6|march=i6400: -mips64r6}}"
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/* A spec that injects the default multilib ISA if no architecture is
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specified. */
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@ -70,6 +70,7 @@
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w32
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w64
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m5100
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i6400
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])
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(define_c_enum "unspec" [
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@ -1086,6 +1087,7 @@
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(eq_attr "type" "ghost")
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"nothing")
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(include "i6400.md")
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(include "p5600.md")
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(include "m5100.md")
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(include "4k.md")
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@ -17041,6 +17041,7 @@ The processor names are:
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@samp{34kc}, @samp{34kf2_1}, @samp{34kf1_1}, @samp{34kn},
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@samp{74kc}, @samp{74kf2_1}, @samp{74kf1_1}, @samp{74kf3_2},
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@samp{1004kc}, @samp{1004kf2_1}, @samp{1004kf1_1},
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@samp{i6400},
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@samp{interaptiv},
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@samp{loongson2e}, @samp{loongson2f}, @samp{loongson3a},
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@samp{m4k},
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