[AArch64] Use SVE reversed shifts in preference to MOVPRFX
This patch makes us use reversed SVE shifts when the first operand can't be tied to the output but the second can. This is tested more thoroughly by the ACLE patches but is really an independent improvement. 2019-08-15 Richard Sandiford <richard.sandiford@arm.com> Prathamesh Kulkarni <prathamesh.kulkarni@linaro.org> gcc/ * config/aarch64/aarch64-sve.md (*v<ASHIFT:optab><SVE_I:mode>3): Add an alternative that uses reversed shifts. gcc/testsuite/ * gcc.target/aarch64/sve/shift_1.c: Accept reversed shifts. Co-Authored-By: Prathamesh Kulkarni <prathamesh.kulkarni@linaro.org> From-SVN: r274512
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@ -1,3 +1,9 @@
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2019-08-15 Richard Sandiford <richard.sandiford@arm.com>
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Prathamesh Kulkarni <prathamesh.kulkarni@linaro.org>
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* config/aarch64/aarch64-sve.md (*v<ASHIFT:optab><SVE_I:mode>3):
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Add an alternative that uses reversed shifts.
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2019-08-15 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
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* config/aarch64/aarch64-cores.def (cortex-a76): Use neoversen1 tuning
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@ -2455,23 +2455,24 @@
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;; likely to gain much and would make the instruction seem less uniform
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;; to the register allocator.
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(define_insn_and_split "*v<optab><mode>3"
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[(set (match_operand:SVE_I 0 "register_operand" "=w, w, ?&w")
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[(set (match_operand:SVE_I 0 "register_operand" "=w, w, w, ?&w")
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(unspec:SVE_I
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[(match_operand:<VPRED> 1 "register_operand" "Upl, Upl, Upl")
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[(match_operand:<VPRED> 1 "register_operand" "Upl, Upl, Upl, Upl")
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(ASHIFT:SVE_I
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(match_operand:SVE_I 2 "register_operand" "w, 0, w")
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(match_operand:SVE_I 3 "aarch64_sve_<lr>shift_operand" "D<lr>, w, w"))]
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(match_operand:SVE_I 2 "register_operand" "w, 0, w, w")
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(match_operand:SVE_I 3 "aarch64_sve_<lr>shift_operand" "D<lr>, w, 0, w"))]
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UNSPEC_PRED_X))]
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"TARGET_SVE"
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"@
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#
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<shift>\t%0.<Vetype>, %1/m, %0.<Vetype>, %3.<Vetype>
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<shift>r\t%0.<Vetype>, %1/m, %3.<Vetype>, %2.<Vetype>
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movprfx\t%0, %2\;<shift>\t%0.<Vetype>, %1/m, %0.<Vetype>, %3.<Vetype>"
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"&& reload_completed
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&& !register_operand (operands[3], <MODE>mode)"
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[(set (match_dup 0) (ASHIFT:SVE_I (match_dup 2) (match_dup 3)))]
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""
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[(set_attr "movprfx" "*,*,yes")]
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[(set_attr "movprfx" "*,*,*,yes")]
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)
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;; Unpredicated shift operations by a constant (post-RA only).
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@ -1,3 +1,8 @@
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2019-08-15 Richard Sandiford <richard.sandiford@arm.com>
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Prathamesh Kulkarni <prathamesh.kulkarni@linaro.org>
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* gcc.target/aarch64/sve/shift_1.c: Accept reversed shifts.
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2019-08-15 Richard Sandiford <richard.sandiford@arm.com>
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Kugan Vivekanandarajah <kugan.vivekanandarajah@linaro.org>
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@ -75,9 +75,9 @@ DO_IMMEDIATE_OPS (63, int64_t, 63);
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/* { dg-final { scan-assembler-times {\tlsr\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 2 } } */
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/* { dg-final { scan-assembler-times {\tlsl\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 2 } } */
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/* { dg-final { scan-assembler-times {\tasr\tz[0-9]+\.d, p[0-7]/m, z[0-9]+\.d, z[0-9]+\.d\n} 2 } } */
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/* { dg-final { scan-assembler-times {\tlsr\tz[0-9]+\.d, p[0-7]/m, z[0-9]+\.d, z[0-9]+\.d\n} 2 } } */
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/* { dg-final { scan-assembler-times {\tlsl\tz[0-9]+\.d, p[0-7]/m, z[0-9]+\.d, z[0-9]+\.d\n} 2 } } */
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/* { dg-final { scan-assembler-times {\tasrr?\tz[0-9]+\.d, p[0-7]/m, z[0-9]+\.d, z[0-9]+\.d\n} 2 } } */
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/* { dg-final { scan-assembler-times {\tlsrr?\tz[0-9]+\.d, p[0-7]/m, z[0-9]+\.d, z[0-9]+\.d\n} 2 } } */
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/* { dg-final { scan-assembler-times {\tlslr?\tz[0-9]+\.d, p[0-7]/m, z[0-9]+\.d, z[0-9]+\.d\n} 2 } } */
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/* { dg-final { scan-assembler-times {\tasr\tz[0-9]+\.b, z[0-9]+\.b, #5\n} 1 } } */
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/* { dg-final { scan-assembler-times {\tlsr\tz[0-9]+\.b, z[0-9]+\.b, #5\n} 1 } } */
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