arm.c (get_arm_condition_code): Remove CC_NOTBmode case.
* config/arm/arm.c (get_arm_condition_code): Remove CC_NOTBmode case. * arm-modes.def (CC_NOTB): Don't define. * config/arm/arm.md (arm_adddi3): Generate canonical RTL. (adddi_sesidi_di, adddi_zesidi_di): Likewise. (LTUGEU): New code_iterator. (cnb, optab): New corresponding code_attrs. (addsi3_carryin_<optab>): Renamed from addsi3_carryin. Change pattern to canonical form. Operands 1 and 2 are commutative. Parametrize using LTUGEU. (addsi3_carryin_shift_<optab>): Likewise. (addsi3_carryin_alt2_<optab>): Renamed from addsi3_carryin_alt2. Operands 1 and 2 are commutative. Parametrize using LTUGEU. (addsi3_carryin_alt1, addsi3_carryin_alt3): Remove. (subsi3_compare): Renamed from subsi3_compare0_c. Change CC_NOTB to CC. (arm_subsi3_insn): Allow constants for operand 0. (compare_scc peephole for eq case): New. (compare_scc splitters): Change CC_NOTB to CC. From-SVN: r161831
This commit is contained in:
parent
75421dcdc6
commit
7ec6356e22
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@ -1,3 +1,24 @@
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2010-07-05 Bernd Schmidt <bernds@codesourcery.com>
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* config/arm/arm.c (get_arm_condition_code): Remove CC_NOTBmode case.
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* arm-modes.def (CC_NOTB): Don't define.
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* config/arm/arm.md (arm_adddi3): Generate canonical RTL.
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(adddi_sesidi_di, adddi_zesidi_di): Likewise.
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(LTUGEU): New code_iterator.
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(cnb, optab): New corresponding code_attrs.
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(addsi3_carryin_<optab>): Renamed from addsi3_carryin. Change pattern
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to canonical form. Operands 1 and 2 are commutative. Parametrize
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using LTUGEU.
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(addsi3_carryin_shift_<optab>): Likewise.
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(addsi3_carryin_alt2_<optab>): Renamed from addsi3_carryin_alt2.
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Operands 1 and 2 are commutative. Parametrize using LTUGEU.
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(addsi3_carryin_alt1, addsi3_carryin_alt3): Remove.
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(subsi3_compare): Renamed from subsi3_compare0_c. Change CC_NOTB to
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CC.
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(arm_subsi3_insn): Allow constants for operand 0.
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(compare_scc peephole for eq case): New.
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(compare_scc splitters): Change CC_NOTB to CC.
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2010-07-05 Richard Guenther <rguenther@suse.de>
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* tree-ssa-loop-im.c (for_each_index): Do not handle
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@ -36,8 +36,6 @@ ADJUST_FLOAT_FORMAT (HF, ((arm_fp16_format == ARM_FP16_FORMAT_ALTERNATIVE)
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CC_Zmode should be used if only the Z flag is set correctly
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CC_Cmode should be used if only the C flag is set correctly, after an
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addition.
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CC_NOTBmode should be used if only the C flag is set as a not-borrow
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flag, after a subtraction.
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CC_Nmode should be used if only the N (sign) flag is set correctly
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CC_CZmode should be used if only the C and Z flags are correct
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(used for DImode unsigned comparisons).
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@ -63,7 +61,6 @@ CC_MODE (CC_DLTU);
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CC_MODE (CC_DGEU);
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CC_MODE (CC_DGTU);
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CC_MODE (CC_C);
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CC_MODE (CC_NOTB);
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CC_MODE (CC_N);
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/* Vector modes. */
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@ -16341,14 +16341,6 @@ get_arm_condition_code (rtx comparison)
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default: gcc_unreachable ();
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}
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case CC_NOTBmode:
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switch (comp_code)
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{
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case LTU: return ARM_CC;
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case GEU: return ARM_CS;
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default: gcc_unreachable ();
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}
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case CC_CZmode:
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switch (comp_code)
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{
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@ -503,8 +503,8 @@
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(compare:CC_C (plus:SI (match_dup 1) (match_dup 2))
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(match_dup 1)))
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(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))])
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(set (match_dup 3) (plus:SI (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))
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(plus:SI (match_dup 4) (match_dup 5))))]
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(set (match_dup 3) (plus:SI (plus:SI (match_dup 4) (match_dup 5))
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(ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))]
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"
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{
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operands[3] = gen_highpart (SImode, operands[0]);
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@ -531,10 +531,10 @@
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(compare:CC_C (plus:SI (match_dup 1) (match_dup 2))
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(match_dup 1)))
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(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))])
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(set (match_dup 3) (plus:SI (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))
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(plus:SI (ashiftrt:SI (match_dup 2)
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(set (match_dup 3) (plus:SI (plus:SI (ashiftrt:SI (match_dup 2)
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(const_int 31))
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(match_dup 4))))]
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(match_dup 4))
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(ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))]
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"
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{
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operands[3] = gen_highpart (SImode, operands[0]);
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@ -560,8 +560,8 @@
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(compare:CC_C (plus:SI (match_dup 1) (match_dup 2))
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(match_dup 1)))
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(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))])
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(set (match_dup 3) (plus:SI (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))
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(plus:SI (match_dup 4) (const_int 0))))]
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(set (match_dup 3) (plus:SI (plus:SI (match_dup 4) (const_int 0))
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(ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))]
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"
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{
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operands[3] = gen_highpart (SImode, operands[0]);
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@ -849,60 +849,44 @@
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[(set_attr "conds" "set")]
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)
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(define_insn "*addsi3_carryin"
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[(set (match_operand:SI 0 "s_register_operand" "=r")
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(plus:SI (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))
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(plus:SI (match_operand:SI 1 "s_register_operand" "r")
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(match_operand:SI 2 "arm_rhs_operand" "rI"))))]
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"TARGET_32BIT"
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"adc%?\\t%0, %1, %2"
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[(set_attr "conds" "use")]
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)
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(define_code_iterator LTUGEU [ltu geu])
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(define_code_attr cnb [(ltu "CC_C") (geu "CC")])
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(define_code_attr optab [(ltu "ltu") (geu "geu")])
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(define_insn "*addsi3_carryin_shift"
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(define_insn "*addsi3_carryin_<optab>"
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[(set (match_operand:SI 0 "s_register_operand" "=r")
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(plus:SI (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))
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(plus:SI
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(match_operator:SI 2 "shift_operator"
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[(match_operand:SI 3 "s_register_operand" "r")
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(match_operand:SI 4 "reg_or_int_operand" "rM")])
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(match_operand:SI 1 "s_register_operand" "r"))))]
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"TARGET_32BIT"
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"adc%?\\t%0, %1, %3%S2"
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[(set_attr "conds" "use")
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(set (attr "type") (if_then_else (match_operand 4 "const_int_operand" "")
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(const_string "alu_shift")
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(const_string "alu_shift_reg")))]
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)
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(define_insn "*addsi3_carryin_alt1"
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[(set (match_operand:SI 0 "s_register_operand" "=r")
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(plus:SI (plus:SI (match_operand:SI 1 "s_register_operand" "r")
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(plus:SI (plus:SI (match_operand:SI 1 "s_register_operand" "%r")
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(match_operand:SI 2 "arm_rhs_operand" "rI"))
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(ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))]
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(LTUGEU:SI (reg:<cnb> CC_REGNUM) (const_int 0))))]
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"TARGET_32BIT"
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"adc%?\\t%0, %1, %2"
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[(set_attr "conds" "use")]
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)
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(define_insn "*addsi3_carryin_alt2"
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(define_insn "*addsi3_carryin_alt2_<optab>"
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[(set (match_operand:SI 0 "s_register_operand" "=r")
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(plus:SI (plus:SI (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))
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(match_operand:SI 1 "s_register_operand" "r"))
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(plus:SI (plus:SI (LTUGEU:SI (reg:<cnb> CC_REGNUM) (const_int 0))
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(match_operand:SI 1 "s_register_operand" "%r"))
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(match_operand:SI 2 "arm_rhs_operand" "rI")))]
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"TARGET_32BIT"
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"adc%?\\t%0, %1, %2"
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[(set_attr "conds" "use")]
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)
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(define_insn "*addsi3_carryin_alt3"
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(define_insn "*addsi3_carryin_shift_<optab>"
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[(set (match_operand:SI 0 "s_register_operand" "=r")
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(plus:SI (plus:SI (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))
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(match_operand:SI 2 "arm_rhs_operand" "rI"))
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(match_operand:SI 1 "s_register_operand" "r")))]
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(plus:SI (plus:SI
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(match_operator:SI 2 "shift_operator"
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[(match_operand:SI 3 "s_register_operand" "r")
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(match_operand:SI 4 "reg_or_int_operand" "rM")])
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(match_operand:SI 1 "s_register_operand" "r"))
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(LTUGEU:SI (reg:<cnb> CC_REGNUM) (const_int 0))))]
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"TARGET_32BIT"
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"adc%?\\t%0, %1, %2"
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[(set_attr "conds" "use")]
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"adc%?\\t%0, %1, %3%S2"
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[(set_attr "conds" "use")
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(set (attr "type") (if_then_else (match_operand 4 "const_int_operand" "")
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(const_string "alu_shift")
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(const_string "alu_shift_reg")))]
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)
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(define_expand "incscc"
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@ -1104,24 +1088,27 @@
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; ??? Check Thumb-2 split length
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(define_insn_and_split "*arm_subsi3_insn"
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[(set (match_operand:SI 0 "s_register_operand" "=r,rk,r")
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(minus:SI (match_operand:SI 1 "reg_or_int_operand" "rI,!k,?n")
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(match_operand:SI 2 "s_register_operand" "r, r, r")))]
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[(set (match_operand:SI 0 "s_register_operand" "=r,r,rk,r,r")
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(minus:SI (match_operand:SI 1 "reg_or_int_operand" "rI,r,!k,?n,r")
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(match_operand:SI 2 "reg_or_int_operand" "r,rI, r, r,?n")))]
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"TARGET_32BIT"
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"@
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rsb%?\\t%0, %2, %1
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sub%?\\t%0, %1, %2
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sub%?\\t%0, %1, %2
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#
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#"
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"TARGET_32BIT
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&& GET_CODE (operands[1]) == CONST_INT
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&& !const_ok_for_arm (INTVAL (operands[1]))"
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"&& ((GET_CODE (operands[1]) == CONST_INT
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&& !const_ok_for_arm (INTVAL (operands[1])))
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|| (GET_CODE (operands[2]) == CONST_INT
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&& !const_ok_for_arm (INTVAL (operands[2]))))"
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[(clobber (const_int 0))]
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"
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arm_split_constant (MINUS, SImode, curr_insn,
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INTVAL (operands[1]), operands[0], operands[2], 0);
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DONE;
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"
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[(set_attr "length" "4,4,16")
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[(set_attr "length" "4,4,4,16,16")
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(set_attr "predicable" "yes")]
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)
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@ -1153,10 +1140,10 @@
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[(set_attr "conds" "set")]
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)
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(define_insn "*subsi3_compare0_c"
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[(set (reg:CC_NOTB CC_REGNUM)
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(compare:CC_NOTB (match_operand:SI 1 "arm_rhs_operand" "r,I")
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(match_operand:SI 2 "arm_rhs_operand" "rI,r")))
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(define_insn "*subsi3_compare"
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[(set (reg:CC CC_REGNUM)
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(compare:CC (match_operand:SI 1 "arm_rhs_operand" "r,I")
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(match_operand:SI 2 "arm_rhs_operand" "rI,r")))
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(set (match_operand:SI 0 "s_register_operand" "=r,r")
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(minus:SI (match_dup 1) (match_dup 2)))]
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"TARGET_32BIT"
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@ -9306,11 +9293,11 @@
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(clobber (reg:CC CC_REGNUM))]
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"TARGET_32BIT && reload_completed"
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[(parallel
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[(set (reg:CC_NOTB CC_REGNUM)
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(compare:CC_NOTB (const_int 1) (match_dup 1)))
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[(set (reg:CC CC_REGNUM)
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(compare:CC (const_int 1) (match_dup 1)))
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(set (match_dup 0)
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(minus:SI (const_int 1) (match_dup 1)))])
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(cond_exec (ltu:CC_NOTB (reg:CC_NOTB CC_REGNUM) (const_int 0))
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(cond_exec (ltu:CC (reg:CC CC_REGNUM) (const_int 0))
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(set (match_dup 0) (const_int 0)))])
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(define_split
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@ -9362,7 +9349,7 @@
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enum rtx_code rc = GET_CODE (operands[1]);
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tmp1 = gen_rtx_REG (mode, CC_REGNUM);
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operands[5] = gen_rtx_fmt_ee (rc, VOIDmode, tmp1, const0_rtx);
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if (mode == CCFPmode || mode == CCFPEmode)
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rc = reverse_condition_maybe_unordered (rc);
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@ -9371,6 +9358,27 @@
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operands[4] = gen_rtx_fmt_ee (rc, VOIDmode, tmp1, const0_rtx);
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})
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;; Attempt to improve the sequence generated by the compare_scc splitters
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;; not to use conditional execution.
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(define_peephole2
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[(set (reg:CC CC_REGNUM)
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(compare:CC (match_operand:SI 1 "register_operand" "")
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(match_operand:SI 2 "arm_rhs_operand" "")))
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(cond_exec (ne (reg:CC CC_REGNUM) (const_int 0))
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(set (match_operand:SI 0 "register_operand" "") (const_int 0)))
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(cond_exec (eq (reg:CC CC_REGNUM) (const_int 0))
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(set (match_dup 0) (const_int 1)))
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(match_scratch:SI 3 "r")]
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"TARGET_32BIT"
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[(set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2)))
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(parallel
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[(set (reg:CC CC_REGNUM)
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(compare:CC (const_int 0) (match_dup 3)))
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(set (match_dup 0) (minus:SI (const_int 0) (match_dup 3)))])
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(set (match_dup 0)
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(plus:SI (plus:SI (match_dup 0) (match_dup 3))
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(geu:SI (reg:CC CC_REGNUM) (const_int 0))))])
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(define_insn "*cond_move"
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[(set (match_operand:SI 0 "s_register_operand" "=r,r,r")
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(if_then_else:SI (match_operator 3 "equality_operator"
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