i386.c (index_register_operand): New.
2002-09-09 Jan Hubicka <jh@suse.cz> * i386.c (index_register_operand): New. * i386.h (predicate_codes): Add new predicate. * i386.md (lea_general_*): Use index_regsiter_operand (ashift to lea splitter): Do not produce invalid leas (ashift to mov+ashift split): New. From-SVN: r56970
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@ -1,3 +1,11 @@
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2002-09-09 Jan Hubicka <jh@suse.cz>
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* i386.c (index_register_operand): New.
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* i386.h (predicate_codes): Add new predicate.
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* i386.md (lea_general_*): Use index_regsiter_operand
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(ashift to lea splitter): Do not produce invalid leas
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(ashift to mov+ashift split): New.
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2002-09-09 Nick Clifton <nickc@redhat.com>
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* config/fr30/fr30.c (output.h): Move after inclusion of tree.h.
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@ -3217,6 +3217,30 @@ nonmemory_no_elim_operand (op, mode)
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return GET_CODE (op) == CONST_INT || register_operand (op, mode);
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}
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/* Return false if this is any eliminable register or stack register,
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otherwise work like register_operand. */
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int
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index_register_operand (op, mode)
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register rtx op;
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enum machine_mode mode;
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{
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rtx t = op;
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if (GET_CODE (t) == SUBREG)
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t = SUBREG_REG (t);
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if (!REG_P (t))
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return 0;
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if (t == arg_pointer_rtx
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|| t == frame_pointer_rtx
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|| t == virtual_incoming_args_rtx
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|| t == virtual_stack_vars_rtx
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|| t == virtual_stack_dynamic_rtx
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|| REGNO (t) == STACK_POINTER_REGNUM)
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return 0;
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return general_operand (op, mode);
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}
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/* Return true if op is a Q_REGS class register. */
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int
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@ -3173,6 +3173,7 @@ do { \
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{"general_no_elim_operand", {CONST_INT, CONST_DOUBLE, CONST, \
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SYMBOL_REF, LABEL_REF, SUBREG, REG, MEM}}, \
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{"nonmemory_no_elim_operand", {CONST_INT, REG, SUBREG}}, \
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{"index_register_operand", {SUBREG, REG}}, \
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{"q_regs_operand", {SUBREG, REG}}, \
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{"non_q_regs_operand", {SUBREG, REG}}, \
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{"fcmov_comparison_operator", {EQ, NE, LTU, GTU, LEU, GEU, UNORDERED, \
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@ -4845,7 +4845,7 @@
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(define_insn_and_split "*lea_general_1"
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[(set (match_operand 0 "register_operand" "=r")
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(plus (plus (match_operand 1 "register_operand" "r")
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(plus (plus (match_operand 1 "index_register_operand" "r")
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(match_operand 2 "register_operand" "r"))
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(match_operand 3 "immediate_operand" "i")))]
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"(GET_MODE (operands[0]) == QImode || GET_MODE (operands[0]) == HImode
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@ -4877,7 +4877,7 @@
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(define_insn_and_split "*lea_general_1_zext"
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[(set (match_operand:DI 0 "register_operand" "=r")
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(zero_extend:DI
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(plus:SI (plus:SI (match_operand:SI 1 "register_operand" "r")
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(plus:SI (plus:SI (match_operand:SI 1 "index_register_operand" "r")
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(match_operand:SI 2 "register_operand" "r"))
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(match_operand:SI 3 "immediate_operand" "i"))))]
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"TARGET_64BIT"
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@ -4897,7 +4897,7 @@
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(define_insn_and_split "*lea_general_2"
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[(set (match_operand 0 "register_operand" "=r")
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(plus (mult (match_operand 1 "register_operand" "r")
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(plus (mult (match_operand 1 "index_register_operand" "r")
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(match_operand 2 "const248_operand" "i"))
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(match_operand 3 "nonmemory_operand" "ri")))]
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"(GET_MODE (operands[0]) == QImode || GET_MODE (operands[0]) == HImode
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@ -4927,7 +4927,7 @@
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(define_insn_and_split "*lea_general_2_zext"
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[(set (match_operand:DI 0 "register_operand" "=r")
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(zero_extend:DI
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(plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r")
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(plus:SI (mult:SI (match_operand:SI 1 "index_register_operand" "r")
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(match_operand:SI 2 "const248_operand" "n"))
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(match_operand:SI 3 "nonmemory_operand" "ri"))))]
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"TARGET_64BIT"
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@ -4946,7 +4946,7 @@
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(define_insn_and_split "*lea_general_3"
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[(set (match_operand 0 "register_operand" "=r")
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(plus (plus (mult (match_operand 1 "register_operand" "r")
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(plus (plus (mult (match_operand 1 "index_register_operand" "r")
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(match_operand 2 "const248_operand" "i"))
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(match_operand 3 "register_operand" "r"))
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(match_operand 4 "immediate_operand" "i")))]
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@ -4980,7 +4980,7 @@
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(define_insn_and_split "*lea_general_3_zext"
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[(set (match_operand:DI 0 "register_operand" "=r")
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(zero_extend:DI
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(plus:SI (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r")
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(plus:SI (plus:SI (mult:SI (match_operand:SI 1 "index_register_operand" "r")
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(match_operand:SI 2 "const248_operand" "n"))
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(match_operand:SI 3 "register_operand" "r"))
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(match_operand:SI 4 "immediate_operand" "i"))))]
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@ -10615,7 +10615,7 @@
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;; Convert lea to the lea pattern to avoid flags dependency.
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(define_split
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[(set (match_operand 0 "register_operand" "")
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(ashift (match_operand 1 "register_operand" "")
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(ashift (match_operand 1 "index_register_operand" "")
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(match_operand:QI 2 "const_int_operand" "")))
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(clobber (reg:CC 17))]
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"reload_completed
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@ -10633,6 +10633,26 @@
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DONE;
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})
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;; Rare case of shifting RSP is handled by generating move and shift
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(define_split
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[(set (match_operand 0 "register_operand" "")
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(ashift (match_operand 1 "register_operand" "")
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(match_operand:QI 2 "const_int_operand" "")))
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(clobber (reg:CC 17))]
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"reload_completed
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&& true_regnum (operands[0]) != true_regnum (operands[1])"
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[(const_int 0)]
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{
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rtx pat, clob;
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emit_move_insn (operands[1], operands[0]);
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pat = gen_rtx_SET (VOIDmode, operands[0],
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gen_rtx_ASHIFT (GET_MODE (operands[0]),
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operands[0], operands[2]));
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clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
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emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, pat, clob)));
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DONE;
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})
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(define_insn "*ashlsi3_1_zext"
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[(set (match_operand:DI 0 "register_operand" "=r,r")
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(zero_extend:DI (ashift:SI (match_operand:SI 1 "register_operand" "0,r")
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