[arm] Remove FEATURES field from FPU descriptions
Now that everything uses the new ISA features, we can remove the FEATURES field from the FPU descriptions, along with all the macros and definitions associated with it. * arm-fpus.def (ARM_FPU): Remove features field from all definitions. * arm.h (arm_fpu_feature_set): Delete typedef. (FPU_FL_NONE): Delete. (FPU_FL_NEON): Delete. (FPU_FL_FP16): Delete. (FPU_FL_CRYPTO): Delete. (FPU_FL_DBL): Delete. (FPU_FL_D32): Delete. (FPU_FL_VFPv2): Delete. (FPU_FL_VFPv3): Delete. (FPU_FL_VFPv4): Delete. (FPU_FL_VFPv5): Delete. (FPU_FL_AMRv8): Delete. (FPU_VFPv2): Delete. (FPU_VFPv3): Delete. (FPU_VFPv4): Delete. (FPU_VFPv5): Delete. (FPU_ARMv8): Delete. (FPU_DBL): Delete. (FPU_D32): Delete. (FPU_NEON): Delete. (FPU_CRYPTO): Delete. (FPU_FP16): Delete. (arm_fpu_desc): Delete features field. * arm.c (all_fpus): Don't initialize feature field. From-SVN: r243715
This commit is contained in:
Richard Earnshaw
Richard Earnshaw
parent
56941f70ee
commit
7eca7f0b44
@ -1,3 +1,31 @@
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2016-12-15 Richard Earnshaw <rearnsha@arm.com>
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* arm-fpus.def (ARM_FPU): Remove features field from all definitions.
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* arm.h (arm_fpu_feature_set): Delete typedef.
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(FPU_FL_NONE): Delete.
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(FPU_FL_NEON): Delete.
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(FPU_FL_FP16): Delete.
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(FPU_FL_CRYPTO): Delete.
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(FPU_FL_DBL): Delete.
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(FPU_FL_D32): Delete.
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(FPU_FL_VFPv2): Delete.
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(FPU_FL_VFPv3): Delete.
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(FPU_FL_VFPv4): Delete.
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(FPU_FL_VFPv5): Delete.
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(FPU_FL_AMRv8): Delete.
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(FPU_VFPv2): Delete.
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(FPU_VFPv3): Delete.
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(FPU_VFPv4): Delete.
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(FPU_VFPv5): Delete.
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(FPU_ARMv8): Delete.
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(FPU_DBL): Delete.
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(FPU_D32): Delete.
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(FPU_NEON): Delete.
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(FPU_CRYPTO): Delete.
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(FPU_FP16): Delete.
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(arm_fpu_desc): Delete features field.
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* arm.c (all_fpus): Don't initialize feature field.
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2016-12-15 Richard Earnshaw <rearnsha@arm.com>
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* arm.c (arm_can_inline_p): Use ISA features for determining
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@ -19,31 +19,31 @@
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/* Before using #include to read this file, define a macro:
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ARM_FPU(NAME, ISA, FEATURES)
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ARM_FPU(NAME, ISA)
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The arguments are the fields of struct arm_fpu_desc.
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genopt.sh assumes no whitespace up to the first "," in each entry. */
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ARM_FPU("vfp", ISA_FEAT(ISA_VFPv2) ISA_FEAT(ISA_FP_DBL), FPU_VFPv2 | FPU_DBL)
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ARM_FPU("vfpv2", ISA_FEAT(ISA_VFPv2) ISA_FEAT(ISA_FP_DBL), FPU_VFPv2 | FPU_DBL)
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ARM_FPU("vfpv3", ISA_FEAT(ISA_VFPv3) ISA_FEAT(ISA_FP_D32), FPU_VFPv3 | FPU_D32)
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ARM_FPU("vfpv3-fp16", ISA_FEAT(ISA_VFPv3) ISA_FEAT(ISA_FP_D32) ISA_FEAT(isa_bit_fp16conv), FPU_VFPv3 | FPU_D32 | FPU_FP16)
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ARM_FPU("vfpv3-d16", ISA_FEAT(ISA_VFPv3) ISA_FEAT(ISA_FP_DBL), FPU_VFPv3 | FPU_DBL)
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ARM_FPU("vfpv3-d16-fp16", ISA_FEAT(ISA_VFPv3) ISA_FEAT(ISA_FP_DBL) ISA_FEAT(isa_bit_fp16conv), FPU_VFPv3 | FPU_DBL | FPU_FP16)
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ARM_FPU("vfpv3xd", ISA_FEAT(ISA_VFPv3), FPU_VFPv3)
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ARM_FPU("vfpv3xd-fp16", ISA_FEAT(ISA_VFPv3) ISA_FEAT(isa_bit_fp16conv), FPU_VFPv3 | FPU_FP16)
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ARM_FPU("neon", ISA_FEAT(ISA_VFPv3) ISA_FEAT(ISA_NEON), FPU_VFPv3 | FPU_NEON)
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ARM_FPU("neon-vfpv3", ISA_FEAT(ISA_VFPv3) ISA_FEAT(ISA_NEON), FPU_VFPv3 | FPU_NEON)
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ARM_FPU("neon-fp16", ISA_FEAT(ISA_VFPv3) ISA_FEAT(ISA_NEON) ISA_FEAT(isa_bit_fp16conv), FPU_VFPv3 | FPU_NEON | FPU_FP16)
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ARM_FPU("vfpv4", ISA_FEAT(ISA_VFPv4) ISA_FEAT(ISA_FP_D32), FPU_VFPv4 | FPU_D32 | FPU_FP16)
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ARM_FPU("neon-vfpv4", ISA_FEAT(ISA_VFPv4) ISA_FEAT(ISA_NEON), FPU_VFPv4 | FPU_NEON | FPU_FP16)
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ARM_FPU("vfpv4-d16", ISA_FEAT(ISA_VFPv4) ISA_FEAT(ISA_FP_DBL), FPU_VFPv4 | FPU_DBL | FPU_FP16)
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ARM_FPU("fpv4-sp-d16", ISA_FEAT(ISA_VFPv4), FPU_VFPv4 | FPU_FP16)
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ARM_FPU("fpv5-sp-d16", ISA_FEAT(ISA_FPv5), FPU_VFPv5 | FPU_FP16)
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ARM_FPU("fpv5-d16", ISA_FEAT(ISA_FPv5) ISA_FEAT(ISA_FP_DBL), FPU_VFPv5 | FPU_DBL | FPU_FP16)
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ARM_FPU("fp-armv8", ISA_FEAT(ISA_FP_ARMv8) ISA_FEAT(ISA_FP_D32), FPU_ARMv8 | FPU_D32 | FPU_FP16)
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ARM_FPU("neon-fp-armv8", ISA_FEAT(ISA_FP_ARMv8) ISA_FEAT(ISA_NEON), FPU_ARMv8 | FPU_NEON | FPU_FP16)
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ARM_FPU("crypto-neon-fp-armv8", ISA_FEAT(ISA_FP_ARMv8) ISA_FEAT(ISA_CRYPTO), FPU_ARMv8 | FPU_CRYPTO | FPU_FP16)
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ARM_FPU("vfp", ISA_FEAT(ISA_VFPv2) ISA_FEAT(ISA_FP_DBL))
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ARM_FPU("vfpv2", ISA_FEAT(ISA_VFPv2) ISA_FEAT(ISA_FP_DBL))
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ARM_FPU("vfpv3", ISA_FEAT(ISA_VFPv3) ISA_FEAT(ISA_FP_D32))
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ARM_FPU("vfpv3-fp16", ISA_FEAT(ISA_VFPv3) ISA_FEAT(ISA_FP_D32) ISA_FEAT(isa_bit_fp16conv))
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ARM_FPU("vfpv3-d16", ISA_FEAT(ISA_VFPv3) ISA_FEAT(ISA_FP_DBL))
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ARM_FPU("vfpv3-d16-fp16", ISA_FEAT(ISA_VFPv3) ISA_FEAT(ISA_FP_DBL) ISA_FEAT(isa_bit_fp16conv))
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ARM_FPU("vfpv3xd", ISA_FEAT(ISA_VFPv3))
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ARM_FPU("vfpv3xd-fp16", ISA_FEAT(ISA_VFPv3) ISA_FEAT(isa_bit_fp16conv))
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ARM_FPU("neon", ISA_FEAT(ISA_VFPv3) ISA_FEAT(ISA_NEON))
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ARM_FPU("neon-vfpv3", ISA_FEAT(ISA_VFPv3) ISA_FEAT(ISA_NEON))
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ARM_FPU("neon-fp16", ISA_FEAT(ISA_VFPv3) ISA_FEAT(ISA_NEON) ISA_FEAT(isa_bit_fp16conv))
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ARM_FPU("vfpv4", ISA_FEAT(ISA_VFPv4) ISA_FEAT(ISA_FP_D32))
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ARM_FPU("neon-vfpv4", ISA_FEAT(ISA_VFPv4) ISA_FEAT(ISA_NEON))
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ARM_FPU("vfpv4-d16", ISA_FEAT(ISA_VFPv4) ISA_FEAT(ISA_FP_DBL))
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ARM_FPU("fpv4-sp-d16", ISA_FEAT(ISA_VFPv4))
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ARM_FPU("fpv5-sp-d16", ISA_FEAT(ISA_FPv5))
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ARM_FPU("fpv5-d16", ISA_FEAT(ISA_FPv5) ISA_FEAT(ISA_FP_DBL))
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ARM_FPU("fp-armv8", ISA_FEAT(ISA_FP_ARMv8) ISA_FEAT(ISA_FP_D32))
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ARM_FPU("neon-fp-armv8", ISA_FEAT(ISA_FP_ARMv8) ISA_FEAT(ISA_NEON))
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ARM_FPU("crypto-neon-fp-armv8", ISA_FEAT(ISA_FP_ARMv8) ISA_FEAT(ISA_CRYPTO))
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/* Compatibility aliases. */
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ARM_FPU("vfp3", ISA_FEAT(ISA_VFPv3) ISA_FEAT(ISA_FP_D32), FPU_VFPv3 | FPU_D32)
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ARM_FPU("vfp3", ISA_FEAT(ISA_VFPv3) ISA_FEAT(ISA_FP_D32))
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@ -2328,8 +2328,8 @@ char arm_arch_name[] = "__ARM_ARCH_PROFILE__";
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const struct arm_fpu_desc all_fpus[] =
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{
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#define ARM_FPU(NAME, ISA, FEATURES) \
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{ NAME, {ISA isa_nobit}, FEATURES },
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#define ARM_FPU(NAME, ISA) \
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{ NAME, {ISA isa_nobit} },
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#include "arm-fpus.def"
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#undef ARM_FPU
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};
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@ -326,44 +326,10 @@ extern tree arm_fp16_type_node;
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{"mode", "%{!marm:%{!mthumb:-m%(VALUE)}}"}, \
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{"tls", "%{!mtls-dialect=*:-mtls-dialect=%(VALUE)}"},
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/* FPU feature sets. */
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typedef unsigned long arm_fpu_feature_set;
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/* Test for an FPU feature. */
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#define ARM_FPU_FSET_HAS(S,F) (((S) & (F)) == (F))
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/* FPU Features. */
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#define FPU_FL_NONE (0u)
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#define FPU_FL_NEON (1u << 0) /* NEON instructions. */
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#define FPU_FL_FP16 (1u << 1) /* Half-precision. */
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#define FPU_FL_CRYPTO (1u << 2) /* Crypto extensions. */
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#define FPU_FL_DBL (1u << 3) /* Has double precision. */
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#define FPU_FL_D32 (1u << 4) /* Has 32 double precision regs. */
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#define FPU_FL_VFPv2 (1u << 5) /* Has VFPv2 features. */
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#define FPU_FL_VFPv3 (1u << 6) /* Has VFPv3 extensions. */
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#define FPU_FL_VFPv4 (1u << 7) /* Has VFPv4 extensions. */
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#define FPU_FL_VFPv5 (1u << 8) /* Has VFPv5 extensions. */
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#define FPU_FL_ARMv8 (1u << 9) /* Has ARMv8 extensions to VFP. */
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/* Some useful combinations. */
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#define FPU_VFPv2 (FPU_FL_VFPv2)
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#define FPU_VFPv3 (FPU_VFPv2 | FPU_FL_VFPv3)
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#define FPU_VFPv4 (FPU_VFPv3 | FPU_FL_VFPv4)
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#define FPU_VFPv5 (FPU_VFPv4 | FPU_FL_VFPv5)
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#define FPU_ARMv8 (FPU_VFPv5 | FPU_FL_ARMv8)
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#define FPU_DBL (FPU_FL_DBL)
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#define FPU_D32 (FPU_DBL | FPU_FL_D32)
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#define FPU_NEON (FPU_D32 | FPU_FL_NEON)
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#define FPU_CRYPTO (FPU_NEON | FPU_FL_CRYPTO)
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#define FPU_FP16 (FPU_FL_FP16)
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extern const struct arm_fpu_desc
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{
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const char *name;
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enum isa_feature isa_bits[isa_num_bits];
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arm_fpu_feature_set features;
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} all_fpus[];
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/* Which floating point hardware to schedule for. */
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