2007-xx-xx Chao-ying Fu <fu@mips.com> Richard Sandiford <richard@nildram.co.uk>
gcc/ 2007-xx-xx Chao-ying Fu <fu@mips.com> Richard Sandiford <richard@nildram.co.uk> * doc/md.texi (madd@var{m}@var{n}4, umadd@var{m}@var{n}4): Document. * optabs.h (OTI_smadd_widen, OTI_umadd_widen): New optab_indexes. (smadd_widen_optab, umadd_widen_optab): Define. * optabs.c (init_optabs): Initialize smadd_widen_optab and umadd_widen_optab. * genopinit.c (optabs): Fill in smadd_widen_optab and umadd_widen_optab. * expr.c (expand_expr_real_1): Try to use smadd_widen_optab and umadd_widen_optab to implement multiply-add sequences. * config/mips/mips.md (*<su>mul_acc_di): Rename to... (<u>maddsidi4): ...this. Extend condition to include GENERATE_MADD_MSUB and TARGET_DSPR2. Change the constraint of operand 0 to "ka" and use the three-operand form of madd<u> for TARGET_DSPR2. * config/mips/mips-dspr2.md (mips_madd, mips_maddu): Convert to define_expands. * config/mips/constraints.md (ka): New register constraint. gcc/testsuite/ 2007-xx-xx Richard Sandiford <richard@nildram.co.uk> * gcc.target/mips/madd-1.c, gcc.target/mips/madd-2.c, * gcc.target/mips/madd-3.c, gcc.target/mips/madd-4.c, * gcc.target/mips/maddu-1.c, gcc.target/mips/maddu-2.c, * gcc.target/mips/maddu-3.c, gcc.target/mips/maddu-4.c: New tests. From-SVN: r124095
This commit is contained in:
parent
ec9ac2bc42
commit
7f9844caf1
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@ -1,3 +1,24 @@
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2007-04-24 Chao-ying Fu <fu@mips.com>
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Richard Sandiford <richard@nildram.co.uk>
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* doc/md.texi (madd@var{m}@var{n}4, umadd@var{m}@var{n}4): Document.
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* optabs.h (OTI_smadd_widen, OTI_umadd_widen): New optab_indexes.
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(smadd_widen_optab, umadd_widen_optab): Define.
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* optabs.c (init_optabs): Initialize smadd_widen_optab and
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umadd_widen_optab.
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* genopinit.c (optabs): Fill in smadd_widen_optab and
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umadd_widen_optab.
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* expr.c (expand_expr_real_1): Try to use smadd_widen_optab
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and umadd_widen_optab to implement multiply-add sequences.
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* config/mips/mips.md (*<su>mul_acc_di): Rename to...
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(<u>maddsidi4): ...this. Extend condition to include
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GENERATE_MADD_MSUB and TARGET_DSPR2. Change the constraint
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of operand 0 to "ka" and use the three-operand form of madd<u>
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for TARGET_DSPR2.
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* config/mips/mips-dspr2.md (mips_madd, mips_maddu): Convert
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to define_expands.
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* config/mips/constraints.md (ka): New register constraint.
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2007-04-24 Jan Hubicka <j@suse.cz>
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2007-04-24 Jan Hubicka <j@suse.cz>
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Revert:
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Revert:
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@ -78,6 +78,11 @@
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(define_register_constraint "D" "COP3_REGS"
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(define_register_constraint "D" "COP3_REGS"
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"@internal")
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"@internal")
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;; Registers that can be used as the target of multiply-accumulate
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;; instructions. The core MIPS32 ISA provides a hi/lo madd,
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;; but the DSPr2 version allows any accumulator target.
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(define_register_constraint "ka" "TARGET_DSPR2 ? ACC_REGS : MD_REGS")
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;; Integer constraints
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;; Integer constraints
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(define_constraint "I"
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(define_constraint "I"
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@ -154,31 +154,13 @@
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[(set_attr "type" "imadd")
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[(set_attr "type" "imadd")
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(set_attr "mode" "SI")])
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(set_attr "mode" "SI")])
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(define_insn "mips_madd"
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(define_expand "mips_madd<u>"
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[(set (match_operand:DI 0 "register_operand" "=a")
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[(set (match_operand:DI 0 "register_operand")
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(plus:DI
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(plus:DI
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(mult:DI (sign_extend:DI
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(mult:DI (any_extend:DI (match_operand:SI 2 "register_operand"))
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(match_operand:SI 2 "register_operand" "d"))
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(any_extend:DI (match_operand:SI 3 "register_operand")))
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(sign_extend:DI
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(match_operand:DI 1 "register_operand")))]
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(match_operand:SI 3 "register_operand" "d")))
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"TARGET_DSPR2 && !TARGET_64BIT")
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(match_operand:DI 1 "register_operand" "0")))]
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"TARGET_DSPR2 && !TARGET_64BIT"
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"madd\t%q0,%2,%3"
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[(set_attr "type" "imadd")
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(set_attr "mode" "SI")])
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(define_insn "mips_maddu"
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[(set (match_operand:DI 0 "register_operand" "=a")
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(plus:DI
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(mult:DI (zero_extend:DI
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(match_operand:SI 2 "register_operand" "d"))
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(zero_extend:DI
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(match_operand:SI 3 "register_operand" "d")))
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(match_operand:DI 1 "register_operand" "0")))]
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"TARGET_DSPR2 && !TARGET_64BIT"
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"maddu\t%q0,%2,%3"
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[(set_attr "type" "imadd")
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(set_attr "mode" "SI")])
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(define_insn "mips_msub"
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(define_insn "mips_msub"
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[(set (match_operand:DI 0 "register_operand" "=a")
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[(set (match_operand:DI 0 "register_operand" "=a")
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@ -623,4 +605,3 @@
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"dpsqx_sa.w.ph\t%q0,%z2,%z3"
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"dpsqx_sa.w.ph\t%q0,%z2,%z3"
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[(set_attr "type" "imadd")
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[(set_attr "type" "imadd")
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(set_attr "mode" "SI")])
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(set_attr "mode" "SI")])
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@ -1767,18 +1767,20 @@
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[(set_attr "type" "imadd")
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[(set_attr "type" "imadd")
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(set_attr "mode" "SI")])
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(set_attr "mode" "SI")])
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(define_insn "*<su>mul_acc_di"
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(define_insn "<u>maddsidi4"
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[(set (match_operand:DI 0 "register_operand" "=x")
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[(set (match_operand:DI 0 "register_operand" "=ka")
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(plus:DI
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(plus:DI
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(mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
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(mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
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(any_extend:DI (match_operand:SI 2 "register_operand" "d")))
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(any_extend:DI (match_operand:SI 2 "register_operand" "d")))
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(match_operand:DI 3 "register_operand" "0")))]
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(match_operand:DI 3 "register_operand" "0")))]
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"(TARGET_MAD || ISA_HAS_MACC)
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"(TARGET_MAD || ISA_HAS_MACC || GENERATE_MADD_MSUB || TARGET_DSPR2)
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&& !TARGET_64BIT"
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&& !TARGET_64BIT"
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{
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{
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if (TARGET_MAD)
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if (TARGET_MAD)
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return "mad<u>\t%1,%2";
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return "mad<u>\t%1,%2";
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else if (TARGET_MIPS5500)
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else if (TARGET_DSPR2)
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return "madd<u>\t%q0,%1,%2";
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else if (GENERATE_MADD_MSUB || TARGET_MIPS5500)
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return "madd<u>\t%1,%2";
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return "madd<u>\t%1,%2";
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else
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else
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/* See comment in *macc. */
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/* See comment in *macc. */
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@ -3669,6 +3669,24 @@ The least significant half of the product is discarded.
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@item @samp{umul@var{m}3_highpart}
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@item @samp{umul@var{m}3_highpart}
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Similar, but the multiplication is unsigned.
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Similar, but the multiplication is unsigned.
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@cindex @code{madd@var{m}@var{n}4} instruction pattern
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@item @samp{madd@var{m}@var{n}4}
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Multiply operands 1 and 2, sign-extend them to mode @var{n}, add
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operand 3, and store the result in operand 0. Operands 1 and 2
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have mode @var{m} and operands 0 and 3 have mode @var{n}.
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Both modes must be integer modes and @var{n} must be twice
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the size of @var{m}.
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In other words, @code{madd@var{m}@var{n}4} is like
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@code{mul@var{m}@var{n}3} except that it also adds operand 3.
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These instructions are not allowed to @code{FAIL}.
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@cindex @code{umadd@var{m}@var{n}4} instruction pattern
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@item @samp{umadd@var{m}@var{n}4}
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Like @code{madd@var{m}@var{n}4}, but zero-extend the multiplication
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operands instead of sign-extending them.
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@cindex @code{divmod@var{m}4} instruction pattern
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@cindex @code{divmod@var{m}4} instruction pattern
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@item @samp{divmod@var{m}4}
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@item @samp{divmod@var{m}4}
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Signed division that produces both a quotient and a remainder.
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Signed division that produces both a quotient and a remainder.
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43
gcc/expr.c
43
gcc/expr.c
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@ -6824,7 +6824,7 @@ static rtx
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expand_expr_real_1 (tree exp, rtx target, enum machine_mode tmode,
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expand_expr_real_1 (tree exp, rtx target, enum machine_mode tmode,
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enum expand_modifier modifier, rtx *alt_rtl)
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enum expand_modifier modifier, rtx *alt_rtl)
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{
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{
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rtx op0, op1, temp, decl_rtl;
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rtx op0, op1, op2, temp, decl_rtl;
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tree type;
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tree type;
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int unsignedp;
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int unsignedp;
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enum machine_mode mode;
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enum machine_mode mode;
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@ -7977,6 +7977,47 @@ expand_expr_real_1 (tree exp, rtx target, enum machine_mode tmode,
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return op0;
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return op0;
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case PLUS_EXPR:
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case PLUS_EXPR:
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/* Check if this is a case for multiplication and addition. */
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if (TREE_CODE (type) == INTEGER_TYPE
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&& TREE_CODE (TREE_OPERAND (exp, 0)) == MULT_EXPR)
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{
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tree subsubexp0, subsubexp1;
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enum tree_code code0, code1;
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subexp0 = TREE_OPERAND (exp, 0);
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subsubexp0 = TREE_OPERAND (subexp0, 0);
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subsubexp1 = TREE_OPERAND (subexp0, 1);
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code0 = TREE_CODE (subsubexp0);
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code1 = TREE_CODE (subsubexp1);
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if (code0 == NOP_EXPR && code1 == NOP_EXPR
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&& (TYPE_PRECISION (TREE_TYPE (TREE_OPERAND (subsubexp0, 0)))
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< TYPE_PRECISION (TREE_TYPE (subsubexp0)))
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&& (TYPE_PRECISION (TREE_TYPE (TREE_OPERAND (subsubexp0, 0)))
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== TYPE_PRECISION (TREE_TYPE (TREE_OPERAND (subsubexp1, 0))))
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&& (TYPE_UNSIGNED (TREE_TYPE (TREE_OPERAND (subsubexp0, 0)))
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== TYPE_UNSIGNED (TREE_TYPE (TREE_OPERAND (subsubexp1, 0)))))
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{
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tree op0type = TREE_TYPE (TREE_OPERAND (subsubexp0, 0));
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enum machine_mode innermode = TYPE_MODE (op0type);
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bool zextend_p = TYPE_UNSIGNED (op0type);
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this_optab = zextend_p ? umadd_widen_optab : smadd_widen_optab;
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if (mode == GET_MODE_2XWIDER_MODE (innermode)
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&& (this_optab->handlers[(int) mode].insn_code
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!= CODE_FOR_nothing))
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{
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expand_operands (TREE_OPERAND (subsubexp0, 0),
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TREE_OPERAND (subsubexp1, 0),
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NULL_RTX, &op0, &op1, EXPAND_NORMAL);
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op2 = expand_expr (TREE_OPERAND (exp, 1), subtarget,
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VOIDmode, 0);
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temp = expand_ternary_op (mode, this_optab, op0, op1, op2,
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target, unsignedp);
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gcc_assert (temp);
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return REDUCE_BIT_FIELD (temp);
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}
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}
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}
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/* If we are adding a constant, a VAR_DECL that is sp, fp, or ap, and
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/* If we are adding a constant, a VAR_DECL that is sp, fp, or ap, and
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something else, make sure we add the register to the constant and
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something else, make sure we add the register to the constant and
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then to the other thing. This case can occur during strength
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then to the other thing. This case can occur during strength
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@ -85,6 +85,8 @@ static const char * const optabs[] =
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"smul_widen_optab->handlers[$B].insn_code = CODE_FOR_$(mul$a$b3$)$N",
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"smul_widen_optab->handlers[$B].insn_code = CODE_FOR_$(mul$a$b3$)$N",
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"umul_widen_optab->handlers[$B].insn_code = CODE_FOR_$(umul$a$b3$)$N",
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"umul_widen_optab->handlers[$B].insn_code = CODE_FOR_$(umul$a$b3$)$N",
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"usmul_widen_optab->handlers[$B].insn_code = CODE_FOR_$(usmul$a$b3$)$N",
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"usmul_widen_optab->handlers[$B].insn_code = CODE_FOR_$(usmul$a$b3$)$N",
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"smadd_widen_optab->handlers[$B].insn_code = CODE_FOR_$(madd$a$b4$)$N",
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"umadd_widen_optab->handlers[$B].insn_code = CODE_FOR_$(umadd$a$b4$)$N",
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"sdiv_optab->handlers[$A].insn_code = CODE_FOR_$(div$a3$)",
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"sdiv_optab->handlers[$A].insn_code = CODE_FOR_$(div$a3$)",
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"sdivv_optab->handlers[$A].insn_code = CODE_FOR_$(div$V$I$a3$)",
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"sdivv_optab->handlers[$A].insn_code = CODE_FOR_$(div$V$I$a3$)",
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"udiv_optab->handlers[$A].insn_code = CODE_FOR_$(udiv$I$a3$)",
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"udiv_optab->handlers[$A].insn_code = CODE_FOR_$(udiv$I$a3$)",
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@ -5439,6 +5439,8 @@ init_optabs (void)
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smul_widen_optab = init_optab (UNKNOWN);
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smul_widen_optab = init_optab (UNKNOWN);
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umul_widen_optab = init_optab (UNKNOWN);
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umul_widen_optab = init_optab (UNKNOWN);
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usmul_widen_optab = init_optab (UNKNOWN);
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usmul_widen_optab = init_optab (UNKNOWN);
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smadd_widen_optab = init_optab (UNKNOWN);
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umadd_widen_optab = init_optab (UNKNOWN);
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sdiv_optab = init_optab (DIV);
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sdiv_optab = init_optab (DIV);
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sdivv_optab = init_optabv (DIV);
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sdivv_optab = init_optabv (DIV);
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sdivmod_optab = init_optab (UNKNOWN);
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sdivmod_optab = init_optab (UNKNOWN);
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@ -86,6 +86,12 @@ enum optab_index
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OTI_umul_widen,
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OTI_umul_widen,
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/* Widening multiply of one unsigned and one signed operand. */
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/* Widening multiply of one unsigned and one signed operand. */
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OTI_usmul_widen,
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OTI_usmul_widen,
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/* Signed multiply and add with the result and addend one machine mode
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wider than the multiplicand and multiplier. */
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OTI_smadd_widen,
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/* Unigned multiply and add with the result and addend one machine mode
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wider than the multiplicand and multiplier. */
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OTI_umadd_widen,
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/* Signed divide */
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/* Signed divide */
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OTI_sdiv,
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OTI_sdiv,
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@ -309,6 +315,8 @@ extern GTY(()) optab optab_table[OTI_MAX];
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#define smul_widen_optab (optab_table[OTI_smul_widen])
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#define smul_widen_optab (optab_table[OTI_smul_widen])
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#define umul_widen_optab (optab_table[OTI_umul_widen])
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#define umul_widen_optab (optab_table[OTI_umul_widen])
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#define usmul_widen_optab (optab_table[OTI_usmul_widen])
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#define usmul_widen_optab (optab_table[OTI_usmul_widen])
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#define smadd_widen_optab (optab_table[OTI_smadd_widen])
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#define umadd_widen_optab (optab_table[OTI_umadd_widen])
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#define sdiv_optab (optab_table[OTI_sdiv])
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#define sdiv_optab (optab_table[OTI_sdiv])
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#define smulv_optab (optab_table[OTI_smulv])
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#define smulv_optab (optab_table[OTI_smulv])
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#define sdivv_optab (optab_table[OTI_sdivv])
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#define sdivv_optab (optab_table[OTI_sdivv])
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@ -1,3 +1,10 @@
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2007-04-24 Richard Sandiford <richard@nildram.co.uk>
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* gcc.target/mips/madd-1.c, gcc.target/mips/madd-2.c,
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* gcc.target/mips/madd-3.c, gcc.target/mips/madd-4.c,
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* gcc.target/mips/maddu-1.c, gcc.target/mips/maddu-2.c,
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* gcc.target/mips/maddu-3.c, gcc.target/mips/maddu-4.c: New tests.
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2007-04-23 Simon Baldwin <simonb@google.com>
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2007-04-23 Simon Baldwin <simonb@google.com>
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* g++.dg/other/error15.C: New.
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* g++.dg/other/error15.C: New.
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@ -0,0 +1,25 @@
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/* { dg-do compile } */
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||||||
|
/* { dg-mips-options "-O2 -march=vr4130 -mgp32" } */
|
||||||
|
/* { dg-final { scan-assembler-times "\tmacc\t\\\$1," 3 } } */
|
||||||
|
|
||||||
|
long long
|
||||||
|
f1 (int x, int y, long long z)
|
||||||
|
{
|
||||||
|
return (long long) x * y + z;
|
||||||
|
}
|
||||||
|
|
||||||
|
long long
|
||||||
|
f2 (int x, int y, long long z)
|
||||||
|
{
|
||||||
|
return z + (long long) y * x;
|
||||||
|
}
|
||||||
|
|
||||||
|
long long
|
||||||
|
f3 (int x, int y, long long z)
|
||||||
|
{
|
||||||
|
long long t = (long long) x * y;
|
||||||
|
int temp = 5;
|
||||||
|
if (temp == 5)
|
||||||
|
z += t;
|
||||||
|
return z;
|
||||||
|
}
|
|
@ -0,0 +1,25 @@
|
||||||
|
/* { dg-do compile } */
|
||||||
|
/* { dg-mips-options "-O2 -march=vr5500 -mgp32" } */
|
||||||
|
/* { dg-final { scan-assembler-times "\tmadd\t" 3 } } */
|
||||||
|
|
||||||
|
long long
|
||||||
|
f1 (int x, int y, long long z)
|
||||||
|
{
|
||||||
|
return (long long) x * y + z;
|
||||||
|
}
|
||||||
|
|
||||||
|
long long
|
||||||
|
f2 (int x, int y, long long z)
|
||||||
|
{
|
||||||
|
return z + (long long) y * x;
|
||||||
|
}
|
||||||
|
|
||||||
|
long long
|
||||||
|
f3 (int x, int y, long long z)
|
||||||
|
{
|
||||||
|
long long t = (long long) x * y;
|
||||||
|
int temp = 5;
|
||||||
|
if (temp == 5)
|
||||||
|
z += t;
|
||||||
|
return z;
|
||||||
|
}
|
|
@ -0,0 +1,25 @@
|
||||||
|
/* { dg-do compile } */
|
||||||
|
/* { dg-mips-options "-O2 -mips32 -mgp32" } */
|
||||||
|
/* { dg-final { scan-assembler-times "\tmadd\t" 3 } } */
|
||||||
|
|
||||||
|
long long
|
||||||
|
f1 (int x, int y, long long z)
|
||||||
|
{
|
||||||
|
return (long long) x * y + z;
|
||||||
|
}
|
||||||
|
|
||||||
|
long long
|
||||||
|
f2 (int x, int y, long long z)
|
||||||
|
{
|
||||||
|
return z + (long long) y * x;
|
||||||
|
}
|
||||||
|
|
||||||
|
long long
|
||||||
|
f3 (int x, int y, long long z)
|
||||||
|
{
|
||||||
|
long long t = (long long) x * y;
|
||||||
|
int temp = 5;
|
||||||
|
if (temp == 5)
|
||||||
|
z += t;
|
||||||
|
return z;
|
||||||
|
}
|
|
@ -0,0 +1,25 @@
|
||||||
|
/* { dg-do compile } */
|
||||||
|
/* { dg-mips-options "-O2 -mips32r2 -mdspr2 -mgp32" } */
|
||||||
|
/* { dg-final { scan-assembler-times "\tmadd\t\\\$ac" 3 } } */
|
||||||
|
|
||||||
|
long long
|
||||||
|
f1 (int x, int y, long long z)
|
||||||
|
{
|
||||||
|
return (long long) x * y + z;
|
||||||
|
}
|
||||||
|
|
||||||
|
long long
|
||||||
|
f2 (int x, int y, long long z)
|
||||||
|
{
|
||||||
|
return z + (long long) y * x;
|
||||||
|
}
|
||||||
|
|
||||||
|
long long
|
||||||
|
f3 (int x, int y, long long z)
|
||||||
|
{
|
||||||
|
long long t = (long long) x * y;
|
||||||
|
int temp = 5;
|
||||||
|
if (temp == 5)
|
||||||
|
z += t;
|
||||||
|
return z;
|
||||||
|
}
|
|
@ -0,0 +1,28 @@
|
||||||
|
/* { dg-do compile } */
|
||||||
|
/* { dg-mips-options "-O2 -march=vr4130 -mgp32" } */
|
||||||
|
/* { dg-final { scan-assembler-times "\tmaccu\t\\\$1," 3 } } */
|
||||||
|
|
||||||
|
typedef unsigned int ui;
|
||||||
|
typedef unsigned long long ull;
|
||||||
|
|
||||||
|
ull
|
||||||
|
f1 (ui x, ui y, ull z)
|
||||||
|
{
|
||||||
|
return (ull) x * y + z;
|
||||||
|
}
|
||||||
|
|
||||||
|
ull
|
||||||
|
f2 (ui x, ui y, ull z)
|
||||||
|
{
|
||||||
|
return z + (ull) y * x;
|
||||||
|
}
|
||||||
|
|
||||||
|
ull
|
||||||
|
f3 (ui x, ui y, ull z)
|
||||||
|
{
|
||||||
|
ull t = (ull) x * y;
|
||||||
|
int temp = 5;
|
||||||
|
if (temp == 5)
|
||||||
|
z += t;
|
||||||
|
return z;
|
||||||
|
}
|
|
@ -0,0 +1,28 @@
|
||||||
|
/* { dg-do compile } */
|
||||||
|
/* { dg-mips-options "-O2 -march=vr5500 -mgp32" } */
|
||||||
|
/* { dg-final { scan-assembler-times "\tmaddu\t" 3 } } */
|
||||||
|
|
||||||
|
typedef unsigned int ui;
|
||||||
|
typedef unsigned long long ull;
|
||||||
|
|
||||||
|
ull
|
||||||
|
f1 (ui x, ui y, ull z)
|
||||||
|
{
|
||||||
|
return (ull) x * y + z;
|
||||||
|
}
|
||||||
|
|
||||||
|
ull
|
||||||
|
f2 (ui x, ui y, ull z)
|
||||||
|
{
|
||||||
|
return z + (ull) y * x;
|
||||||
|
}
|
||||||
|
|
||||||
|
ull
|
||||||
|
f3 (ui x, ui y, ull z)
|
||||||
|
{
|
||||||
|
ull t = (ull) x * y;
|
||||||
|
int temp = 5;
|
||||||
|
if (temp == 5)
|
||||||
|
z += t;
|
||||||
|
return z;
|
||||||
|
}
|
|
@ -0,0 +1,28 @@
|
||||||
|
/* { dg-do compile } */
|
||||||
|
/* { dg-mips-options "-O2 -mips32 -mgp32" } */
|
||||||
|
/* { dg-final { scan-assembler-times "\tmaddu\t" 3 } } */
|
||||||
|
|
||||||
|
typedef unsigned int ui;
|
||||||
|
typedef unsigned long long ull;
|
||||||
|
|
||||||
|
ull
|
||||||
|
f1 (ui x, ui y, ull z)
|
||||||
|
{
|
||||||
|
return (ull) x * y + z;
|
||||||
|
}
|
||||||
|
|
||||||
|
ull
|
||||||
|
f2 (ui x, ui y, ull z)
|
||||||
|
{
|
||||||
|
return z + (ull) y * x;
|
||||||
|
}
|
||||||
|
|
||||||
|
ull
|
||||||
|
f3 (ui x, ui y, ull z)
|
||||||
|
{
|
||||||
|
ull t = (ull) x * y;
|
||||||
|
int temp = 5;
|
||||||
|
if (temp == 5)
|
||||||
|
z += t;
|
||||||
|
return z;
|
||||||
|
}
|
|
@ -0,0 +1,28 @@
|
||||||
|
/* { dg-do compile } */
|
||||||
|
/* { dg-mips-options "-O2 -mips32r2 -mdspr2 -mgp32" } */
|
||||||
|
/* { dg-final { scan-assembler-times "\tmaddu\t\\\$ac" 3 } } */
|
||||||
|
|
||||||
|
typedef unsigned int ui;
|
||||||
|
typedef unsigned long long ull;
|
||||||
|
|
||||||
|
ull
|
||||||
|
f1 (ui x, ui y, ull z)
|
||||||
|
{
|
||||||
|
return (ull) x * y + z;
|
||||||
|
}
|
||||||
|
|
||||||
|
ull
|
||||||
|
f2 (ui x, ui y, ull z)
|
||||||
|
{
|
||||||
|
return z + (ull) y * x;
|
||||||
|
}
|
||||||
|
|
||||||
|
ull
|
||||||
|
f3 (ui x, ui y, ull z)
|
||||||
|
{
|
||||||
|
ull t = (ull) x * y;
|
||||||
|
int temp = 5;
|
||||||
|
if (temp == 5)
|
||||||
|
z += t;
|
||||||
|
return z;
|
||||||
|
}
|
Loading…
Reference in New Issue