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[AArch64] Revert wrong commit of "Improve TLS Descriptor pattern to release RTL loop IV opt"

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Revert the wrong commit of

  2015-08-06    Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
	      Jiong Wang  <jiong.wang@arm.com>

	* config/aarch64/aarch64.d (tlsdesc_small_pseudo_<mode>): New pattern.
	* config/aarch64/aarch64.h (reg_class): New enumeration FIXED_REG0.
	(REG_CLASS_NAMES): Likewise.
	(REG_CLASS_CONTENTS): Likewise.
	* config/aarch64/aarch64.c (aarch64_class_max_nregs): Likewise.
	(aarch64_register_move_cost): Likewise.
	(aarch64_load_symref_appropriately): Invoke the new added pattern if
	possible.
	* config/aarch64/constraints.md (Uc0): New constraint.

From-SVN: r226756
This commit is contained in:
Jiong Wang 2015-08-10 10:00:56 +00:00
parent 9ca287086f
commit 7fd8646421
3 changed files with 5 additions and 58 deletions
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24
gcc/config/aarch64/aarch64.c
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@ -1048,26 +1048,12 @@ aarch64_load_symref_appropriately (rtx dest, rtx imm,
gcc_assert (mode == Pmode || mode == ptr_mode); gcc_assert (mode == Pmode || mode == ptr_mode);
if (can_create_pseudo_p ()) /* In ILP32, the got entry is always of SImode size. Unlike
{ small GOT, the dest is fixed at reg 0. */
rtx reg = gen_reg_rtx (mode); if (TARGET_ILP32)
emit_insn (gen_tlsdesc_small_si (imm));
if (TARGET_ILP32)
emit_insn (gen_tlsdesc_small_pseudo_si (imm, reg));
else
emit_insn (gen_tlsdesc_small_pseudo_di (imm, reg));
emit_use (reg);
}
else else
{ emit_insn (gen_tlsdesc_small_di (imm));
/* In ILP32, the got entry is always of SImode size. Unlike
small GOT, the dest is fixed at reg 0. */
if (TARGET_ILP32)
emit_insn (gen_tlsdesc_small_si (imm));
else
emit_insn (gen_tlsdesc_small_di (imm));
}
tp = aarch64_load_tp (NULL); tp = aarch64_load_tp (NULL);
if (mode != Pmode) if (mode != Pmode)

17
gcc/config/aarch64/aarch64.md
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@ -4549,23 +4549,6 @@
[(set_attr "type" "call") [(set_attr "type" "call")
(set_attr "length" "16")]) (set_attr "length" "16")])
;; The same as tlsdesc_small_<mode> except that we don't expose hard register X0
;; as the destination of set as it will cause trouble for RTL loop iv.
;; RTL loop iv will abort ongoing optimization once it finds there is hard reg
;; as destination of set. This pattern thus could help these tlsdesc
;; instruction sequences hoisted out of loop.
(define_insn "tlsdesc_small_pseudo_<mode>"
[(set (match_operand:PTR 1 "register_operand" "=r")
(unspec:PTR [(match_operand 0 "aarch64_valid_symref" "S")]
UNSPEC_TLSDESC))
(clobber (reg:DI R0_REGNUM))
(clobber (reg:DI LR_REGNUM))
(clobber (reg:CC CC_REGNUM))]
"TARGET_TLS_DESC"
"adrp\\tx0, %A0\;ldr\\t%<w>1, [x0, #%L0]\;add\\t<w>0, <w>0, %L0\;.tlsdesccall\\t%0\;blr\\t%1"
[(set_attr "type" "call")
(set_attr "length" "16")])
(define_insn "stack_tie" (define_insn "stack_tie"
[(set (mem:BLK (scratch)) [(set (mem:BLK (scratch))
(unspec:BLK [(match_operand:DI 0 "register_operand" "rk") (unspec:BLK [(match_operand:DI 0 "register_operand" "rk")

22
gcc/testsuite/gcc.target/aarch64/tlsdesc_hoist.c
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@ -1,22 +0,0 @@
/* { dg-do compile } */
/* { dg-require-effective-target tls_native } */
/* { dg-options "-O2 -fpic -fdump-rtl-loop2_invariant" } */
/* { dg-skip-if "-mcmodel=large, no support for -fpic" { aarch64-*-* } { "-mcmodel=large" } { "" } } */
int cal (int, int);
__thread int tls_data;
int
foo (int bound)
{
int i = 0;
int sum = 0;
for (i; i < bound; i++)
sum = cal (sum, tls_data);
return sum;
}
/* Insn sequences for TLS descriptor should be hoisted out of the loop. */
/* { dg-final { scan-rtl-dump "Decided" "loop2_invariant" } } */