Check in support for Xilinx MicroBlaze processor.

From-SVN: r164756
This commit is contained in:
Michael Eager 2010-09-30 18:21:57 +00:00
parent 51be162e8e
commit 809201325a
74 changed files with 9137 additions and 6 deletions

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@ -1,3 +1,8 @@
2010-09-30 Michael Eager <eager@eagercon.com>
* configure.ac (microblaze): Add target-libssp to noconfigdirs.
* configure: Regenerate.
2010-09-28 Michael Eager <eager@eagercon.com>
* MAINTAINERS (CPU Port Maintainers): Add myself for MicroBlaze port.

2
configure vendored
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@ -3650,7 +3650,7 @@ case "${target}" in
noconfigdirs="$noconfigdirs ld binutils gprof target-libgloss ${libgcj}"
;;
microblaze*)
noconfigdirs="$noconfigdirs gprof ${libgcj}"
noconfigdirs="$noconfigdirs gprof target-libssp ${libgcj}"
;;
mips*-sde-elf*)
skipdirs="$skipdirs target-libiberty"

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@ -887,7 +887,7 @@ case "${target}" in
noconfigdirs="$noconfigdirs ld binutils gprof target-libgloss ${libgcj}"
;;
microblaze*)
noconfigdirs="$noconfigdirs gprof ${libgcj}"
noconfigdirs="$noconfigdirs gprof target-libssp ${libgcj}"
;;
mips*-sde-elf*)
skipdirs="$skipdirs target-libiberty"

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@ -1,3 +1,27 @@
2010-09-30 Michael Eager <eager@eagercon.com>
* extend.texi (interrupt_handler): Add MicroBlaze to list.
(save_volatiles): Describe option for MicroBlaze.
* invoke.texi: Add MicroBlaze Options.
* contrib.texi: Add acknowledgment.
* md.texi: Add MicroBlaze d and z constraints.
* install.texi: Add microblaze-*-elf.
* configure.ac: Add microblaze-*-* to target list.
* configure: Regenerate.
* config.gcc: Add microblaze*-*-*, microblaze*-linux*.
* config/microblaze/microblaze-protos.h: New.
* config/microblaze/crti.s: New.
* config/microblaze/predicates.md: New.
* config/microblaze/linux.h: New.
* config/microblaze/microblaze.md: New.
* config/microblaze/constraints.md: New.
* config/microblaze/crtn.s: New.
* config/microblaze/microblaze.opt: New.
* config/microblaze/microblaze-c.c: New.
* config/microblaze/t-microblaze: New.
* config/microblaze/microblaze.c: New.
* config/microblaze/microblaze.h: New.
2010-09-30 Iain Sandoe <iains@gcc.gnu.org>
* c-parser.c (c_parser_objc_methodprotolist): Amend preceding comment,
@ -905,6 +929,7 @@
unconditionally if TODO_rebuild_alias is set, else only when optimizing
if TODO_update_address_taken is set.
>>>>>>> .r164755
2010-09-23 Anatoly Sokolov <aesok@post.ru>
* config/arm/arm.h (OUTPUT_ADDR_CONST_EXTRA): Remove.

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@ -350,6 +350,10 @@ m32r*-*-*)
m68k-*-*)
extra_headers=math-68881.h
;;
microblaze*-*-*)
cpu_type=microblaze
extra_options="${extra_options} g.opt"
;;
mips*-*-*)
cpu_type=mips
need_64bit_hwint=yes
@ -1757,6 +1761,19 @@ mep-*-*)
fi
use_gcc_stdint=wrap
;;
microblaze*-linux*)
tm_file="${tm_file} dbxelf.h linux.h microblaze/linux.h"
c_target_objs="${c_target_objs} microblaze-c.o"
cxx_target_objs="${cxx_target_objs} microblaze-c.o"
tmake_file="${tmake_file} t-slibgcc-elf-ver t-slibgcc-nolc-override t-linux microblaze/t-microblaze"
extra_parts="crtbegin.o crtbeginS.o crtend.o crtendS.o crtbeginT.o"
;;
microblaze*-*-*)
tm_file="${tm_file} dbxelf.h"
c_target_objs="${c_target_objs} microblaze-c.o"
cxx_target_objs="${cxx_target_objs} microblaze-c.o"
tmake_file="${tmake_file} microblaze/t-microblaze"
;;
mips-sgi-irix6.5*)
tm_file="elfos.h ${tm_file} mips/iris6.h"
tmake_file="mips/t-iris mips/t-iris6 mips/t-slibgcc-irix"

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@ -0,0 +1,72 @@
;; Constraint definitions for Xilinx MicroBlaze processors.
;; Copyright 2010 Free Software Foundation, Inc.
;; Contributed by Michael Eager <eager@eagercon.com>.
;; This file is part of GCC.
;; GCC is free software; you can redistribute it and/or modify
;; it under the terms of the GNU General Public License as published by
;; the Free Software Foundation; either version 3, or (at your option)
;; any later version.
;; GCC is distributed in the hope that it will be useful,
;; but WITHOUT ANY WARRANTY; without even the implied warranty of
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
;; GNU General Public License for more details.
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
(define_register_constraint "d" "GR_REGS"
"A general register.")
(define_register_constraint "z" "ST_REGS"
"A status register.")
;; Define integer constraints
(define_constraint "I"
"A signed 16-bit constant."
(and (match_code "const_int")
(match_test "SMALL_OPERAND (ival)")))
(define_constraint "J"
"Integer zero."
(and (match_code "const_int")
(match_test "ival == 0")))
(define_constraint "M"
"A constant which needs two instructions to load."
(and (match_code "const_int")
(match_test "LARGE_OPERAND (ival)")))
(define_constraint "N"
"A constant in the range -65535 to -1 (inclusive)."
(and (match_code "const_int")
(match_test "(unsigned HOST_WIDE_INT) (ival + 0xffff) < 0xffff")))
(define_constraint "P"
"A constant in the range 1 to 65535 (inclusive)."
(and (match_code "const_int")
(match_test "ival > 0 && ival < 0x10000")))
;; Define floating point constraints
(define_constraint "G"
"Floating-point zero."
(and (match_code "const_double")
(match_test "op == CONST0_RTX (mode)")))
;; Define memory constraints
(define_memory_constraint "R"
"Memory operand which fits in single instruction."
(and (match_code "mem")
(match_test "simple_memory_operand (op, GET_MODE (op))")))
(define_memory_constraint "T"
"Double word operand."
(and (match_code "mem")
(match_test "double_memory_operand (op, GET_MODE (op))")))

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@ -0,0 +1,39 @@
/* crti.s for __init, __fini
This file supplies the prologue for __init and __fini routines
Copyright 2009, 2010 Free Software Foundation, Inc.
Contributed by Michael Eager <eager@eagercon.com>.
This file is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by the
Free Software Foundation; either version 3, or (at your option) any
later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .init, "ax"
.global __init
.align 2
__init:
addik r1, r1, -8
sw r15, r0, r1
.section .fini, "ax"
.global __fini
.align 2
__fini:
addik r1, r1, -8
sw r15, r0, r1

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@ -0,0 +1,35 @@
/* crtn.s for __init, __fini
This file supplies the epilogue for __init and __fini routines
Copyright 2009, 2010 Free Software Foundation, Inc.
Contributed by Michael Eager <eager@eagercon.com>.
This file is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by the
Free Software Foundation; either version 3, or (at your option) any
later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .init, "ax"
lw r15, r0, r1
rtsd r15, 8
addik r1, r1, 8
.section .fini, "ax"
lw r15, r0, r1
rtsd r15, 8
addik r1, r1, 8

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@ -0,0 +1,35 @@
/* Definitions for MicroBlaze running Linux.
Copyright 2009, 2010 Free Software Foundation, Inc.
This file is part of GCC.
Contributed by Michael Eager <eager@eagercon.com>.
GCC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
GCC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
#define DYNAMIC_LINKER "/lib/ld.so.1"
#undef SUBTARGET_EXTRA_SPECS
#define SUBTARGET_EXTRA_SPECS \
{ "dynamic_linker", DYNAMIC_LINKER }
#undef LINK_SPEC
#define LINK_SPEC "%{shared:-shared} \
%{!shared: \
%{!static: \
%{rdynamic:-export-dynamic} \
%{!dynamic-linker:-dynamic-linker %(dynamic_linker)}} \
%{static:-static}}"

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@ -0,0 +1,93 @@
/* Subroutines used for the C front end for Xilinx MicroBlaze.
Copyright 2010 Free Software Foundation, Inc.
Contributed by Michael Eager <eager@eagercon.com>.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
#include "config.h"
#include "system.h"
#include "coretypes.h"
#include "tm.h"
#include "cpplib.h"
#include "tree.h"
#include "c-family/c-common.h"
#include "toplev.h"
#include "tm_p.h"
#include "target.h"
#define builtin_define(TXT) cpp_define (pfile, TXT)
#define builtin_assert(TXT) cpp_assert (pfile, TXT)
/* Define preprocessor symbols for MicroBlaze.
Symbols which do not start with __ are deprecated. */
void
microblaze_cpp_define (cpp_reader *pfile)
{
builtin_assert ("cpu=microblaze");
builtin_assert ("machine=microblaze");
builtin_define ("__MICROBLAZE__");
if (!TARGET_SOFT_MUL)
{
if (!flag_iso)
builtin_define ("HAVE_HW_MUL");
builtin_define ("__HAVE_HW_MUL__");
}
if (TARGET_MULTIPLY_HIGH)
{
if (!flag_iso)
builtin_define ("HAVE_HW_MUL_HIGH");
builtin_define ("__HAVE_HW_MUL_HIGH__");
}
if (!TARGET_SOFT_DIV)
{
if (!flag_iso)
builtin_define ("HAVE_HW_DIV");
builtin_define ("__HAVE_HW_DIV__");
}
if (TARGET_BARREL_SHIFT)
{
if (!flag_iso)
builtin_define ("HAVE_HW_BSHIFT");
builtin_define ("__HAVE_HW_BSHIFT__");
}
if (TARGET_PATTERN_COMPARE)
{
if (!flag_iso)
builtin_define ("HAVE_HW_PCMP");
builtin_define ("__HAVE_HW_PCMP__");
}
if (TARGET_HARD_FLOAT)
{
if (!flag_iso)
builtin_define ("HAVE_HW_FPU");
builtin_define ("__HAVE_HW_FPU__");
}
if (TARGET_FLOAT_CONVERT)
{
if (!flag_iso)
builtin_define ("HAVE_HW_FPU_CONVERT");
builtin_define ("__HAVE_HW_FPU_CONVERT__");
}
if (TARGET_FLOAT_SQRT)
{
if (!flag_iso)
builtin_define ("HAVE_HW_FPU_SQRT");
builtin_define ("__HAVE_HW_FPU_SQRT__");
}
}

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@ -0,0 +1,64 @@
/* Definitions of target machine for GNU compiler, for Xilinx MicroBlaze.
Copyright 2009, 2010 Free Software Foundation, Inc.
This file is part of GCC.
Contributed by Michael Eager <eager@eagercon.com>.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
#ifndef GCC_MICROBLAZE_PROTOS_H
#define GCC_MICROBLAZE_PROTOS_H
#ifdef RTX_CODE
extern int pic_address_needs_scratch (rtx);
extern void expand_block_move (rtx *);
extern void microblaze_expand_prologue (void);
extern void microblaze_expand_epilogue (void);
extern void override_options (void);
extern int microblaze_expand_shift (rtx *);
extern bool microblaze_expand_move (enum machine_mode, rtx *);
extern bool microblaze_expand_block_move (rtx, rtx, rtx, rtx);
extern void microblaze_expand_divide (rtx *);
extern void microblaze_expand_conditional_branch (enum machine_mode, rtx *);
extern void microblaze_expand_conditional_branch_sf (rtx *);
extern int microblaze_can_use_return_insn (void);
extern int microblaze_const_double_ok (rtx, enum machine_mode);
extern void print_operand (FILE *, rtx, int);
extern void print_operand_address (FILE *, rtx);
extern void init_cumulative_args (CUMULATIVE_ARGS *,tree, rtx);
extern bool microblaze_legitimate_address_p (enum machine_mode, rtx, bool);
extern int microblaze_is_interrupt_handler (void);
extern rtx microblaze_return_addr (int, rtx);
extern int simple_memory_operand (rtx, enum machine_mode);
extern int double_memory_operand (rtx, enum machine_mode);
extern int microblaze_regno_ok_for_base_p (int, int);
extern HOST_WIDE_INT microblaze_initial_elimination_offset (int, int);
extern void microblaze_declare_object (FILE *, const char *, const char *,
const char *, int);
extern void microblaze_asm_output_ident (FILE *, const char *);
#endif /* RTX_CODE */
#ifdef TREE_CODE
extern void function_arg_advance (CUMULATIVE_ARGS *, enum machine_mode,
tree, int);
extern rtx function_arg (CUMULATIVE_ARGS *, enum machine_mode, tree, int);
#endif /* TREE_CODE */
/* Declare functions in microblaze-c.c. */
extern void microblaze_cpp_define (struct cpp_reader *);
#endif /* GCC_MICROBLAZE_PROTOS_H */

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@ -0,0 +1,952 @@
/* Definitions of target machine for GNU compiler for Xilinx MicroBlaze.
Copyright 2009, 2010 Free Software Foundation, Inc.
Contributed by Michael Eager <eager@eagercon.com>.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
/* Standard GCC variables that we reference. */
/* MicroBlaze external variables defined in microblaze.c. */
/* Which pipeline to schedule for. */
enum pipeline_type
{
MICROBLAZE_PIPE_3 = 0,
MICROBLAZE_PIPE_5 = 1
};
#define MICROBLAZE_MASK_NO_UNSAFE_DELAY 0x00000001
/* print_operand punctuation chars */
extern char microblaze_print_operand_punct[];
/* # bytes of data/sdata cutoff */
extern int microblaze_section_threshold;
/* Map register # to debug register # */
extern int microblaze_dbx_regno[];
extern int microblaze_no_unsafe_delay;
extern enum pipeline_type microblaze_pipe;
#define OBJECT_FORMAT_ELF
/* Default target_flags if no switches are specified */
#define TARGET_DEFAULT (MASK_SOFT_MUL | MASK_SOFT_DIV | MASK_SOFT_FLOAT)
/* What is the default setting for -mcpu= . We set it to v4.00.a even though
we are actually ahead. This is safest version that has generate code
compatible for the original ISA */
#define MICROBLAZE_DEFAULT_CPU "v4.00.a"
/* Macros to decide whether certain features are available or not,
depending on the instruction set architecture level. */
#undef SWITCH_TAKES_ARG
#define SWITCH_TAKES_ARG(CHAR) \
(DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G')
/* We can debug without having a frame pointer. */
#define CAN_DEBUG_WITHOUT_FP
#define DRIVER_SELF_SPECS \
"%{mxl-soft-mul:%<mno-xl-soft-mul}", \
"%{mno-xl-barrel-shift:%<mxl-barrel-shift}", \
"%{mno-xl-pattern-compare:%<mxl-pattern-compare}", \
"%{mxl-soft-div:%<mno-xl-soft-div}", \
"%{msoft-float:%<mhard-float}"
/* Tell collect what flags to pass to nm. */
#ifndef NM_FLAGS
#define NM_FLAGS "-Bn"
#endif
/* Names to predefine in the preprocessor for this target machine. */
#define TARGET_CPU_CPP_BUILTINS() microblaze_cpp_define (pfile)
/* Assembler specs. */
#define TARGET_ASM_SPEC "%{v}"
#define ASM_SPEC "\
%{microblaze1} \
%(target_asm_spec)"
/* Extra switches sometimes passed to the linker. */
/* -xl-mode-xmdstub translated to -Zxl-mode-xmdstub -- deprecated. */
#define LINK_SPEC "%{shared:-shared} -N -relax \
%{Zxl-mode-xmdstub:-defsym _TEXT_START_ADDR=0x800} \
%{mxl-mode-xmdstub:-defsym _TEXT_START_ADDR=0x800} \
%{mxl-gp-opt:%{G*}} %{!mxl-gp-opt: -G 0} \
%{!Wl,-T*: %{!T*: -dT xilinx.ld%s}}"
/* Specs for the compiler proper */
#ifndef CC1_SPEC
#define CC1_SPEC " \
%{G*} %{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \
%{save-temps: } \
%(subtarget_cc1_spec) \
%{mxl-multiply-high:-mcpu=v6.00.a} \
"
#endif
#define EXTRA_SPECS \
{ "target_asm_spec", TARGET_ASM_SPEC }, \
SUBTARGET_EXTRA_SPECS
/* Print subsidiary information on the compiler version in use. */
#define MICROBLAZE_VERSION MICROBLAZE_DEFAULT_CPU
#ifndef MACHINE_TYPE
#define MACHINE_TYPE "MicroBlaze/ELF"
#endif
#ifndef TARGET_VERSION_INTERNAL
#define TARGET_VERSION_INTERNAL(STREAM) \
fprintf (STREAM, " %s %s", MACHINE_TYPE, MICROBLAZE_VERSION)
#endif
#ifndef TARGET_VERSION
#define TARGET_VERSION TARGET_VERSION_INTERNAL (stderr)
#endif
/* Local compiler-generated symbols must have a prefix that the assembler
understands. */
#ifndef LOCAL_LABEL_PREFIX
#define LOCAL_LABEL_PREFIX "$"
#endif
/* fixed registers. */
#define MB_ABI_BASE_REGNUM 0
#define MB_ABI_STACK_POINTER_REGNUM 1
#define MB_ABI_GPRO_REGNUM 2
#define MB_ABI_GPRW_REGNUM 13
#define MB_ABI_INTR_RETURN_ADDR_REGNUM 14
#define MB_ABI_SUB_RETURN_ADDR_REGNUM 15
#define MB_ABI_DEBUG_RETURN_ADDR_REGNUM 16
#define MB_ABI_EXCEPTION_RETURN_ADDR_REGNUM 17
#define MB_ABI_ASM_TEMP_REGNUM 18
/* This is our temp register. */
#define MB_ABI_FRAME_POINTER_REGNUM 19
#define MB_ABI_PIC_ADDR_REGNUM 20
#define MB_ABI_PIC_FUNC_REGNUM 21
/* Volatile registers. */
#define MB_ABI_INT_RETURN_VAL_REGNUM 3
#define MB_ABI_INT_RETURN_VAL2_REGNUM 4
#define MB_ABI_FIRST_ARG_REGNUM 5
#define MB_ABI_LAST_ARG_REGNUM 10
#define MB_ABI_MAX_ARG_REGS (MB_ABI_LAST_ARG_REGNUM \
- MB_ABI_FIRST_ARG_REGNUM + 1)
#define MB_ABI_STATIC_CHAIN_REGNUM 3
#define MB_ABI_TEMP1_REGNUM 11
#define MB_ABI_TEMP2_REGNUM 12
#define MB_ABI_MSR_SAVE_REG 11
/* Volatile register used to save MSR in interrupt handlers. */
/* Debug stuff. */
/* How to renumber registers for dbx and gdb. */
#define DBX_REGISTER_NUMBER(REGNO) microblaze_dbx_regno[(REGNO)]
/* Generate DWARF exception handling info. */
#define DWARF2_UNWIND_INFO 1
/* Don't generate .loc operations. */
#define DWARF2_ASM_LINE_DEBUG_INFO 0
/* The DWARF 2 CFA column which tracks the return address. */
#define DWARF_FRAME_RETURN_COLUMN \
(GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM)
/* Initial state of return address on entry to func = R15.
Actually, the RA is at R15+8, but gcc doesn't know how
to generate this.
NOTE: GDB has a workaround and expects this incorrect value.
If this is fixed, a corresponding fix to GDB is needed. */
#define INCOMING_RETURN_ADDR_RTX \
gen_rtx_REG (VOIDmode, GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM)
/* Use DWARF 2 debugging information by default. */
#define DWARF2_DEBUGGING_INFO
#define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
/* Target machine storage layout */
#define BITS_BIG_ENDIAN 0
#define BYTES_BIG_ENDIAN 1
#define WORDS_BIG_ENDIAN 1
#define BITS_PER_UNIT 8
#define BITS_PER_WORD 32
#define UNITS_PER_WORD 4
#define MIN_UNITS_PER_WORD 4
#define INT_TYPE_SIZE 32
#define SHORT_TYPE_SIZE 16
#define LONG_TYPE_SIZE 32
#define LONG_LONG_TYPE_SIZE 64
#define FLOAT_TYPE_SIZE 32
#define DOUBLE_TYPE_SIZE 64
#define LONG_DOUBLE_TYPE_SIZE 64
#define POINTER_SIZE 32
#define PARM_BOUNDARY 32
#define FUNCTION_BOUNDARY 32
#define EMPTY_FIELD_BOUNDARY 32
#define STRUCTURE_SIZE_BOUNDARY 8
#define BIGGEST_ALIGNMENT 32
#define STRICT_ALIGNMENT 1
#define PCC_BITFIELD_TYPE_MATTERS 1
#define CONSTANT_ALIGNMENT(EXP, ALIGN) \
((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
&& (ALIGN) < BITS_PER_WORD \
? BITS_PER_WORD \
: (ALIGN))
#define DATA_ALIGNMENT(TYPE, ALIGN) \
((((ALIGN) < BITS_PER_WORD) \
&& (TREE_CODE (TYPE) == ARRAY_TYPE \
|| TREE_CODE (TYPE) == UNION_TYPE \
|| TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
#define LOCAL_ALIGNMENT(TYPE, ALIGN) \
(((TREE_CODE (TYPE) == ARRAY_TYPE \
&& TYPE_MODE (TREE_TYPE (TYPE)) == QImode) \
&& (ALIGN) < BITS_PER_WORD) ? BITS_PER_WORD : (ALIGN))
#define WORD_REGISTER_OPERATIONS
#define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
if (GET_MODE_CLASS (MODE) == MODE_INT \
&& GET_MODE_SIZE (MODE) < 4) \
(MODE) = SImode;
/* Standard register usage. */
/* On the MicroBlaze, we have 32 integer registers */
#define FIRST_PSEUDO_REGISTER 36
#define FIXED_REGISTERS \
{ \
1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, \
1, 1, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1, 1, 1, 1 \
}
#define CALL_USED_REGISTERS \
{ \
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1, 1, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1, 1, 1, 1 \
}
#define GP_REG_FIRST 0
#define GP_REG_LAST 31
#define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
#define GP_DBX_FIRST 0
#define ST_REG 32
#define AP_REG_NUM 33
#define RAP_REG_NUM 34
#define FRP_REG_NUM 35
#define GP_REG_P(REGNO) ((unsigned) ((REGNO) - GP_REG_FIRST) < GP_REG_NUM)
#define ST_REG_P(REGNO) ((REGNO) == ST_REG)
#define HARD_REGNO_NREGS(REGNO, MODE) \
((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
/* Value is 1 if hard register REGNO can hold a value of machine-mode
MODE. In 32 bit mode, require that DImode and DFmode be in even
registers. For DImode, this makes some of the insns easier to
write, since you don't have to worry about a DImode value in
registers 3 & 4, producing a result in 4 & 5.
To make the code simpler HARD_REGNO_MODE_OK now just references an
array built in override_options. Because machmodes.h is not yet
included before this file is processed, the MODE bound can't be
expressed here. */
extern char microblaze_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
#define HARD_REGNO_MODE_OK(REGNO, MODE) \
microblaze_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO)]
#define MODES_TIEABLE_P(MODE1, MODE2) \
((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \
GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
== (GET_MODE_CLASS (MODE2) == MODE_FLOAT || \
GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
#define STACK_POINTER_REGNUM (GP_REG_FIRST + MB_ABI_STACK_POINTER_REGNUM)
#define STACK_POINTER_OFFSET FIRST_PARM_OFFSET(FNDECL)
/* Base register for access to local variables of the function. We
pretend that the frame pointer is
MB_ABI_INTR_RETURN_ADDR_REGNUM, and then eliminate it
to HARD_FRAME_POINTER_REGNUM. We can get away with this because
rMB_ABI_INTR_RETUREN_ADDR_REGNUM is a fixed
register(return address for interrupt), and will not be used for
anything else. */
#define FRAME_POINTER_REGNUM FRP_REG_NUM
#define HARD_FRAME_POINTER_REGNUM \
(GP_REG_FIRST + MB_ABI_FRAME_POINTER_REGNUM)
#define ARG_POINTER_REGNUM AP_REG_NUM
#define RETURN_ADDRESS_POINTER_REGNUM RAP_REG_NUM
#define STATIC_CHAIN_REGNUM \
(GP_REG_FIRST + MB_ABI_STATIC_CHAIN_REGNUM)
/* registers used in prologue/epilogue code when the stack frame
is larger than 32K bytes. These registers must come from the
scratch register set, and not used for passing and returning
arguments and any other information used in the calling sequence
(such as pic). */
#define MICROBLAZE_TEMP1_REGNUM \
(GP_REG_FIRST + MB_ABI_TEMP1_REGNUM)
#define MICROBLAZE_TEMP2_REGNUM \
(GP_REG_FIRST + MB_ABI_TEMP2_REGNUM)
#define NO_FUNCTION_CSE 1
#define PIC_OFFSET_TABLE_REGNUM \
(flag_pic ? (GP_REG_FIRST + MB_ABI_PIC_ADDR_REGNUM) : \
INVALID_REGNUM)
enum reg_class
{
NO_REGS, /* no registers in set. */
GR_REGS, /* integer registers. */
ST_REGS, /* status register. */
ALL_REGS, /* all registers. */
LIM_REG_CLASSES /* max value + 1. */
};
#define N_REG_CLASSES (int) LIM_REG_CLASSES
#define GENERAL_REGS GR_REGS
#define REG_CLASS_NAMES \
{ \
"NO_REGS", \
"GR_REGS", \
"ST_REGS", \
"ALL_REGS" \
}
#define REG_CLASS_CONTENTS \
{ \
{ 0x00000000, 0x00000000 }, /* no registers. */ \
{ 0xffffffff, 0x00000000 }, /* integer registers. */ \
{ 0x00000000, 0x00000001 }, /* status registers. */ \
{ 0xffffffff, 0x0000000f } /* all registers. */ \
}
extern enum reg_class microblaze_regno_to_class[];
#define REGNO_REG_CLASS(REGNO) microblaze_regno_to_class[ (REGNO) ]
#define BASE_REG_CLASS GR_REGS
#define INDEX_REG_CLASS GR_REGS
#define GR_REG_CLASS_P(CLASS) ((CLASS) == GR_REGS)
/* REGISTER AND CONSTANT CLASSES */
#define SMALL_INT(X) ((unsigned HOST_WIDE_INT) (INTVAL (X) + 0x8000) < 0x10000)
#define LARGE_INT(X) (INTVAL (X) >= 0x80000000 && INTVAL (X) <= 0xffffffff)
#define PLT_ADDR_P(X) (GET_CODE (X) == UNSPEC && XINT (X,1) == UNSPEC_PLT)
/* Test for a valid operand for a call instruction.
Don't allow the arg pointer register or virtual regs
since they may change into reg + const, which the patterns
can't handle yet. */
#define CALL_INSN_OP(X) (CONSTANT_ADDRESS_P (X) \
|| (GET_CODE (X) == REG && X != arg_pointer_rtx\
&& ! (REGNO (X) >= FIRST_PSEUDO_REGISTER \
&& REGNO (X) <= LAST_VIRTUAL_REGISTER)))
/* True if VALUE is a signed 16-bit number. */
#define SMALL_OPERAND(VALUE) \
((unsigned HOST_WIDE_INT) (VALUE) + 0x8000 < 0x10000)
/* Constant which cannot be loaded in one instruction. */
#define LARGE_OPERAND(VALUE) \
((((VALUE) & ~0x0000ffff) != 0) \
&& (((VALUE) & ~0x0000ffff) != ~0x0000ffff) \
&& (((VALUE) & 0x0000ffff) != 0 \
|| (((VALUE) & ~2147483647) != 0 \
&& ((VALUE) & ~2147483647) != ~2147483647)))
#define PREFERRED_RELOAD_CLASS(X,CLASS) \
((CLASS) != ALL_REGS \
? (CLASS) \
: ((GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
|| GET_MODE_CLASS (GET_MODE (X)) == MODE_COMPLEX_FLOAT) \
? (GR_REGS) \
: ((GET_MODE_CLASS (GET_MODE (X)) == MODE_INT \
|| GET_MODE (X) == VOIDmode) \
? (GR_REGS) : (CLASS))))
#define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
(GET_MODE_CLASS (MODE) == MODE_INT)
#define CLASS_MAX_NREGS(CLASS, MODE) \
((GET_MODE_SIZE (MODE) + (UNITS_PER_WORD) - 1) / (UNITS_PER_WORD))
/* Stack layout; function entry, exit and calling. */
#define STACK_GROWS_DOWNWARD
/* Changed the starting frame offset to including the new link stuff */
#define STARTING_FRAME_OFFSET \
(crtl->outgoing_args_size + FIRST_PARM_OFFSET(FNDECL))
/* The return address for the current frame is in r31 if this is a leaf
function. Otherwise, it is on the stack. It is at a variable offset
from sp/fp/ap, so we define a fake hard register rap which is a
poiner to the return address on the stack. This always gets eliminated
during reload to be either the frame pointer or the stack pointer plus
an offset. */
#define RETURN_ADDR_RTX(count, frame) \
microblaze_return_addr(count,frame)
extern struct microblaze_frame_info current_frame_info;
#define ELIMINABLE_REGS \
{{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
{ ARG_POINTER_REGNUM, GP_REG_FIRST + MB_ABI_FRAME_POINTER_REGNUM}, \
{ RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
{ RETURN_ADDRESS_POINTER_REGNUM, \
GP_REG_FIRST + MB_ABI_FRAME_POINTER_REGNUM}, \
{ RETURN_ADDRESS_POINTER_REGNUM, \
GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM}, \
{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
{ FRAME_POINTER_REGNUM, GP_REG_FIRST + MB_ABI_FRAME_POINTER_REGNUM}}
#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
(OFFSET) = microblaze_initial_elimination_offset ((FROM), (TO))
#define ACCUMULATE_OUTGOING_ARGS 1
#define FIRST_PARM_OFFSET(FNDECL) (UNITS_PER_WORD)
#define ARG_POINTER_CFA_OFFSET(FNDECL) 0
#define REG_PARM_STACK_SPACE(FNDECL) (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD)
#define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
#define STACK_BOUNDARY 32
#define NUM_OF_ARGS 6
#define GP_RETURN (GP_REG_FIRST + MB_ABI_INT_RETURN_VAL_REGNUM)
#define GP_ARG_FIRST (GP_REG_FIRST + MB_ABI_FIRST_ARG_REGNUM)
#define GP_ARG_LAST (GP_REG_FIRST + MB_ABI_LAST_ARG_REGNUM)
#define MAX_ARGS_IN_REGISTERS MB_ABI_MAX_ARG_REGS
#define LIBCALL_VALUE(MODE) \
gen_rtx_REG ( \
((GET_MODE_CLASS (MODE) != MODE_INT \
|| GET_MODE_SIZE (MODE) >= 4) \
? (MODE) \
: SImode), GP_RETURN)
/* 1 if N is a possible register number for a function value.
On the MicroBlaze, R2 R3 are the only register thus used.
Currently, R2 are only implemented here (C has no complex type) */
#define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN)
#define FUNCTION_ARG_REGNO_P(N) (((N) >= GP_ARG_FIRST && (N) <= GP_ARG_LAST))
typedef struct microblaze_args
{
int gp_reg_found; /* whether a gp register was found yet */
int arg_number; /* argument number */
int arg_words; /* # total words the arguments take */
int fp_arg_words; /* # words for FP args */
int last_arg_fp; /* nonzero if last arg was FP (EABI only) */
int fp_code; /* Mode of FP arguments */
int num_adjusts; /* number of adjustments made */
/* Adjustments made to args pass in regs. */
/* ??? The size is doubled to work around a bug in the code that sets the
adjustments in function_arg. */
struct rtx_def *adjust[MAX_ARGS_IN_REGISTERS * 2];
} CUMULATIVE_ARGS;
#define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,FNDECL,N_NAMED_ARGS) \
init_cumulative_args (&CUM, FNTYPE, LIBNAME)
#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
function_arg_advance (&CUM, MODE, TYPE, NAMED)
#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
function_arg( &CUM, MODE, TYPE, NAMED)
#define NO_PROFILE_COUNTERS 1
#define FUNCTION_PROFILER(FILE, LABELNO) { \
{ \
fprintf (FILE, "\tbrki\tr16,_mcount\n"); \
} \
}
#define EXIT_IGNORE_STACK 1
#define TRAMPOLINE_SIZE (32 + 8)
#define TRAMPOLINE_ALIGNMENT 32
#define REGNO_OK_FOR_BASE_P(regno) microblaze_regno_ok_for_base_p ((regno), 1)
#define REGNO_OK_FOR_INDEX_P(regno) microblaze_regno_ok_for_base_p ((regno), 1)
#ifndef REG_OK_STRICT
#define REG_STRICT_FLAG 0
#else
#define REG_STRICT_FLAG 1
#endif
#define REG_OK_FOR_BASE_P(X) \
microblaze_regno_ok_for_base_p (REGNO (X), REG_STRICT_FLAG)
#define REG_OK_FOR_INDEX_P(X) \
microblaze_regno_ok_for_base_p (REGNO (X), REG_STRICT_FLAG)
#define MAX_REGS_PER_ADDRESS 2
/* Identify valid constant addresses. Exclude if PIC addr which
needs scratch register. */
#define CONSTANT_ADDRESS_P(X) \
(GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
|| GET_CODE (X) == CONST_INT \
|| (GET_CODE (X) == CONST \
&& ! (flag_pic && pic_address_needs_scratch (X))))
/* Define this, so that when PIC, reload won't try to reload invalid
addresses which require two reload registers. */
#define LEGITIMATE_PIC_OPERAND_P(X) (!pic_address_needs_scratch (X))
/* At present, GAS doesn't understand li.[sd], so don't allow it
to be generated at present. */
#define LEGITIMATE_CONSTANT_P(X) \
(GET_CODE (X) != CONST_DOUBLE \
|| microblaze_const_double_ok (X, GET_MODE (X)))
#define CASE_VECTOR_MODE (SImode)
#ifndef DEFAULT_SIGNED_CHAR
#define DEFAULT_SIGNED_CHAR 1
#endif
#define MOVE_MAX 4
#define MAX_MOVE_MAX 8
#define SLOW_BYTE_ACCESS 1
/* sCOND operations return 1. */
#define STORE_FLAG_VALUE 1
#define SHIFT_COUNT_TRUNCATED 1
/* This results in inefficient code for 64 bit to 32 conversions.
Something needs to be done about this. Perhaps not use any 32 bit
instructions? Perhaps use PROMOTE_MODE? */
#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
#define Pmode SImode
#define FUNCTION_MODE SImode
/* Mode should alwasy be SImode */
#define REGISTER_MOVE_COST(MODE, FROM, TO) \
( GR_REG_CLASS_P (FROM) && GR_REG_CLASS_P (TO) ? 2 \
: (FROM) == ST_REGS && GR_REG_CLASS_P (TO) ? 4 \
: 12)
#define MEMORY_MOVE_COST(MODE,CLASS,TO_P) \
(4 + memory_move_secondary_cost ((MODE), (CLASS), (TO_P)))
#define BRANCH_COST(speed_p, predictable_p) 2
/* Control the assembler format that we output. */
#define ASM_APP_ON " #APP\n"
#define ASM_APP_OFF " #NO_APP\n"
#define REGISTER_NAMES { \
"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
"r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", \
"r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", \
"rmsr", "$ap", "$rap", "$frp" }
#define ADDITIONAL_REGISTER_NAMES \
{ \
{ "r0", 0 + GP_REG_FIRST }, \
{ "r1", 1 + GP_REG_FIRST }, \
{ "r2", 2 + GP_REG_FIRST }, \
{ "r3", 3 + GP_REG_FIRST }, \
{ "r4", 4 + GP_REG_FIRST }, \
{ "r5", 5 + GP_REG_FIRST }, \
{ "r6", 6 + GP_REG_FIRST }, \
{ "r7", 7 + GP_REG_FIRST }, \
{ "r8", 8 + GP_REG_FIRST }, \
{ "r9", 9 + GP_REG_FIRST }, \
{ "r10", 10 + GP_REG_FIRST }, \
{ "r11", 11 + GP_REG_FIRST }, \
{ "r12", 12 + GP_REG_FIRST }, \
{ "r13", 13 + GP_REG_FIRST }, \
{ "r14", 14 + GP_REG_FIRST }, \
{ "r15", 15 + GP_REG_FIRST }, \
{ "r16", 16 + GP_REG_FIRST }, \
{ "r17", 17 + GP_REG_FIRST }, \
{ "r18", 18 + GP_REG_FIRST }, \
{ "r19", 19 + GP_REG_FIRST }, \
{ "r20", 20 + GP_REG_FIRST }, \
{ "r21", 21 + GP_REG_FIRST }, \
{ "r22", 22 + GP_REG_FIRST }, \
{ "r23", 23 + GP_REG_FIRST }, \
{ "r24", 24 + GP_REG_FIRST }, \
{ "r25", 25 + GP_REG_FIRST }, \
{ "r26", 26 + GP_REG_FIRST }, \
{ "r27", 27 + GP_REG_FIRST }, \
{ "r28", 28 + GP_REG_FIRST }, \
{ "r29", 29 + GP_REG_FIRST }, \
{ "r30", 30 + GP_REG_FIRST }, \
{ "r31", 31 + GP_REG_FIRST }, \
{ "rmsr", ST_REG} \
}
#define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
#define PRINT_OPERAND_PUNCT_VALID_P(CODE) microblaze_print_operand_punct[CODE]
#define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
/* ASM_OUTPUT_ALIGNED_COMMON and ASM_OUTPUT_ALIGNED_LOCAL
Unfortunately, we still need to set the section explicitly. Somehow,
our binutils assign .comm and .lcomm variables to the "current" section
in the assembly file, rather than where they implicitly belong. We need to
remove this explicit setting in GCC when binutils can understand sections
better. */
#undef ASM_OUTPUT_ALIGNED_COMMON
#define ASM_OUTPUT_ALIGNED_COMMON(FILE, NAME, SIZE, ALIGN) \
do { \
if (SIZE > 0 && SIZE <= microblaze_section_threshold \
&& TARGET_XLGPOPT) \
{ \
switch_to_section (sbss_section); \
} \
else \
{ \
switch_to_section (bss_section); \
} \
fprintf (FILE, "%s", COMMON_ASM_OP); \
assemble_name ((FILE), (NAME)); \
fprintf ((FILE), ","HOST_WIDE_INT_PRINT_UNSIGNED",%u\n", \
(SIZE), (ALIGN) / BITS_PER_UNIT); \
ASM_OUTPUT_TYPE_DIRECTIVE (FILE, NAME, "object"); \
} while (0)
#undef ASM_OUTPUT_ALIGNED_LOCAL
#define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGN) \
do { \
if (SIZE > 0 && SIZE <= microblaze_section_threshold \
&& TARGET_XLGPOPT) \
{ \
switch_to_section (sbss_section); \
} \
else \
{ \
switch_to_section (bss_section); \
} \
fprintf (FILE, "%s", LCOMMON_ASM_OP); \
assemble_name ((FILE), (NAME)); \
fprintf ((FILE), ","HOST_WIDE_INT_PRINT_UNSIGNED",%u\n", \
(SIZE), (ALIGN) / BITS_PER_UNIT); \
ASM_OUTPUT_TYPE_DIRECTIVE (FILE, NAME, "object"); \
} while (0)
#define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
do { \
ASM_OUTPUT_ALIGNED_LOCAL (FILE, NAME, SIZE, ALIGN); \
} while (0)
#define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL) \
{ \
}
#define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
#define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
fprintf (STREAM, "\t%s\t%sL%d\n", \
".gpword", \
LOCAL_LABEL_PREFIX, VALUE)
#define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
do { \
if (flag_pic == 2) \
fprintf (STREAM, "\t%s\t%sL%d@GOTOFF\n", \
".gpword", \
LOCAL_LABEL_PREFIX, VALUE); \
else \
fprintf (STREAM, "\t%s\t%sL%d\n", \
".gpword", \
LOCAL_LABEL_PREFIX, VALUE); \
} while (0)
#define ASM_OUTPUT_ALIGN(STREAM,LOG) \
fprintf (STREAM, "\t.align\t%d\n", (LOG))
#define ASM_OUTPUT_SKIP(STREAM,SIZE) \
fprintf (STREAM, "\t.space\t%lu\n", (SIZE))
#define ASCII_DATA_ASM_OP "\t.ascii\t"
#define STRING_ASM_OP "\t.asciz\t"
#define ASM_OUTPUT_IDENT(FILE, STRING) \
microblaze_asm_output_ident (FILE, STRING)
/* Default to -G 8 */
#ifndef MICROBLAZE_DEFAULT_GVALUE
#define MICROBLAZE_DEFAULT_GVALUE 8
#endif
/* Given a decl node or constant node, choose the section to output it in
and select that section. */
/* Store in OUTPUT a string (made with alloca) containing
an assembler-name for a local static variable named NAME.
LABELNO is an integer which is different for each call. */
#define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
/* How to start an assembler comment.
The leading space is important (the microblaze assembler requires it). */
#ifndef ASM_COMMENT_START
#define ASM_COMMENT_START " #"
#endif
#define BSS_VAR 1
#define SBSS_VAR 2
#define DATA_VAR 4
#define SDATA_VAR 5
#define RODATA_VAR 6
#define SDATA2_VAR 7
/* These definitions are used in with the shift_type flag in the rtl. */
#define SHIFT_CONST 1
#define SHIFT_REG 2
#define USE_ADDK 3
/* Handle interrupt attribute. */
extern int interrupt_handler;
extern int save_volatiles;
#define INTERRUPT_HANDLER_NAME "_interrupt_handler"
/* These #define added for C++. */
#define UNALIGNED_SHORT_ASM_OP ".data16"
#define UNALIGNED_INT_ASM_OP ".data32"
#define UNALIGNED_DOUBLE_INT_ASM_OP ".data8"
#define ASM_BYTE_OP ".data8"
/* The following #defines are used in the headers files. Always retain these. */
/* Added for declaring size at the end of the function. */
#undef ASM_DECLARE_FUNCTION_SIZE
#define ASM_DECLARE_FUNCTION_SIZE(FILE, FNAME, DECL) \
do { \
if (!flag_inhibit_size_directive) \
{ \
char label[256]; \
static int labelno; \
labelno++; \
ASM_GENERATE_INTERNAL_LABEL (label, "Lfe", labelno); \
(*targetm.asm_out.internal_label) (FILE, "Lfe", labelno); \
fprintf (FILE, "%s", SIZE_ASM_OP); \
assemble_name (FILE, (FNAME)); \
fprintf (FILE, ","); \
assemble_name (FILE, label); \
fprintf (FILE, "-"); \
assemble_name (FILE, (FNAME)); \
putc ('\n', FILE); \
} \
} while (0)
#define GLOBAL_ASM_OP "\t.globl\t"
#define TYPE_ASM_OP "\t.type\t"
#define SIZE_ASM_OP "\t.size\t"
#define COMMON_ASM_OP "\t.comm\t"
#define LCOMMON_ASM_OP "\t.lcomm\t"
#define MAX_OFILE_ALIGNMENT (32768*8)
#define TYPE_OPERAND_FMT "@%s"
/* Write the extra assembler code needed to declare an object properly. */
#undef ASM_DECLARE_OBJECT_NAME
#define ASM_DECLARE_OBJECT_NAME(FILE, NAME, DECL) \
do { \
fprintf (FILE, "%s", TYPE_ASM_OP); \
assemble_name (FILE, NAME); \
putc (',', FILE); \
fprintf (FILE, TYPE_OPERAND_FMT, "object"); \
putc ('\n', FILE); \
size_directive_output = 0; \
if (!flag_inhibit_size_directive && DECL_SIZE (DECL)) \
{ \
size_directive_output = 1; \
fprintf (FILE, "%s", SIZE_ASM_OP); \
assemble_name (FILE, NAME); \
fprintf (FILE, ",%d\n", int_size_in_bytes (TREE_TYPE (DECL))); \
} \
microblaze_declare_object (FILE, NAME, "", ":\n", 0); \
} while (0)
#undef ASM_FINISH_DECLARE_OBJECT
#define ASM_FINISH_DECLARE_OBJECT(FILE, DECL, TOP_LEVEL, AT_END) \
do { \
char *name = XSTR (XEXP (DECL_RTL (DECL), 0), 0); \
if (!flag_inhibit_size_directive && DECL_SIZE (DECL) \
&& ! AT_END && TOP_LEVEL \
&& DECL_INITIAL (DECL) == error_mark_node \
&& !size_directive_output) \
{ \
size_directive_output = 1; \
fprintf (FILE, "%s", SIZE_ASM_OP); \
assemble_name (FILE, name); \
fprintf (FILE, ",%d\n", int_size_in_bytes (TREE_TYPE (DECL))); \
} \
} while (0)
#define ASM_OUTPUT_DEF(FILE,LABEL1,LABEL2) \
do { fputc ( '\t', FILE); \
assemble_name (FILE, LABEL1); \
fputs ( " = ", FILE); \
assemble_name (FILE, LABEL2); \
fputc ( '\n', FILE); \
} while (0)
#define ASM_WEAKEN_LABEL(FILE,NAME) \
do { fputs ("\t.weakext\t", FILE); \
assemble_name (FILE, NAME); \
fputc ('\n', FILE); \
} while (0)
#define MAKE_DECL_ONE_ONLY(DECL) (DECL_WEAK (DECL) = 1)
#undef UNIQUE_SECTION_P
#define UNIQUE_SECTION_P(DECL) (DECL_ONE_ONLY (DECL))
#undef TARGET_ASM_NAMED_SECTION
#define TARGET_ASM_NAMED_SECTION default_elf_asm_named_section
/* Define the strings to put out for each section in the object file.
Note: For ctors/dtors, we want to give these sections the SHF_WRITE
attribute to allow shared libraries to patch/resolve addresses into
these locations. On Microblaze, there is no concept of shared libraries
yet, so this is for future use. */
#define TEXT_SECTION_ASM_OP "\t.text"
#define DATA_SECTION_ASM_OP "\t.data"
#define READONLY_DATA_SECTION_ASM_OP \
"\t.rodata"
#define BSS_SECTION_ASM_OP "\t.bss"
#define CTORS_SECTION_ASM_OP "\t.section\t.ctors,\"aw\""
#define DTORS_SECTION_ASM_OP "\t.section\t.dtors,\"aw\""
#define INIT_SECTION_ASM_OP "\t.section\t.init,\"ax\""
#define FINI_SECTION_ASM_OP "\t.section\t.fini,\"ax\""
#define SDATA_SECTION_ASM_OP "\t.sdata" /* Small RW initialized data */
#define SDATA2_SECTION_ASM_OP "\t.sdata2" /* Small RO initialized data */
#define SBSS_SECTION_ASM_OP "\t.sbss" /* Small RW uninitialized data */
#define SBSS2_SECTION_ASM_OP "\t.sbss2" /* Small RO uninitialized data */
#define HOT_TEXT_SECTION_NAME ".text.hot"
#define UNLIKELY_EXECUTED_TEXT_SECTION_NAME \
".text.unlikely"
/* We do this to save a few 10s of code space that would be taken up
by the call_FUNC () wrappers, used by the generic CRT_CALL_STATIC_FUNCTION
definition in crtstuff.c. */
#define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
asm ( SECTION_OP "\n" \
"\tbrlid r15, " #FUNC "\n\t nop\n" \
TEXT_SECTION_ASM_OP);
/* We need to group -lm as well, since some Newlib math functions
reference __errno! */
#undef LIB_SPEC
#define LIB_SPEC \
"%{!nostdlib: \
%{pg:-start-group -lxilprofile -lgloss -lxil -lc -lm -end-group } \
%{!pg:-start-group -lgloss -lxil -lc -lm -end-group }} "
#undef ENDFILE_SPEC
#define ENDFILE_SPEC "crtend.o%s crtn.o%s"
#define STARTFILE_EXECUTABLE_SPEC "crt0.o%s crti.o%s crtbegin.o%s"
#define STARTFILE_XMDSTUB_SPEC "crt1.o%s crti.o%s crtbegin.o%s"
#define STARTFILE_BOOTSTRAP_SPEC "crt2.o%s crti.o%s crtbegin.o%s"
#define STARTFILE_NOVECTORS_SPEC "crt3.o%s crti.o%s crtbegin.o%s"
#define STARTFILE_CRTINIT_SPEC "%{!pg: %{!mno-clearbss: crtinit.o%s} \
%{mno-clearbss: sim-crtinit.o%s}} \
%{pg: %{!mno-clearbss: pgcrtinit.o%s} %{mno-clearbss: sim-pgcrtinit.o%s}}"
#define STARTFILE_DEFAULT_SPEC STARTFILE_EXECUTABLE_SPEC
#undef SUBTARGET_EXTRA_SPECS
#define SUBTARGET_EXTRA_SPECS \
{ "startfile_executable", STARTFILE_EXECUTABLE_SPEC }, \
{ "startfile_xmdstub", STARTFILE_XMDSTUB_SPEC }, \
{ "startfile_bootstrap", STARTFILE_BOOTSTRAP_SPEC }, \
{ "startfile_novectors", STARTFILE_NOVECTORS_SPEC }, \
{ "startfile_crtinit", STARTFILE_CRTINIT_SPEC }, \
{ "startfile_default", STARTFILE_DEFAULT_SPEC },
#undef STARTFILE_SPEC
#define STARTFILE_SPEC "\
%{Zxl-mode-executable : %(startfile_executable) ; \
mxl-mode-executable : %(startfile_executable) ; \
Zxl-mode-xmdstub : %(startfile_xmdstub) ; \
mxl-mode-xmdstub : %(startfile_xmdstub) ; \
Zxl-mode-bootstrap : %(startfile_bootstrap) ; \
mxl-mode-bootstrap : %(startfile_bootstrap) ; \
Zxl-mode-novectors : %(startfile_novectors) ; \
mxl-mode-novectors : %(startfile_novectors) ; \
Zxl-mode-xilkernel : %(startfile_xilkernel) ; \
mxl-mode-xilkernel : %(startfile_xilkernel) ; \
: %(startfile_default) \
} \
%(startfile_crtinit)"

File diff suppressed because it is too large Load Diff

View File

@ -0,0 +1,97 @@
; Options for the MicroBlaze port of the compiler
;
; Copyright 2009, 2010 Free Software Foundation, Inc.
;
; Contributed by Michael Eager <eager@eagercon.com>.
;
; This file is part of GCC.
;
; GCC is free software; you can redistribute it and/or modify it under
; the terms of the GNU General Public License as published by the Free
; Software Foundation; either version 3, or (at your option) any later
; version.
;
; GCC is distributed in the hope that it will be useful, but WITHOUT
; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
; License for more details.
;
; You should have received a copy of the GNU General Public License
; along with GCC; see the file COPYING3. If not see
; <http://www.gnu.org/licenses/>. */
msoft-float
Target Report RejectNegative Mask(SOFT_FLOAT)
Use software emulation for floating point (default)
mhard-float
Target Report RejectNegative InverseMask(SOFT_FLOAT, HARD_FLOAT)
Use hardware floating point instructions
msmall-divides
Target Mask(SMALL_DIVIDES)
Use table lookup optimization for small signed integer divisions
mcpu=
Target RejectNegative Joined Var(microblaze_select_cpu)
-mcpu=PROCESSOR Use features of and schedule code for given CPU
mmemcpy
Target Mask(MEMCPY)
Don't optimize block moves, use memcpy
mxl-soft-mul
Target Mask(SOFT_MUL)
Use the soft multiply emulation (default)
mxl-soft-div
Target Mask(SOFT_DIV)
Use the software emulation for divides (default)
mxl-barrel-shift
Target Mask(BARREL_SHIFT)
Use the hardware barrel shifter instead of emulation
mxl-pattern-compare
Target Mask(PATTERN_COMPARE)
Use pattern compare instructions
mxl-stack-check
Target Mask(STACK_CHECK)
Check for stack overflow at runtime
mxl-gp-opt
Target Mask(XLGPOPT)
Use GP relative sdata/sbss sections
mno-clearbss
Target RejectNegative
Clear the BSS to zero and place zero initialized in BSS
mxl-multiply-high
Target Mask(MULTIPLY_HIGH)
Use multiply high instructions for high part of 32x32 multiply
mxl-float-convert
Target Mask(FLOAT_CONVERT)
Use hardware floating point converstion instructions
mxl-float-sqrt
Target Mask(FLOAT_SQRT)
Use hardware floating point square root instruction
mxl-mode-executable
Target Mask(XL_MODE_EXECUTABLE)
Description for mxl-mode-executable
mxl-mode-xmdstub
Target Mask(XL_MODE_XMDSTUB)
Description for mxl-mode-xmdstub
mxl-mode-bootstrap
Target Mask(XL_MODE_BOOTSTRAP)
Description for mxl-mode-bootstrap
mxl-mode-novectors
Target Mask(XL_MODE_NOVECTORS)
Description for mxl-mode-novectors

View File

@ -0,0 +1,64 @@
;; Predicate definitions for Xilinx MicroBlaze
;; Copyright 2009, 2010 Free Software Foundation, Inc.
;;
;; Contributed by Michael Eager <eager@eagercon.com>.
;;
;; This file is part of GCC.
;;
;; GCC is free software; you can redistribute it and/or modify
;; it under the terms of the GNU General Public License as published by
;; the Free Software Foundation; either version 3, or (at your option)
;; any later version.
;;
;; GCC is distributed in the hope that it will be useful,
;; but WITHOUT ANY WARRANTY; without even the implied warranty of
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
;; GNU General Public License for more details.
;;
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
;; Return whether OP can be used as an operands in arithmetic.
(define_predicate "arith_operand"
(ior (match_code "const_int,const_double")
(match_operand 0 "register_operand")))
(define_predicate "arith_operand32"
(ior (match_operand 0 "register_operand")
(and (match_code "const_int,const_double")
(match_test "LARGE_INT (op)"))))
(define_predicate "const_0_operand"
(and (match_code "const_int,const_double")
(match_test "op == CONST0_RTX (GET_MODE (op))")))
;; Return whether OP is a register or the constant 0.
(define_predicate "reg_or_0_operand"
(ior (match_operand 0 "const_0_operand")
(match_operand 0 "register_operand")))
;; Return if the operand is either the PC or a label_ref.
(define_special_predicate "pc_or_label_operand"
(ior (match_code "pc,label_ref")
(and (match_code "symbol_ref")
(match_test "!(strcmp ((XSTR (op, 0)), \"_stack_overflow_exit\"))"))))
;; Test for valid call operand
(define_predicate "call_insn_operand"
(match_test "CALL_INSN_OP (op)"))
;; Return if OPERAND is valid as a source operand for a move instruction.
(define_predicate "move_operand"
(and (
not (
and (match_code "plus")
(not (match_test "(GET_CODE (XEXP (op, 0)) == REG) ^ (GET_CODE (XEXP (op,1)) == REG)"))
)
)
(match_operand 0 "general_operand")))
;; Test for valid PIC call operand
(define_predicate "call_insn_plt_operand"
(match_test "PLT_ADDR_P (op)"))

View File

@ -0,0 +1,33 @@
# For C++ crtstuff
EXTRA_MULTILIB_PARTS = crtbegin$(objext) crtend$(objext)
EXTRA_PARTS += crti$(objext) crtn$(objext)
MULTILIB_OPTIONS = mxl-barrel-shift mno-xl-soft-mul mxl-multiply-high
MULTILIB_DIRNAMES = bs m mh
MULTILIB_EXCEPTIONS = *mxl-barrel-shift/mxl-multiply-high mxl-multiply-high
# Extra files
microblaze-c.o: $(srcdir)/config/microblaze/microblaze-c.c \
$(srcdir)/config/microblaze/microblaze-protos.h \
$(CONFIG_H) $(SYSTEM_H) $(CPPLIB_H) $(TM_P_H) $(TREE_H) errors.h $(TM_H)
$(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) \
$(srcdir)/config/microblaze/microblaze-c.c
# Build soft FP routines.
FPBIT = fp-bit.c
DPBIT = dp-bit.c
fp-bit.c: $(srcdir)/config/fp-bit.c
echo '#define FLOAT' > fp-bit.c
cat $(srcdir)/config/fp-bit.c >> fp-bit.c
dp-bit.c: $(srcdir)/config/fp-bit.c
cat $(srcdir)/config/fp-bit.c > dp-bit.c
# Assemble startup files
$(T)crti$(objext): $(srcdir)/config/microblaze/crti.s
$(GCC_FOR_TARGET) -c $(srcdir)/config/microblaze/crti.s -o $(T)crti$(objext)
$(T)crtn$(objext): $(srcdir)/config/microblaze/crtn.s
$(GCC_FOR_TARGET) -c $(srcdir)/config/microblaze/crtn.s -o $(T)crtn$(objext)

2
gcc/configure vendored
View File

@ -24484,7 +24484,7 @@ case "$target" in
i?86*-*-* | mips*-*-* | alpha*-*-* | powerpc*-*-* | sparc*-*-* | m68*-*-* \
| x86_64*-*-* | hppa*-*-* | arm*-*-* \
| xstormy16*-*-* | cris-*-* | crisv32-*-* | xtensa*-*-* | bfin-*-* | score*-*-* \
| spu-*-* | fido*-*-* | m32c-*-*)
| spu-*-* | fido*-*-* | m32c-*-* | microblaze-*-*)
insn="nop"
;;
ia64*-*-* | s390*-*-*)

View File

@ -3745,7 +3745,7 @@ case "$target" in
i?86*-*-* | mips*-*-* | alpha*-*-* | powerpc*-*-* | sparc*-*-* | m68*-*-* \
| x86_64*-*-* | hppa*-*-* | arm*-*-* \
| xstormy16*-*-* | cris-*-* | crisv32-*-* | xtensa*-*-* | bfin-*-* | score*-*-* \
| spu-*-* | fido*-*-* | m32c-*-*)
| spu-*-* | fido*-*-* | m32c-*-* | microblaze-*-*)
insn="nop"
;;
ia64*-*-* | s390*-*-*)

View File

@ -238,6 +238,9 @@ architecture, libio maintenance, and early math work.
@item
Zdenek Dvorak for a new loop unroller and various fixes.
@item
Michael Eager for his work on the Xilinx MicroBlaze port.
@item
Richard Earnshaw for his ongoing work with the ARM@.

View File

@ -2534,8 +2534,8 @@ interrupt handler. The compiler will generate function entry and exit
sequences suitable for use in an interrupt handler when this attribute
is present.
Note, interrupt handlers for the Blackfin, H8/300, H8/300H, H8S, and
SH processors can be specified via the @code{interrupt_handler} attribute.
Note, interrupt handlers for the Blackfin, H8/300, H8/300H, H8S, MicroBlaze,
and SH processors can be specified via the @code{interrupt_handler} attribute.
Note, on the AVR, interrupts will be enabled inside the function.
@ -3134,6 +3134,14 @@ Use this attribute on the Blackfin, H8/300, H8/300H, and H8S to indicate that
all registers except the stack pointer should be saved in the prologue
regardless of whether they are used or not.
@item save_volatiles
@cindex save volatile registers on the MicroBlaze
Use this attribute on the MicroBlaze to indicate that the function is
an interrupt handler. All volatile registers (in addition to non-volatile
registers) will be saved in the function prologue. If the function is a leaf
function, only volatiles used by the function are saved. A normal function
return is generated instead of a return from interrupt.
@item section ("@var{section-name}")
@cindex @code{section} function attribute
Normally, the compiler places the code it generates in the @code{text} section.

View File

@ -2952,6 +2952,8 @@ information are.
@item
@uref{#mep-x-elf,,mep-*-elf}
@item
@uref{#microblaze-x-elf,,microblaze-*-elf}
@item
@uref{#mips-x-x,,mips-*-*}
@item
@uref{#mips-sgi-irix5,,mips-sgi-irix5}
@ -3819,6 +3821,13 @@ original ABI by configuring for @samp{m68k-uclinuxoldabi} or
Toshiba Media embedded Processor.
This configuration is intended for embedded systems.
@html
<hr />
@end html
@heading @anchor{microblaze-x-elf}microblaze-*-elf
Xilinx MicroBlaze processor.
This configuration is intended for embedded systems.
@html
<hr />
@end html

View File

@ -683,6 +683,13 @@ Objective-C and Objective-C++ Dialects}.
-mmult -mno-opts -mrepeat -ms -msatur -msdram -msim -msimnovec -mtf @gol
-mtiny=@var{n}}
@emph{MicroBlaze Options}
@gccoptlist{-msoft-float -mhard-float -msmall-divides -mcpu=@var{cpu} @gol
-mmemcpy -mxl-soft-mul -mxl-soft-div -mxl-barrel-shift @gol
-mxl-pattern-compare -mxl-stack-check -mxl-gp-opt -mno-clearbss @gol
-mxl-multiply-high -mxl-float-convert -mxl-float-sqrt @gol
-mxl-mode-@var{app-model}}
@emph{MIPS Options}
@gccoptlist{-EL -EB -march=@var{arch} -mtune=@var{arch} @gol
-mips1 -mips2 -mips3 -mips4 -mips32 -mips32r2 @gol
@ -9828,6 +9835,7 @@ platform.
* M68hc1x Options::
* MCore Options::
* MeP Options::
* MicroBlaze Options::
* MIPS Options::
* MMIX Options::
* MN10300 Options::
@ -13811,6 +13819,104 @@ register. The default for this option is 4, but note that there's a
@end table
@node MicroBlaze Options
@subsection MicroBlaze Options
@cindex MicroBlaze Options
@table @gcctabopt
@item -msoft-float
@opindex msoft-float
Use software emulation for floating point (default).
@item -mhard-float
@opindex mhard-float
Use hardware floating point instructions.
@item -mmemcpy
@opindex mmemcpy
Do not optimize block moves, use @code{memcpy}.
@item -mno-clearbss
@opindex mno-clearbss
This option is deprecated. Use @option{-fno-zero-initialized-in-bss} instead.
@item -mcpu=@var{cpu-type}
@opindex mcpu=
Use features of and schedule code for given CPU.
Supported values are in the format @samp{v@var{X}.@var{YY}.@var{Z}},
where @var{X} is a major version, @var{YY} is the minor version, and
@var{Z} is compatiblity code. Example values are @samp{v3.00.a},
@samp{v4.00.b}, @samp{v5.00.a}, @samp{v5.00.b}, @samp{v5.00.b}, @samp{v6.00.a}.
@item -mxl-soft-mul
@opindex mxl-soft-mul
Use software multiply emulation (default).
@item -mxl-soft-div
@opindex mxl-soft-div
Use software emulation for divides (default).
@item -mxl-barrel-shift
@opindex mxl-barrel-shift
Use the hardware barrel shifter.
@item -mxl-pattern-compare
@opindex mxl-pattern-compare
Use pattern compare instructions.
@item -msmall-divides
@opindex msmall-divides
Use table lookup optimization for small signed integer divisions.
@item -mxl-stack-check
@opindex mxl-stack-check
This option is deprecated. Use -fstack-check instead.
@item -mxl-gp-opt
@opindex mxl-gp-opt
Use GP relative sdata/sbss sections.
@item -mxl-multiply-high
@opindex mxl-multiply-high
Use multiply high instructions for high part of 32x32 multiply.
@item -mxl-float-convert
@opindex mxl-float-convert
Use hardware floating point converstion instructions.
@item -mxl-float-sqrt
@opindex mxl-float-sqrt
Use hardware floating point square root instruction.
@item -mxl-mode-@var{app-model}
Select application model @var{app-model}. Valid models are
@table @samp
@item executable
normal executable (default), uses startup code @file{crt0.o}.
@item xmdstub
for use with Xilinx Microprocessor Debugger (XMD) based
software intrusive debug agent called xmdstub. This uses startup file
@file{crt1.o} and sets the start address of the program to be 0x800.
@item bootstrap
for applications that are loaded using a bootloader.
This model uses startup file @file{crt2.o} which does not contain a processor
reset vector handler. This is suitable for transferring control on a
processor reset to the bootloader rather than the application.
@item novectors
for applications that do not require any of the
MicroBlaze vectors. This option may be useful for applications running
within a monitoring application. This model uses @file{crt3.o} as a startup file.
@end table
Option @option{-xl-mode-@var{app-model}} is a deprecated alias for
@option{-mxl-mode-@var{app-model}}.
@end table
@node MIPS Options
@subsection MIPS Options
@cindex MIPS options

View File

@ -2677,7 +2677,15 @@ A register indirect address without offset.
@item Z
Symbolic references to the control bus.
@end table
@item MicroBlaze---@file{config/microblaze/constraints.md}
@table @code
@item d
A general register (@code{r0} to @code{r31}).
@item z
A status register (@code{rmsr}, @code{$fcc1} to @code{$fcc7}).
@end table

View File

@ -1,3 +1,41 @@
2010-09-30 Michael Eager <eager@eagercon.com>
* gcc.c-torture/execute/cmpsi-2.c: New testcase.
* gcc.c-torture/execute/cmpsf-1.c: Ditto.
* gcc.target/microblaze/microblaze.exp: Ditto.
* gcc.target/microblaze/others/string_cst1.c: Ditto.
* gcc.target/microblaze/others/string_cst2.c: Ditto.
* gcc.target/microblaze/others/data_var1.c: Ditto.
* gcc.target/microblaze/others/data_var2.c: Ditto.
* gcc.target/microblaze/others/data_var3.c: Ditto.
* gcc.target/microblaze/others/string_cst1_gpopt.c:: Ditto.
* gcc.target/microblaze/others/strings1.c:: Ditto.
* gcc.target/microblaze/others/string_cst2_gpopt.c: Ditto.
* gcc.target/microblaze/others/interrupt_handler_leaf.c: Ditto.
* gcc.target/microblaze/others/sdata_var1.c: Ditto.
* gcc.target/microblaze/others/sdata_var2.c: Ditto.
* gcc.target/microblaze/others/sdata_var3.c: Ditto.
* gcc.target/microblaze/others/sdata_var4.c: Ditto.
* gcc.target/microblaze/others/sdata_var5.c: Ditto.
* gcc.target/microblaze/others/sdata_var6.c: Ditto.
* gcc.target/microblaze/isa/fsqrt.c: Ditto.
* gcc.target/microblaze/isa/pcmp.c: Ditto.
* gcc.target/microblaze/isa/nofloat.c: Ditto.
* gcc.target/microblaze/isa/fcvt.c: Ditto.
* gcc.target/microblaze/isa/float.c: Ditto.
* gcc.target/microblaze/isa/mulh.c: Ditto.
* gcc.target/microblaze/isa/fcmp1.c: Ditto.
* gcc.target/microblaze/isa/mul-bshift-pcmp.c: Ditto.
* gcc.target/microblaze/isa/fcmp2.c: Ditto.
* gcc.target/microblaze/isa/fcmp3.c: Ditto.
* gcc.target/microblaze/isa/mul-bshift.c: Ditto.
* gcc.target/microblaze/isa/mulh-bshift-pcmp.c: Ditto.
* gcc.target/microblaze/isa/bshift.c: Ditto.
* gcc.target/microblaze/isa/nofcmp.c: Ditto.
* gcc.target/microblaze/isa/div.c: Ditto.
* gcc.target/microblaze/isa/vanilla.c: Ditto.
* gcc.target/microblaze/isa/mul.c: Ditto.
2010-09-30 Iain Sandoe <iains@gcc.gnu.org>
merge from FSF 'apple/trunk' branch.
@ -348,6 +386,7 @@
PR fortran/45744
* gfortran.dg/dependency_36.f90: New test.
>>>>>>> .r164755
2010-09-23 Uros Bizjak <ubizjak@gmail.com>
* gcc.target/i386/pad-1.c: Remove -S from dg-options.

View File

@ -0,0 +1,169 @@
#include <limits.h>
#define F 140
#define T 13
feq (float x, float y)
{
if (x == y)
return T;
else
return F;
}
fne (float x, float y)
{
if (x != y)
return T;
else
return F;
}
flt (float x, float y)
{
if (x < y)
return T;
else
return F;
}
fge (float x, float y)
{
if (x >= y)
return T;
else
return F;
}
fgt (float x, float y)
{
if (x > y)
return T;
else
return F;
}
fle (float x, float y)
{
if (x <= y)
return T;
else
return F;
}
float args[] =
{
0.0F,
1.0F,
-1.0F,
FLOAT_MAX,
FLOAT_MIN,
0.0000000000001F,
123456789.0F,
-987654321.0F
};
int correct_results[] =
{
T, F, F, T, F, T, F, T, F, T,
F, T, T, F, F, T, T, F, F, T,
F, T, F, T, T, F, T, F, F, T,
F, T, T, F, F, T, T, F, F, T,
F, T, F, T, T, F, T, F, F, T,
F, T, F, T, T, F, T, F, F, T,
F, T, T, F, F, T, T, F, F, T,
F, T, F, T, T, F, T, F, F, T,
F, T, F, T, T, F, F, T, T, F,
T, F, F, T, F, T, F, T, F, T,
F, T, F, T, T, F, T, F, F, T,
F, T, T, F, F, T, T, F, F, T,
F, T, F, T, T, F, T, F, F, T,
F, T, F, T, T, F, T, F, F, T,
F, T, T, F, F, T, T, F, F, T,
F, T, F, T, T, F, T, F, F, T,
F, T, T, F, F, T, F, T, T, F,
F, T, T, F, F, T, F, T, T, F,
T, F, F, T, F, T, F, T, F, T,
F, T, T, F, F, T, F, T, T, F,
F, T, F, T, T, F, F, T, T, F,
F, T, F, T, T, F, F, T, T, F,
F, T, T, F, F, T, F, T, T, F,
F, T, F, T, T, F, F, T, T, F,
F, T, F, T, T, F, F, T, T, F,
F, T, F, T, T, F, F, T, T, F,
F, T, F, T, T, F, T, F, F, T,
T, F, F, T, F, T, F, T, F, T,
F, T, F, T, T, F, T, F, F, T,
F, T, F, T, T, F, T, F, F, T,
F, T, F, T, T, F, F, T, T, F,
F, T, F, T, T, F, T, F, F, T,
F, T, T, F, F, T, F, T, T, F,
F, T, T, F, F, T, F, T, T, F,
F, T, T, F, F, T, T, F, F, T,
F, T, T, F, F, T, F, T, T, F,
T, F, F, T, F, T, F, T, F, T,
F, T, T, F, F, T, T, F, F, T,
F, T, T, F, F, T, F, T, T, F,
F, T, T, F, F, T, T, F, F, T,
F, T, T, F, F, T, F, T, T, F,
F, T, T, F, F, T, F, T, T, F,
F, T, T, F, F, T, T, F, F, T,
F, T, T, F, F, T, F, T, T, F,
F, T, F, T, T, F, F, T, T, F,
T, F, F, T, F, T, F, T, F, T,
F, T, T, F, F, T, F, T, T, F,
F, T, T, F, F, T, T, F, F, T,
F, T, F, T, T, F, F, T, T, F,
F, T, F, T, T, F, F, T, T, F,
F, T, F, T, T, F, T, F, F, T,
F, T, T, F, F, T, T, F, F, T,
F, T, F, T, T, F, T, F, F, T,
F, T, F, T, T, F, T, F, F, T,
T, F, F, T, F, T, F, T, F, T,
F, T, F, T, T, F, T, F, F, T,
F, T, T, F, F, T, F, T, T, F,
F, T, T, F, F, T, F, T, T, F,
F, T, T, F, F, T, T, F, F, T,
F, T, T, F, F, T, F, T, T, F,
F, T, F, T, T, F, F, T, T, F,
F, T, F, T, T, F, F, T, T, F,
F, T, T, F, F, T, F, T, T, F,
T, F, F, T, F, T, F, T, F, T
};
int
main (void)
{
int i, j, *res = correct_results;
for (i = 0; i < 8; i++)
{
long arg0 = args[i];
for (j = 0; j < 8; j++)
{
long arg1 = args[j];
if (feq (arg0, arg1) != *res++)
abort ();
if (fne (arg0, arg1) != *res++)
abort ();
if (flt (arg0, arg1) != *res++)
abort ();
if (fge (arg0, arg1) != *res++)
abort ();
if (fgt (arg0, arg1) != *res++)
abort ();
if (fle (arg0, arg1) != *res++)
abort ();
if (fltu (arg0, arg1) != *res++)
abort ();
if (fgeu (arg0, arg1) != *res++)
abort ();
if (fgtu (arg0, arg1) != *res++)
abort ();
if (fleu (arg0, arg1) != *res++)
abort ();
}
}
exit (0);
}

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@ -0,0 +1,199 @@
#define F 140
#define T 13
feq (long x, long y)
{
if (x == y)
return T;
else
return F;
}
fne (long x, long y)
{
if (x != y)
return T;
else
return F;
}
flt (long x, long y)
{
if (x < y)
return T;
else
return F;
}
fge (long x, long y)
{
if (x >= y)
return T;
else
return F;
}
fgt (long x, long y)
{
if (x > y)
return T;
else
return F;
}
fle (long x, long y)
{
if (x <= y)
return T;
else
return F;
}
fltu (long x, long y)
{
if (x < y)
return T;
else
return F;
}
fgeu (long x, long y)
{
if (x >= y)
return T;
else
return F;
}
fgtu (long x, long y)
{
if (x > y)
return T;
else
return F;
}
fleu (long x, long y)
{
if (x <= y)
return T;
else
return F;
}
long args[] =
{
0L,
1L,
-1L,
0x7fffffffL,
0x80000000L,
0x80000001L,
0x1A3F2373L,
0x93850E92L
};
int correct_results[] =
{
T, F, F, T, F, T, F, T, F, T,
F, T, T, F, F, T, T, F, F, T,
F, T, F, T, T, F, T, F, F, T,
F, T, T, F, F, T, T, F, F, T,
F, T, F, T, T, F, T, F, F, T,
F, T, F, T, T, F, T, F, F, T,
F, T, T, F, F, T, T, F, F, T,
F, T, F, T, T, F, T, F, F, T,
F, T, F, T, T, F, F, T, T, F,
T, F, F, T, F, T, F, T, F, T,
F, T, F, T, T, F, T, F, F, T,
F, T, T, F, F, T, T, F, F, T,
F, T, F, T, T, F, T, F, F, T,
F, T, F, T, T, F, T, F, F, T,
F, T, T, F, F, T, T, F, F, T,
F, T, F, T, T, F, T, F, F, T,
F, T, T, F, F, T, F, T, T, F,
F, T, T, F, F, T, F, T, T, F,
T, F, F, T, F, T, F, T, F, T,
F, T, T, F, F, T, F, T, T, F,
F, T, F, T, T, F, F, T, T, F,
F, T, F, T, T, F, F, T, T, F,
F, T, T, F, F, T, F, T, T, F,
F, T, F, T, T, F, F, T, T, F,
F, T, F, T, T, F, F, T, T, F,
F, T, F, T, T, F, F, T, T, F,
F, T, F, T, T, F, T, F, F, T,
T, F, F, T, F, T, F, T, F, T,
F, T, F, T, T, F, T, F, F, T,
F, T, F, T, T, F, T, F, F, T,
F, T, F, T, T, F, F, T, T, F,
F, T, F, T, T, F, T, F, F, T,
F, T, T, F, F, T, F, T, T, F,
F, T, T, F, F, T, F, T, T, F,
F, T, T, F, F, T, T, F, F, T,
F, T, T, F, F, T, F, T, T, F,
T, F, F, T, F, T, F, T, F, T,
F, T, T, F, F, T, T, F, F, T,
F, T, T, F, F, T, F, T, T, F,
F, T, T, F, F, T, T, F, F, T,
F, T, T, F, F, T, F, T, T, F,
F, T, T, F, F, T, F, T, T, F,
F, T, T, F, F, T, T, F, F, T,
F, T, T, F, F, T, F, T, T, F,
F, T, F, T, T, F, F, T, T, F,
T, F, F, T, F, T, F, T, F, T,
F, T, T, F, F, T, F, T, T, F,
F, T, T, F, F, T, T, F, F, T,
F, T, F, T, T, F, F, T, T, F,
F, T, F, T, T, F, F, T, T, F,
F, T, F, T, T, F, T, F, F, T,
F, T, T, F, F, T, T, F, F, T,
F, T, F, T, T, F, T, F, F, T,
F, T, F, T, T, F, T, F, F, T,
T, F, F, T, F, T, F, T, F, T,
F, T, F, T, T, F, T, F, F, T,
F, T, T, F, F, T, F, T, T, F,
F, T, T, F, F, T, F, T, T, F,
F, T, T, F, F, T, T, F, F, T,
F, T, T, F, F, T, F, T, T, F,
F, T, F, T, T, F, F, T, T, F,
F, T, F, T, T, F, F, T, T, F,
F, T, T, F, F, T, F, T, T, F,
T, F, F, T, F, T, F, T, F, T
};
int
main (void)
{
int i, j, *res = correct_results;
for (i = 0; i < 8; i++)
{
long arg0 = args[i];
for (j = 0; j < 8; j++)
{
long arg1 = args[j];
if (feq (arg0, arg1) != *res++)
abort ();
if (fne (arg0, arg1) != *res++)
abort ();
if (flt (arg0, arg1) != *res++)
abort ();
if (fge (arg0, arg1) != *res++)
abort ();
if (fgt (arg0, arg1) != *res++)
abort ();
if (fle (arg0, arg1) != *res++)
abort ();
if (fltu (arg0, arg1) != *res++)
abort ();
if (fgeu (arg0, arg1) != *res++)
abort ();
if (fgtu (arg0, arg1) != *res++)
abort ();
if (fleu (arg0, arg1) != *res++)
abort ();
}
}
exit (0);
}

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/* { dg-options "-O3 -mcpu=v6.00.a -mxl-barrel-shift" } */
volatile int m1, m2, m3;
volatile unsigned int u1, u2, u3;
volatile long l1, l2;
volatile long long llp;
volatile unsigned long ul1, ul2;
volatile unsigned long long ullp;
int test_mul () {
/* { dg-final { scan-assembler-not "mul\tr" } } */
m1 = m2 * m3 ;
/* { dg-final { scan-assembler-not "muli" } } */
m3 = m1 * 1234 ;
/* { dg-final { scan-assembler-not "mulh" } } */
llp = ((long long)l1 * l2);
/* { dg-final { scan-assembler-not "mulhu" } } */
ullp = ((unsigned long long)ul1 * ul2);
/* { dg-final { scan-assembler-not "mulhsu" } } */
llp = ((long long)l1 * ul2);
/* { dg-final { scan-assembler "bslli\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),25" } } */
m3 = m2 << 25;
/* { dg-final { scan-assembler "bsll\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
m2 = m1 << m3;
/* { dg-final { scan-assembler "bsrai\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),25" } } */
m3 = m2 >> 25;
/* { dg-final { scan-assembler "bsra\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
m2 = m1 >> m3;
/* { dg-final { scan-assembler-not "idiv" } } */
m1 = m2 / m1;
/* { dg-final { scan-assembler-not "idivu" } } */
u1 = u2 / u3;
/* { dg-final { scan-assembler-not "pcmpne" } } */
m3 = (m3 != m1);
/* { dg-final { scan-assembler-not "pcmpeq" } } */
return (m1 == m2);
}

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/* { dg-options "-O3 -mcpu=v6.00.a -mno-xl-soft-div" } */
volatile int m1, m2, m3;
volatile long l1, l2;
volatile long long llp;
volatile unsigned int u1, u2, u3;
volatile unsigned long ul1, ul2;
volatile unsigned long long ullp;
int test_mul () {
/* { dg-final { scan-assembler-not "mul\tr" } } */
m1 = m2 * m3 ;
/* { dg-final { scan-assembler-not "muli" } } */
m3 = m1 * 1234 ;
/* { dg-final { scan-assembler-not "mulh" } } */
llp = ((long long)l1 * l2);
/* { dg-final { scan-assembler-not "mulhu" } } */
ullp = ((unsigned long long)ul1 * ul2);
/* { dg-final { scan-assembler-not "mulhsu" } } */
llp = ((long long)l1 * ul2);
/* { dg-final { scan-assembler-not "bslli" } } */
m3 = m2 << 25;
/* { dg-final { scan-assembler-not "bsll" } } */
m2 = m1 << m3;
/* { dg-final { scan-assembler-not "bsrai" } } */
m3 = m2 >> 25;
/* { dg-final { scan-assembler-not "bsra" } } */
m2 = m1 >> m3;
/* { dg-final { scan-assembler "idiv" } } */
m1 = m2 / m1;
/* { dg-final { scan-assembler "idivu" } } */
u1 = u2 / u3;
/* { dg-final { scan-assembler-not "pcmpne" } } */
m3 = (m3 != m1);
/* { dg-final { scan-assembler-not "pcmpeq" } } */
return (m1 == m2);
}

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/* { dg-options "-O3 -mcpu=v6.00.a -mhard-float" } */
volatile float f1, f2, f3;
void float_func ()
{
/* { dg-final { scan-assembler "fcmp\.(le|gt)\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
if (f2 <= f3)
print ("le");
}

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@ -0,0 +1,10 @@
/* { dg-options "-O3 -mcpu=v6.00.a -mhard-float" } */
volatile float f1, f2, f3;
void float_func ()
{
/* { dg-final { scan-assembler "fcmp\.(lt|ge)\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
if (f2 < f3)
print ("lt");
}

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@ -0,0 +1,10 @@
/* { dg-options "-O3 -mcpu=v6.00.a -mhard-float" } */
volatile float f1, f2, f3;
void float_func ()
{
/* { dg-final { scan-assembler "fcmp\.(eq|ne)\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
if (f2 == f3)
print ("eq");
}

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/* { dg-options "-O3 -mcpu=v6.00.a -mhard-float -mxl-float-convert" } */
int float_func (float f)
{
/* { dg-final { scan-assembler "flt\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
return f;
}
float int_func (int i)
{
/* { dg-final { scan-assembler "fint\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
return i;
}
float uint_func (unsigned int i)
{
/* { dg-final { scan-assembler "fint\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
return i;
}

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/* { dg-options "-O3 -mcpu=v6.00.a -mhard-float" } */
volatile float f1, f2, f3;
void float_func ()
{
/* { dg-final { scan-assembler "fmul\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
f1 = f2 * f3;
/* { dg-final { scan-assembler "fadd\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
f1 = f2 + f3;
/* { dg-final { scan-assembler "frsub\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
f1 = f2 - f3;
/* { dg-final { scan-assembler "fdiv\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
f1 = f2 / f3;
}

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/* { dg-options "-O3 -mcpu=v6.00.a -mhard-float -mxl-float-sqrt" } */
#include <math.h>
float sqrt_func (float f)
{
/* { dg-final { scan-assembler "fsqrt\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
return sqrtf (f);
}

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/* { dg-options "-O3 -mcpu=v6.00.a -mxl-barrel-shift -mno-xl-soft-mul -mxl-pattern-compare" } */
volatile int m1, m2, m3;
volatile unsigned int u1, u2, u3;
volatile long l1, l2;
volatile long long llp;
volatile unsigned long ul1, ul2;
volatile unsigned long long ullp;
int test_mul () {
/* { dg-final { scan-assembler "mul\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
m1 = m2 * m3 ;
/* { dg-final { scan-assembler "muli\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),(0x\[0-9a-fA-F]+|\[+-]*\[0-9]+)" } } */
m3 = m1 * 1234 ;
/* { dg-final { scan-assembler-not "mulh" } } */
llp = ((long long)l1 * l2);
/* { dg-final { scan-assembler-not "mulhu" } } */
ullp = ((unsigned long long)ul1 * ul2);
/* { dg-final { scan-assembler-not "mulhsu" } } */
llp = ((long long)l1 * ul2);
/* { dg-final { scan-assembler "bslli\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),25" } } */
m3 = m2 << 25;
/* { dg-final { scan-assembler "bsll\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
m2 = m1 << m3;
/* { dg-final { scan-assembler "bsrai\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),25" } } */
m3 = m2 >> 25;
/* { dg-final { scan-assembler "bsra\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
m2 = m1 >> m3;
/* { dg-final { scan-assembler-not "idiv" } } */
m1 = m2 / m1;
/* { dg-final { scan-assembler-not "idivu" } } */
u1 = u2 / u3;
/* { dg-final { scan-assembler "pcmpne\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
m3 = (m3 != m1);
/* { dg-final { scan-assembler "pcmpeq\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
return (m1 == m2);
}

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/* { dg-options "-O3 -mcpu=v6.00.a -mxl-barrel-shift -mno-xl-soft-mul" } */
volatile int m1, m2, m3;
volatile unsigned int u1, u2, u3;
volatile long l1, l2;
volatile long long llp;
volatile unsigned long ul1, ul2;
volatile unsigned long long ullp;
int test_mul () {
/* { dg-final { scan-assembler "mul\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
m1 = m2 * m3 ;
/* { dg-final { scan-assembler "muli\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),(0x\[0-9a-fA-F]+|\[+-]*\[0-9]+)" } } */
m3 = m1 * 1234 ;
/* { dg-final { scan-assembler-not "mulh" } } */
llp = ((long long)l1 * l2);
/* { dg-final { scan-assembler-not "mulhu" } } */
ullp = ((unsigned long long)ul1 * ul2);
/* { dg-final { scan-assembler-not "mulhsu" } } */
llp = ((long long)l1 * ul2);
/* { dg-final { scan-assembler "bslli\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),25" } } */
m3 = m2 << 25;
/* { dg-final { scan-assembler "bsll\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
m2 = m1 << m3;
/* { dg-final { scan-assembler "bsrai\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),25" } } */
m3 = m2 >> 25;
/* { dg-final { scan-assembler "bsra\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
m2 = m1 >> m3;
/* { dg-final { scan-assembler-not "idiv" } } */
m1 = m2 / m1;
/* { dg-final { scan-assembler-not "idivu" } } */
u1 = u2 / u3;
/* { dg-final { scan-assembler-not "pcmpne" } } */
m3 = (m3 != m1);
/* { dg-final { scan-assembler-not "pcmpeq" } } */
return (m1 == m2);
}

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/* { dg-options "-O3 -mcpu=v6.00.a -mno-xl-soft-mul" } */
volatile int m1, m2, m3;
volatile long l1, l2;
volatile long long llp;
volatile unsigned int u1, u2, u3;
volatile unsigned long ul1, ul2;
volatile unsigned long long ullp;
int test_mul () {
/* { dg-final { scan-assembler "mul\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
m1 = m2 * m3 ;
/* { dg-final { scan-assembler "muli\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),(0x\[0-9a-fA-F]+|\[+-]*\[0-9]+)" } } */
m3 = m1 * 1234 ;
/* { dg-final { scan-assembler-not "mulh" } } */
llp = ((long long)l1 * l2);
/* { dg-final { scan-assembler-not "mulhu" } } */
ullp = ((unsigned long long)ul1 * ul2);
/* { dg-final { scan-assembler-not "mulhsu" } } */
llp = ((long long)l1 * ul2);
/* { dg-final { scan-assembler-not "bslli" } } */
m3 = m2 << 25;
/* { dg-final { scan-assembler-not "bsll" } } */
m2 = m1 << m3;
/* { dg-final { scan-assembler-not "bsrai" } } */
m3 = m2 >> 25;
/* { dg-final { scan-assembler-not "bsra" } } */
m2 = m1 >> m3;
/* { dg-final { scan-assembler-not "idiv" } } */
m1 = m2 / m1;
/* { dg-final { scan-assembler-not "idivu" } } */
u1 = u2 / u3;
/* { dg-final { scan-assembler-not "pcmpne" } } */
m3 = (m3 != m1);
/* { dg-final { scan-assembler-not "pcmpeq" } } */
return (m1 == m2);
}

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@ -0,0 +1,53 @@
/* { dg-options "-O3 -mcpu=v6.00.a -mxl-barrel-shift -mno-xl-soft-mul -mxl-pattern-compare -mxl-multiply-high" } */
volatile int m1, m2, m3;
volatile unsigned int u1, u2, u3;
volatile long l1, l2;
volatile long long llp;
volatile unsigned long ul1, ul2;
volatile unsigned long long ullp;
int test_mul () {
/* { dg-final { scan-assembler "mul\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
m1 = m2 * m3 ;
/* { dg-final { scan-assembler "muli\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),(0x\[0-9a-fA-F]+|\[+-]*\[0-9]+)" } } */
m3 = m1 * 1234 ;
/* { dg-final { scan-assembler "mulh\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
llp = (long long)l1 * l2;
/* { dg-final { scan-assembler "mulhu\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
ullp = (unsigned long long)ul1 * ul2;
/* { dg-final { scan-assembler "mulhsu\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
llp = (long long)l1 * ul2;
/* { dg-final { scan-assembler "bslli\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),25" } } */
m3 = m2 << 25;
/* { dg-final { scan-assembler "bsll\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
m2 = m1 << m3;
/* { dg-final { scan-assembler "bsrai\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),25" } } */
m3 = m2 >> 25;
/* { dg-final { scan-assembler "bsra\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
m2 = m1 >> m3;
/* { dg-final { scan-assembler-not "idiv" } } */
m1 = m2 / m1;
/* { dg-final { scan-assembler-not "idivu" } } */
u1 = u2 / u3;
/* { dg-final { scan-assembler "pcmpne\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
m3 = (m3 != m1);
/* { dg-final { scan-assembler "pcmpeq\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
return (m1 == m2);
}

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@ -0,0 +1,53 @@
/* { dg-options "-O3 -mcpu=v6.00.a -mno-xl-soft-mul -mxl-multiply-high" } */
volatile int m1, m2, m3;
volatile unsigned int u1, u2, u3;
volatile long l1, l2;
volatile long long llp;
volatile unsigned long ul1, ul2;
volatile unsigned long long ullp;
int test_mul () {
/* { dg-final { scan-assembler "mul\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
m1 = m2 * m3 ;
/* { dg-final { scan-assembler "muli\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),(0x\[0-9a-fA-F]+|\[+-]*\[0-9]+)" } } */
m3 = m1 * 1234 ;
/* { dg-final { scan-assembler "mulh\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
llp = ((long long)l1 * l2);
/* { dg-final { scan-assembler "mulhu\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
ullp = ((unsigned long long)ul1 * ul2);
/* { dg-final { scan-assembler "mulhsu\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
llp = ((long long)l1 * ul2);
/* { dg-final { scan-assembler-not "bslli" } } */
m3 = m2 << 25;
/* { dg-final { scan-assembler-not "bsll" } } */
m2 = m1 << m3;
/* { dg-final { scan-assembler-not "bsrai" } } */
m3 = m2 >> 25;
/* { dg-final { scan-assembler-not "bsra" } } */
m2 = m1 >> m3;
/* { dg-final { scan-assembler-not "idiv" } } */
m1 = m2 / m1;
/* { dg-final { scan-assembler-not "idivu" } } */
u1 = u2 / u3;
/* { dg-final { scan-assembler-not "pcmpne" } } */
m3 = (m3 != m1);
/* { dg-final { scan-assembler-not "pcmpeq" } } */
return (m1 == m2);
}

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@ -0,0 +1,21 @@
/* { dg-options "-O3 -mcpu=v6.00.a " } */
volatile float f1, f2, f3;
void float_func ()
{
/* { dg-final { scan-assembler-not "fcmp" } } */
if (f2 <= f3)
print ("le");
else if (f2 == f3)
print ("eq");
else if (f2 < f3)
print ("lt");
else if (f2 > f3)
print ("gt");
else if (f2 >= f3)
print ("ge");
else if (f2 != f3)
print ("ne");
}

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@ -0,0 +1,19 @@
/* { dg-options "-O3 -mcpu=v6.00.a -msoft-float" } */
volatile float f1, f2, f3;
void float_func ()
{
/* { dg-final { scan-assembler-not "fmul" } } */
f1 = f2 * f3;
/* { dg-final { scan-assembler-not "fadd" } } */
f1 = f2 + f3;
/* { dg-final { scan-assembler-not "frsub" } } */
f1 = f2 - f3;
/* { dg-final { scan-assembler-not "fdiv" } } */
f1 = f2 / f3;
}

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@ -0,0 +1,52 @@
/* { dg-options "-O3 -mcpu=v6.00.a -mxl-pattern-compare" } */
volatile int m1, m2, m3;
volatile long l1, l2;
volatile long long llp;
volatile unsigned int u1, u2, u3;
volatile unsigned long ul1, ul2;
volatile unsigned long long ullp;
int test_mul () {
/* { dg-final { scan-assembler-not "mul\tr" } } */
m1 = m2 * m3 ;
/* { dg-final { scan-assembler-not "muli" } } */
m3 = m1 * 1234 ;
/* { dg-final { scan-assembler-not "mulh" } } */
llp = ((long long)l1 * l2);
/* { dg-final { scan-assembler-not "mulhu" } } */
ullp = ((unsigned long long)ul1 * ul2);
/* { dg-final { scan-assembler-not "mulhsu" } } */
llp = ((long long)l1 * ul2);
/* { dg-final { scan-assembler-not "bslli" } } */
m3 = m2 << 25;
/* { dg-final { scan-assembler-not "bsll" } } */
m2 = m1 << m3;
/* { dg-final { scan-assembler-not "bsrai" } } */
m3 = m2 >> 25;
/* { dg-final { scan-assembler-not "bsra" } } */
m2 = m1 >> m3;
/* { dg-final { scan-assembler-not "idiv" } } */
m1 = m2 / m1;
/* { dg-final { scan-assembler-not "idivu" } } */
u1 = u2 / u3;
/* { dg-final { scan-assembler "pcmpne" } } */
m3 = (m3 != m1);
/* { dg-final { scan-assembler "pcmpeq" } } */
return (m1 == m2);
}

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@ -0,0 +1,89 @@
/* { dg-options "-O3 -mcpu=v6.00.a -mcpu=v6.00.a" } */
volatile int m1, m2, m3;
volatile long l1, l2;
volatile long long llp;
volatile unsigned int u1, u2, u3;
volatile unsigned long ul1, ul2;
volatile unsigned long long ullp;
int test_mul () {
/* { dg-final { scan-assembler-not "mul\tr" } } */
m1 = m2 * m3 ;
/* { dg-final { scan-assembler-not "muli" } } */
m3 = m1 * 1234 ;
/* { dg-final { scan-assembler-not "mulh" } } */
llp = ((long long)l1 * l2);
/* { dg-final { scan-assembler-not "mulhu" } } */
ullp = ((unsigned long long)ul1 * ul2);
/* { dg-final { scan-assembler-not "mulhsu" } } */
llp = ((long long)l1 * ul2);
/* { dg-final { scan-assembler-not "bslli" } } */
m3 = m2 << 25;
/* { dg-final { scan-assembler-not "bsll" } } */
m2 = m1 << m3;
/* { dg-final { scan-assembler-not "bsrai" } } */
m3 = m2 >> 25;
/* { dg-final { scan-assembler-not "bsra" } } */
m2 = m1 >> m3;
/* { dg-final { scan-assembler-not "idiv" } } */
m1 = m2 / m1;
/* { dg-final { scan-assembler-not "idivu" } } */
u1 = u2 / u3;
/* { dg-final { scan-assembler-not "pcmpne" } } */
m3 = (m3 != m1);
/* { dg-final { scan-assembler-not "pcmpeq" } } */
return (m1 == m2);
}
volatile float f1, f2, f3;
void float_func ()
{
/* { dg-final { scan-assembler-not "fmul" } } */
f1 = f2 * f3;
/* { dg-final { scan-assembler-not "fadd" } } */
f1 = f2 + f3;
/* { dg-final { scan-assembler-not "frsub" } } */
f1 = f2 - f3;
/* { dg-final { scan-assembler-not "fdiv" } } */
f1 = f2 / f3;
}
void float_cmp_func ()
{
/* { dg-final { scan-assembler-not "fcmp" } } */
if (f2 <= f3)
print ("le");
else if (f2 == f3)
print ("eq");
else if (f2 < f3)
print ("lt");
else if (f2 > f3)
print ("gt");
else if (f2 >= f3)
print ("ge");
else if (f2 != f3)
print ("ne");
}

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@ -0,0 +1,62 @@
# Copyright 2009, 2010 Free Software Foundation, Inc.
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with GCC; see the file COPYING3. If not see
# <http://www.gnu.org/licenses/>.
# MicroBlaze test driver that uses the `dg.exp' driver.
# Exit immediately if this isn't a MicroBlaze target.
if { ![istarget microblaze*-*-*] } then {
return
}
# Don't execute when we are testing some configuration of GCC or G++.
# This we figure out by looking at target_config_cflags which needs to be "" for microblaze.exp
if { $target_config_cflags != "" } {
return
}
global TORTURE_OPTIONS
set TORTURE_OPTIONS [list \
{ -O0 } \
{ -O1 } \
{ -O2 } \
{ -O3 } \
{ -Os } ]
# If a testcase doesn't have special options, use these.
global DEFAULT_CFLAGS
if ![info exists DEFAULT_CFLAGS] then {
set DEFAULT_CFLAGS " -ansi -pedantic-errors"
}
# Load support procs.
load_lib gcc-dg.exp
# Initialize `dg'.
dg-init
set default_c_flags ""
# Main loop.
dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/isa/*.\[cSi\]]] \
${default_c_flags} ""
gcc-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/others/*.\[cSi\]]] \
"-mcpu=v6.00.a"
# All done.
dg-finish

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@ -0,0 +1,8 @@
/* { dg-final { scan-assembler "\.bss*" } } */
int global;
int testfunc ()
{
/* { dg-final { scan-assembler "\lwi\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r0" } } */
return global;
}

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@ -0,0 +1,8 @@
/* { dg-final { scan-assembler "\.data*" } } */
int global = 10;
int testfunc ()
{
/* { dg-final { scan-assembler "\lwi\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r0" } } */
return global;
}

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@ -0,0 +1,7 @@
/* { dg-final { scan-assembler "\.rodata*" } } */
const int global = 10;
int testfunc ()
{
return global;
}

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@ -0,0 +1,10 @@
int leaf_func () __attribute__ ((interrupt_handler));
volatile int intr_occurred;
int leaf_func ()
{
/* { dg-final { scan-assembler "rtid\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),0" } } */
/* { dg-final { scan-assembler-not "rtsd" } } */
intr_occurred += 1;
}

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@ -0,0 +1,15 @@
/* { dg-options "-mxl-gp-opt" } */
/* { dg-final { scan-assembler "\.sbss\[^2]+" } } */
typedef int Boolean;
volatile Boolean global = 0;
int testfunc ()
{
/* { dg-final { scan-assembler "\lwi\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r13" } } */
return global;
}
int main ()
{
}

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@ -0,0 +1,10 @@
/* { dg-options "-mxl-gp-opt" } */
/* { dg-final { scan-assembler "\.sdata\[^2]+" } } */
int global = 10;
int testfunc ()
{
/* { dg-final { scan-assembler "\lwi\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r13" } } */
return global;
}

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@ -0,0 +1,13 @@
/* { dg-options "-mxl-gp-opt" } */
extern int a;
/* { dg-final { scan-assembler "\.sdata2" } } */
const int global1 = 10;
extern const int global2;
int testfunc ()
{
/* { dg-final { scan-assembler "\lwi\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r2" } } */
return global2 + global1;
}

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@ -0,0 +1,15 @@
/* { dg-options "-mxl-gp-opt -G 16" } */
/* { dg-final { scan-assembler "\.sbss\[^2]+" } } */
struct test_s {
int a;
int b;
int c;
int d;
} global;
int testfunc ()
{
/* { dg-final { scan-assembler "\lwi\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r13" } } */
return global.a;
}

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@ -0,0 +1,15 @@
/* { dg-options "-mxl-gp-opt -G 16" } */
/* { dg-final { scan-assembler "\.sdata\[^2]+" } } */
struct test_s {
int a;
int b;
int c;
int d;
} global = { 1, 2, 3, 4 };
int testfunc ()
{
/* { dg-final { scan-assembler "\lwi\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r13" } } */
return global.a;
}

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@ -0,0 +1,18 @@
/* { dg-options "-mxl-gp-opt -G 16" } */
struct test_s {
int a;
int b;
int c;
int d;
};
/* { dg-final { scan-assembler "\.sdata2" } } */
const struct test_s global1 = { 1, 2, 3, 4};
extern const struct test_s global2;
int testfunc ()
{
/* { dg-final { scan-assembler "\lwi\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r2" } } */
return global2.a + global1.a;
}

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@ -0,0 +1,12 @@
#include <string.h>
/* { dg-final { scan-assembler "\.rodata*" } } */
/* { dg-final { scan-assembler "\.data*" } } */
char *string1 = "string1";
int testfunc (char *cptr)
{
/* { dg-final { scan-assembler-not "\lwi\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r13" } } */
strcpy (string1, cptr);
}

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@ -0,0 +1,13 @@
/* { dg-options "-mxl-gp-opt" } */
#include <string.h>
/* { dg-final { scan-assembler "\.rodata*" } } */
/* { dg-final { scan-assembler "\.sdata\[^2]+" } } */
char *string1 = "string1";
int testfunc (char *cptr)
{
/* { dg-final { scan-assembler "\lwi\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r13" } } */
strcpy (string1, cptr);
}

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@ -0,0 +1,13 @@
#include <string.h>
/* { dg-final { scan-assembler "\.rodata*" } } */
/* { dg-final { scan-assembler "\.data*" } } */
const char *string1 = "string1";
char* testfunc (char *cptr)
{
/* { dg-final { scan-assembler-not "\lwi\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r13" } } */
strcpy (cptr, string1);
return cptr;
}

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@ -0,0 +1,15 @@
/* { dg-options "-mxl-gp-opt" } */
#include <string.h>
/* { dg-final { scan-assembler "\.rodata*" } } */
/* { dg-final { scan-assembler "\.sdata\[^2]+" } } */
const char *string1 = "string1";
char* testfunc (char *cptr)
{
/* { dg-final { scan-assembler "\lwi\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r13" } } */
strcpy (cptr, string1);
return cptr;
}

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@ -0,0 +1,13 @@
/* { dg-options "-O3" } */
#include <string.h>
/* { dg-final { scan-assembler "\.rodata*" } } */
extern void somefunc (char *);
int testfunc ()
{
char string2[80];
/* { dg-final { scan-assembler "\lwi\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r0,.LC*" } } */
strcpy (string2, "hello");
somefunc (string2);
}

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@ -1,3 +1,10 @@
2010-09-30 Michael Eager <eager@eagercon.com>
* config.host: Add microblaze*-*-*.
* config/microblaze/{divsi3.asm,divsi3_table.c,moddi3.asm,modsi3.asm,
muldi3_hard.asm,mulsi3.asm,stack_overflow_exit.asm,t-microblaze,
udivsi3.asm,umodsi3.asm}: New.
2010-09-28 Ian Lance Taylor <iant@google.com>
* configure.ac: Adjust CFI test to test assembler directly rather
@ -22,6 +29,7 @@
* config.host (i[34567]86-*-linux* and friends): Add t-stack and
i386/t-stack-i386 to tmake_file.
>>>>>>> .r164755
2010-09-21 Iain Sandoe <iains@gcc.gnu.org>
* Makefile.in (libgcc-extra-parts): Check for static archives and

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@ -107,6 +107,9 @@ m68k-*-*)
;;
mep*-*-*)
;;
microblaze*-*-*)
cpu_type=microblaze
;;
mips*-*-*)
cpu_type=mips
;;
@ -399,6 +402,9 @@ mcore-*-elf)
;;
mcore-*-pe*)
;;
microblaze*-*-*)
tmake_file="microblaze/t-microblaze"
;;
mips-sgi-irix[56]*)
;;
mips*-*-netbsd*) # NetBSD/mips, either endian.

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@ -0,0 +1,96 @@
###################################-
#
# Copyright 2009, 2010 Free Software Foundation, Inc.
#
# Contributed by Michael Eager <eager@eagercon.com>.
#
# This file is free software; you can redistribute it and/or modify it
# under the terms of the GNU General Public License as published by the
# Free Software Foundation; either version 3, or (at your option) any
# later version.
#
# GCC is distributed in the hope that it will be useful, but WITHOUT
# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
# License for more details.
#
# Under Section 7 of GPL version 3, you are granted additional
# permissions described in the GCC Runtime Library Exception, version
# 3.1, as published by the Free Software Foundation.
#
# You should have received a copy of the GNU General Public License and
# a copy of the GCC Runtime Library Exception along with this program;
# see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
# <http://www.gnu.org/licenses/>.
#
# divsi3.asm
#
# Divide operation for 32 bit integers.
# Input : Dividend in Reg r5
# Divisor in Reg r6
# Output: Result in Reg r3
#
#######################################
.globl __divsi3
.ent __divsi3
.type __divsi3,@function
__divsi3:
.frame r1,0,r15
ADDIK r1,r1,-16
SWI r28,r1,0
SWI r29,r1,4
SWI r30,r1,8
SWI r31,r1,12
BEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error
BEQI r5,$LaResult_Is_Zero # Result is Zero
BGEID r5,$LaR5_Pos
XOR r28,r5,r6 # Get the sign of the result
RSUBI r5,r5,0 # Make r5 positive
$LaR5_Pos:
BGEI r6,$LaR6_Pos
RSUBI r6,r6,0 # Make r6 positive
$LaR6_Pos:
ADDIK r30,r0,0 # Clear mod
ADDIK r3,r0,0 # clear div
ADDIK r29,r0,32 # Initialize the loop count
# First part try to find the first '1' in the r5
$LaDIV0:
BLTI r5,$LaDIV2 # This traps r5 == 0x80000000
$LaDIV1:
ADD r5,r5,r5 # left shift logical r5
BGTID r5,$LaDIV1
ADDIK r29,r29,-1
$LaDIV2:
ADD r5,r5,r5 # left shift logical r5 get the '1' into the Carry
ADDC r30,r30,r30 # Move that bit into the Mod register
RSUB r31,r6,r30 # Try to subtract (r30 a r6)
BLTI r31,$LaMOD_TOO_SMALL
OR r30,r0,r31 # Move the r31 to mod since the result was positive
ADDIK r3,r3,1
$LaMOD_TOO_SMALL:
ADDIK r29,r29,-1
BEQi r29,$LaLOOP_END
ADD r3,r3,r3 # Shift in the '1' into div
BRI $LaDIV2 # Div2
$LaLOOP_END:
BGEI r28,$LaRETURN_HERE
BRID $LaRETURN_HERE
RSUBI r3,r3,0 # Negate the result
$LaDiv_By_Zero:
$LaResult_Is_Zero:
OR r3,r0,r0 # set result to 0
$LaRETURN_HERE:
# Restore values of CSRs and that of r3 and the divisor and the dividend
LWI r28,r1,0
LWI r29,r1,4
LWI r30,r1,8
LWI r31,r1,12
RTSD r15,8
ADDIK r1,r1,16
.end __divsi3
.size __divsi3, . - __divsi3

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@ -0,0 +1,62 @@
/* Table for software lookup divide for Xilinx MicroBlaze.
Copyright 2009, 2010 Free Software Foundation, Inc.
Contributed by Michael Eager <eager@eagercon.com>.
This file is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by the
Free Software Foundation; either version 3, or (at your option) any
later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
unsigned char _divsi3_table[] =
{
0, 0/1, 0/2, 0/3, 0/4, 0/5, 0/6, 0/7,
0/8, 0/9, 0/10, 0/11, 0/12, 0/13, 0/14, 0/15,
0, 1/1, 1/2, 1/3, 1/4, 1/5, 1/6, 1/7,
1/8, 1/9, 1/10, 1/11, 1/12, 1/13, 1/14, 1/15,
0, 2/1, 2/2, 2/3, 2/4, 2/5, 2/6, 2/7,
2/8, 2/9, 2/10, 2/11, 2/12, 2/13, 2/14, 2/15,
0, 3/1, 3/2, 3/3, 3/4, 3/5, 3/6, 3/7,
3/8, 3/9, 3/10, 3/11, 3/12, 3/13, 3/14, 3/15,
0, 4/1, 4/2, 4/3, 4/4, 4/5, 4/6, 4/7,
4/8, 4/9, 4/10, 4/11, 4/12, 4/13, 4/14, 4/15,
0, 5/1, 5/2, 5/3, 5/4, 5/5, 5/6, 5/7,
5/8, 5/9, 5/10, 5/11, 5/12, 5/13, 5/14, 5/15,
0, 6/1, 6/2, 6/3, 6/4, 6/5, 6/6, 6/7,
6/8, 6/9, 6/10, 6/11, 6/12, 6/13, 6/14, 6/15,
0, 7/1, 7/2, 7/3, 7/4, 7/5, 7/6, 7/7,
7/8, 7/9, 7/10, 7/11, 7/12, 7/13, 7/14, 7/15,
0, 8/1, 8/2, 8/3, 8/4, 8/5, 8/6, 8/7,
8/8, 8/9, 8/10, 8/11, 8/12, 8/13, 8/14, 8/15,
0, 9/1, 9/2, 9/3, 9/4, 9/5, 9/6, 9/7,
9/8, 9/9, 9/10, 9/11, 9/12, 9/13, 9/14, 9/15,
0, 10/1, 10/2, 10/3, 10/4, 10/5, 10/6, 10/7,
10/8, 10/9, 10/10, 10/11, 10/12, 10/13, 10/14, 10/15,
0, 11/1, 11/2, 11/3, 11/4, 11/5, 11/6, 11/7,
11/8, 11/9, 11/10, 11/11, 11/12, 11/13, 11/14, 11/15,
0, 12/1, 12/2, 12/3, 12/4, 12/5, 12/6, 12/7,
12/8, 12/9, 12/10, 12/11, 12/12, 12/13, 12/14, 12/15,
0, 13/1, 13/2, 13/3, 13/4, 13/5, 13/6, 13/7,
13/8, 13/9, 13/10, 13/11, 13/12, 13/13, 13/14, 13/15,
0, 14/1, 14/2, 14/3, 14/4, 14/5, 14/6, 14/7,
14/8, 14/9, 14/10, 14/11, 14/12, 14/13, 14/14, 14/15,
0, 15/1, 15/2, 15/3, 15/4, 15/5, 15/6, 15/7,
15/8, 15/9, 15/10, 15/11, 15/12, 15/13, 15/14, 15/15,
};

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@ -0,0 +1,115 @@
###################################
#
# Copyright 2009, 2010 Free Software Foundation, Inc.
#
# Contributed by Michael Eager <eager@eagercon.com>.
#
# This file is free software; you can redistribute it and/or modify it
# under the terms of the GNU General Public License as published by the
# Free Software Foundation; either version 3, or (at your option) any
# later version.
#
# GCC is distributed in the hope that it will be useful, but WITHOUT
# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
# License for more details.
#
# Under Section 7 of GPL version 3, you are granted additional
# permissions described in the GCC Runtime Library Exception, version
# 3.1, as published by the Free Software Foundation.
#
# You should have received a copy of the GNU General Public License and
# a copy of the GCC Runtime Library Exception along with this program;
# see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
# <http://www.gnu.org/licenses/>.
#
# modsi3.asm
#
# modulo operation for 64 bit integers.
#
#######################################
.globl __moddi3
.ent __moddi3
__moddi3:
.frame r1,0,r15
#Change the stack pointer value and Save callee saved regs
addik r1,r1,-24
swi r25,r1,0
swi r26,r1,4
swi r27,r1,8 # used for sign
swi r28,r1,12 # used for loop count
swi r29,r1,16 # Used for div value High
swi r30,r1,20 # Used for div value Low
#Check for Zero Value in the divisor/dividend
OR r9,r5,r6 # Check for the op1 being zero
BEQID r9,$LaResult_Is_Zero # Result is zero
OR r9,r7,r8 # Check for the dividend being zero
BEQI r9,$LaDiv_By_Zero # Div_by_Zero # Division Error
BGEId r5,$La1_Pos
XOR r27,r5,r7 # Get the sign of the result
RSUBI r6,r6,0 # Make dividend positive
RSUBIC r5,r5,0 # Make dividend positive
$La1_Pos:
BGEI r7,$La2_Pos
RSUBI r8,r8,0 # Make Divisor Positive
RSUBIC r9,r9,0 # Make Divisor Positive
$La2_Pos:
ADDIK r4,r0,0 # Clear mod low
ADDIK r3,r0,0 # Clear mod high
ADDIK r29,r0,0 # clear div high
ADDIK r30,r0,0 # clear div low
ADDIK r28,r0,64 # Initialize the loop count
# First part try to find the first '1' in the r5/r6
$LaDIV1:
ADD r6,r6,r6
ADDC r5,r5,r5 # left shift logical r5
BGEID r5,$LaDIV1
ADDIK r28,r28,-1
$LaDIV2:
ADD r6,r6,r6
ADDC r5,r5,r5 # left shift logical r5/r6 get the '1' into the Carry
ADDC r4,r4,r4 # Move that bit into the Mod register
ADDC r3,r3,r3 # Move carry into high mod register
rsub r18,r7,r3 # Compare the High Parts of Mod and Divisor
bnei r18,$L_High_EQ
rsub r18,r6,r4 # Compare Low Parts only if Mod[h] == Divisor[h]
$L_High_EQ:
rSUB r26,r8,r4 # Subtract divisor[L] from Mod[L]
rsubc r25,r7,r3 # Subtract divisor[H] from Mod[H]
BLTi r25,$LaMOD_TOO_SMALL
OR r3,r0,r25 # move r25 to mod [h]
OR r4,r0,r26 # move r26 to mod [l]
ADDI r30,r30,1
ADDC r29,r29,r0
$LaMOD_TOO_SMALL:
ADDIK r28,r28,-1
BEQi r28,$LaLOOP_END
ADD r30,r30,r30 # Shift in the '1' into div [low]
ADDC r29,r29,r29 # Move the carry generated into high
BRI $LaDIV2 # Div2
$LaLOOP_END:
BGEI r27,$LaRETURN_HERE
rsubi r30,r30,0
rsubc r29,r29,r0
BRI $LaRETURN_HERE
$LaDiv_By_Zero:
$LaResult_Is_Zero:
or r29,r0,r0 # set result to 0 [High]
or r30,r0,r0 # set result to 0 [Low]
$LaRETURN_HERE:
# Restore values of CSRs and that of r29 and the divisor and the dividend
lwi r25,r1,0
lwi r26,r1,4
lwi r27,r1,8
lwi r28,r1,12
lwi r29,r1,16
lwi r30,r1,20
rtsd r15,8
addik r1,r1,24
.end __moddi3

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@ -0,0 +1,93 @@
###################################
#
# Copyright 2009, 2010 Free Software Foundation, Inc.
#
# Contributed by Michael Eager <eager@eagercon.com>.
#
# This file is free software; you can redistribute it and/or modify it
# under the terms of the GNU General Public License as published by the
# Free Software Foundation; either version 3, or (at your option) any
# later version.
#
# GCC is distributed in the hope that it will be useful, but WITHOUT
# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
# License for more details.
#
# Under Section 7 of GPL version 3, you are granted additional
# permissions described in the GCC Runtime Library Exception, version
# 3.1, as published by the Free Software Foundation.
#
# You should have received a copy of the GNU General Public License and
# a copy of the GCC Runtime Library Exception along with this program;
# see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
# <http://www.gnu.org/licenses/>.
#
# modsi3.asm
#
# modulo operation for 32 bit integers.
# Input : op1 in Reg r5
# op2 in Reg r6
# Output: op1 mod op2 in Reg r3
#
#######################################
.globl __modsi3
.ent __modsi3
.type __modsi3,@function
__modsi3:
.frame r1,0,r15
addik r1,r1,-16
swi r28,r1,0
swi r29,r1,4
swi r30,r1,8
swi r31,r1,12
BEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error
BEQI r5,$LaResult_Is_Zero # Result is Zero
BGEId r5,$LaR5_Pos
ADD r28,r5,r0 # Get the sign of the result [ Depends only on the first arg]
RSUBI r5,r5,0 # Make r5 positive
$LaR5_Pos:
BGEI r6,$LaR6_Pos
RSUBI r6,r6,0 # Make r6 positive
$LaR6_Pos:
ADDIK r3,r0,0 # Clear mod
ADDIK r30,r0,0 # clear div
ADDIK r29,r0,32 # Initialize the loop count
# First part try to find the first '1' in the r5
$LaDIV1:
ADD r5,r5,r5 # left shift logical r5
BGEID r5,$LaDIV1 #
ADDIK r29,r29,-1
$LaDIV2:
ADD r5,r5,r5 # left shift logical r5 get the '1' into the Carry
ADDC r3,r3,r3 # Move that bit into the Mod register
rSUB r31,r6,r3 # Try to subtract (r30 a r6)
BLTi r31,$LaMOD_TOO_SMALL
OR r3,r0,r31 # Move the r31 to mod since the result was positive
ADDIK r30,r30,1
$LaMOD_TOO_SMALL:
ADDIK r29,r29,-1
BEQi r29,$LaLOOP_END
ADD r30,r30,r30 # Shift in the '1' into div
BRI $LaDIV2 # Div2
$LaLOOP_END:
BGEI r28,$LaRETURN_HERE
BRId $LaRETURN_HERE
rsubi r3,r3,0 # Negate the result
$LaDiv_By_Zero:
$LaResult_Is_Zero:
or r3,r0,r0 # set result to 0 [Both mod as well as div are 0]
$LaRETURN_HERE:
# Restore values of CSRs and that of r3 and the divisor and the dividend
lwi r28,r1,0
lwi r29,r1,4
lwi r30,r1,8
lwi r31,r1,12
rtsd r15,8
addik r1,r1,16
.end __modsi3
.size __modsi3, . - __modsi3

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@ -0,0 +1,144 @@
###################################-
#
# Copyright 2009, 2010 Free Software Foundation, Inc.
#
# Contributed by Michael Eager <eager@eagercon.com>.
#
# This file is free software; you can redistribute it and/or modify it
# under the terms of the GNU General Public License as published by the
# Free Software Foundation; either version 3, or (at your option) any
# later version.
#
# GCC is distributed in the hope that it will be useful, but WITHOUT
# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
# License for more details.
#
# Under Section 7 of GPL version 3, you are granted additional
# permissions described in the GCC Runtime Library Exception, version
# 3.1, as published by the Free Software Foundation.
#
# You should have received a copy of the GNU General Public License and
# a copy of the GCC Runtime Library Exception along with this program;
# see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
# <http://www.gnu.org/licenses/>.
#
# muldi3_hard.asm
#
# Multiply operation for 64 bit integers, for devices with hard multiply
# Input : Operand1[H] in Reg r5
# Operand1[L] in Reg r6
# Operand2[H] in Reg r7
# Operand2[L] in Reg r8
# Output: Result[H] in Reg r3
# Result[L] in Reg r4
#
# Explaination:
#
# Both the input numbers are divided into 16 bit number as follows
# op1 = A B C D
# op2 = E F G H
# result = D * H
# + (C * H + D * G) << 16
# + (B * H + C * G + D * F) << 32
# + (A * H + B * G + C * F + D * E) << 48
#
# Only 64 bits of the output are considered
#
#######################################
.globl muldi3_hardproc
.ent muldi3_hardproc
muldi3_hardproc:
addi r1,r1,-40
# Save the input operands on the caller's stack
swi r5,r1,44
swi r6,r1,48
swi r7,r1,52
swi r8,r1,56
# Store all the callee saved registers
sw r20,r1,r0
swi r21,r1,4
swi r22,r1,8
swi r23,r1,12
swi r24,r1,16
swi r25,r1,20
swi r26,r1,24
swi r27,r1,28
# Load all the 16 bit values for A thru H
lhui r20,r1,44 # A
lhui r21,r1,46 # B
lhui r22,r1,48 # C
lhui r23,r1,50 # D
lhui r24,r1,52 # E
lhui r25,r1,54 # F
lhui r26,r1,56 # G
lhui r27,r1,58 # H
# D * H ==> LSB of the result on stack ==> Store1
mul r9,r23,r27
swi r9,r1,36 # Pos2 and Pos3
# Hi (Store1) + C * H + D * G ==> Store2 ==> Pos1 and Pos2
# Store the carry generated in position 2 for Pos 3
lhui r11,r1,36 # Pos2
mul r9,r22,r27 # C * H
mul r10,r23,r26 # D * G
add r9,r9,r10
addc r12,r0,r0
add r9,r9,r11
addc r12,r12,r0 # Store the Carry
shi r9,r1,36 # Store Pos2
swi r9,r1,32
lhui r11,r1,32
shi r11,r1,34 # Store Pos1
# Hi (Store2) + B * H + C * G + D * F ==> Store3 ==> Pos0 and Pos1
mul r9,r21,r27 # B * H
mul r10,r22,r26 # C * G
mul r7,r23,r25 # D * F
add r9,r9,r11
add r9,r9,r10
add r9,r9,r7
swi r9,r1,32 # Pos0 and Pos1
# Hi (Store3) + A * H + B * G + C * F + D * E ==> Store3 ==> Pos0
lhui r11,r1,32 # Pos0
mul r9,r20,r27 # A * H
mul r10,r21,r26 # B * G
mul r7,r22,r25 # C * F
mul r8,r23,r24 # D * E
add r9,r9,r11
add r9,r9,r10
add r9,r9,r7
add r9,r9,r8
sext16 r9,r9 # Sign extend the MSB
shi r9,r1,32
# Move results to r3 and r4
lhui r3,r1,32
add r3,r3,r12
shi r3,r1,32
lwi r3,r1,32 # Hi Part
lwi r4,r1,36 # Lo Part
# Restore Callee saved registers
lw r20,r1,r0
lwi r21,r1,4
lwi r22,r1,8
lwi r23,r1,12
lwi r24,r1,16
lwi r25,r1,20
lwi r26,r1,24
lwi r27,r1,28
# Restore Frame and return
rtsd r15,8
addi r1,r1,40
.end muldi3_hardproc

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@ -0,0 +1,69 @@
###################################-*-asm*-
#
# Copyright 2009, 2010 Free Software Foundation, Inc.
#
# Contributed by Michael Eager <eager@eagercon.com>.
#
# This file is free software; you can redistribute it and/or modify it
# under the terms of the GNU General Public License as published by the
# Free Software Foundation; either version 3, or (at your option) any
# later version.
#
# GCC is distributed in the hope that it will be useful, but WITHOUT
# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
# License for more details.
#
# Under Section 7 of GPL version 3, you are granted additional
# permissions described in the GCC Runtime Library Exception, version
# 3.1, as published by the Free Software Foundation.
#
# You should have received a copy of the GNU General Public License and
# a copy of the GCC Runtime Library Exception along with this program;
# see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
# <http://www.gnu.org/licenses/>.
#
# mulsi3.asm
#
# Multiply operation for 32 bit integers.
# Input : Operand1 in Reg r5
# Operand2 in Reg r6
# Output: Result [op1 * op2] in Reg r3
#
#######################################
.globl __mulsi3
.ent __mulsi3
.type __mulsi3,@function
__mulsi3:
.frame r1,0,r15
add r3,r0,r0
BEQI r5,$L_Result_Is_Zero # Multiply by Zero
BEQI r6,$L_Result_Is_Zero # Multiply by Zero
BGEId r5,$L_R5_Pos
XOR r4,r5,r6 # Get the sign of the result
RSUBI r5,r5,0 # Make r5 positive
$L_R5_Pos:
BGEI r6,$L_R6_Pos
RSUBI r6,r6,0 # Make r6 positive
$L_R6_Pos:
bri $L1
$L2:
add r5,r5,r5
$L1:
srl r6,r6
addc r7,r0,r0
beqi r7,$L2
bneid r6,$L2
add r3,r3,r5
blti r4,$L_NegateResult
rtsd r15,8
nop
$L_NegateResult:
rtsd r15,8
rsub r3,r3,r0
$L_Result_Is_Zero:
rtsd r15,8
addi r3,r0,0
.end __mulsi3
.size __mulsi3, . - __mulsi3

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@ -0,0 +1,61 @@
###################################-*-asm*-
#
# Copyright 2009 Free Software Foundation, Inc.
#
#
# Contributed by Michael Eager <eager@eagercon.com>.
#
# This file is free software; you can redistribute it and/or modify it
# under the terms of the GNU General Public License as published by the
# Free Software Foundation; either version 3, or (at your option) any
# later version.
#
# GCC is distributed in the hope that it will be useful, but WITHOUT
# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
# License for more details.
#
# Under Section 7 of GPL version 3, you are granted additional
# permissions described in the GCC Runtime Library Exception, version
# 3.1, as published by the Free Software Foundation.
#
# You should have received a copy of the GNU General Public License and
# a copy of the GCC Runtime Library Exception along with this program;
# see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
# <http://www.gnu.org/licenses/>.
#
# stack_overflow_exit.asm
#
# Checks for stack overflows and sets the global variable
# stack_overflow_error with the value of current stack pointer
#
# This routine exits from the program
#
#######################################
.globl _stack_overflow_error
.data
.align 2
.type _stack_overflow_error,@object
.size _stack_overflow_error,4
_stack_overflow_error:
.data32 0
.text
.globl _stack_overflow_exit
.ent _stack_overflow_exit
.type _stack_overflow_exit,@function
_stack_overflow_exit:
#ifdef __PIC__
mfs r20,rpc
addik r20,r20,_GLOBAL_OFFSET_TABLE_+8
swi r1,r20,_stack_overflow_error@GOTOFF
bri exit@PLT
#else
swi r1,r0,_stack_overflow_error
bri exit
#endif
.end _stack_overflow_exit
.size _stack_overflow_exit,. - _stack_overflow_exit

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@ -0,0 +1,12 @@
LIB2ADD += \
$(srcdir)/config/microblaze/divsi3.asm \
$(srcdir)/config/microblaze/moddi3.asm \
$(srcdir)/config/microblaze/modsi3.asm \
$(srcdir)/config/microblaze/muldi3_hard.asm \
$(srcdir)/config/microblaze/mulsi3.asm \
$(srcdir)/config/microblaze/stack_overflow_exit.asm \
$(srcdir)/config/microblaze/udivsi3.asm \
$(srcdir)/config/microblaze/umodsi3.asm \
$(srcdir)/config/microblaze/divsi3_table.c
MULTILIB_OPTIONS = mxl-barrel-shift mno-xl-soft-mul mxl-multiply-high

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###################################-
#
# Copyright 2009, 2010 Free Software Foundation, Inc.
#
# Contributed by Michael Eager <eager@eagercon.com>.
#
# This file is free software; you can redistribute it and/or modify it
# under the terms of the GNU General Public License as published by the
# Free Software Foundation; either version 3, or (at your option) any
# later version.
#
# GCC is distributed in the hope that it will be useful, but WITHOUT
# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
# License for more details.
#
# Under Section 7 of GPL version 3, you are granted additional
# permissions described in the GCC Runtime Library Exception, version
# 3.1, as published by the Free Software Foundation.
#
# You should have received a copy of the GNU General Public License and
# a copy of the GCC Runtime Library Exception along with this program;
# see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
# <http://www.gnu.org/licenses/>.
#
# udivsi3.asm
#
# Unsigned divide operation.
# Input : Divisor in Reg r5
# Dividend in Reg r6
# Output: Result in Reg r3
#
#######################################
.globl __udivsi3
.ent __udivsi3
.type __udivsi3,@function
__udivsi3:
.frame r1,0,r15
ADDIK r1,r1,-12
SWI r29,r1,0
SWI r30,r1,4
SWI r31,r1,8
BEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error
BEQID r5,$LaResult_Is_Zero # Result is Zero
ADDIK r30,r0,0 # Clear mod
ADDIK r29,r0,32 # Initialize the loop count
# Check if r6 and r5 are equal # if yes, return 1
RSUB r18,r5,r6
BEQID r18,$LaRETURN_HERE
ADDIK r3,r0,1
# Check if (uns)r6 is greater than (uns)r5. In that case, just return 0
XOR r18,r5,r6
BGEID r18,16
ADD r3,r0,r0 # We would anyways clear r3
BLTI r6,$LaRETURN_HERE # r6[bit 31 = 1] hence is greater
BRI $LCheckr6
RSUB r18,r6,r5 # MICROBLAZEcmp
BLTI r18,$LaRETURN_HERE
# If r6 [bit 31] is set, then return result as 1
$LCheckr6:
BGTI r6,$LaDIV0
BRID $LaRETURN_HERE
ADDIK r3,r0,1
# First part try to find the first '1' in the r5
$LaDIV0:
BLTI r5,$LaDIV2
$LaDIV1:
ADD r5,r5,r5 # left shift logical r5
BGTID r5,$LaDIV1
ADDIK r29,r29,-1
$LaDIV2:
ADD r5,r5,r5 # left shift logical r5 get the '1' into the Carry
ADDC r30,r30,r30 # Move that bit into the Mod register
RSUB r31,r6,r30 # Try to subtract (r30 a r6)
BLTI r31,$LaMOD_TOO_SMALL
OR r30,r0,r31 # Move the r31 to mod since the result was positive
ADDIK r3,r3,1
$LaMOD_TOO_SMALL:
ADDIK r29,r29,-1
BEQi r29,$LaLOOP_END
ADD r3,r3,r3 # Shift in the '1' into div
BRI $LaDIV2 # Div2
$LaLOOP_END:
BRI $LaRETURN_HERE
$LaDiv_By_Zero:
$LaResult_Is_Zero:
OR r3,r0,r0 # set result to 0
$LaRETURN_HERE:
# Restore values of CSRs and that of r3 and the divisor and the dividend
LWI r29,r1,0
LWI r30,r1,4
LWI r31,r1,8
RTSD r15,8
ADDIK r1,r1,12
.end __udivsi3
.size __udivsi3, . - __udivsi3

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@ -0,0 +1,106 @@
###################################
#
# Copyright 2009, 2010 Free Software Foundation, Inc.
#
# Contributed by Michael Eager <eager@eagercon.com>.
#
# This file is free software; you can redistribute it and/or modify it
# under the terms of the GNU General Public License as published by the
# Free Software Foundation; either version 3, or (at your option) any
# later version.
#
# GCC is distributed in the hope that it will be useful, but WITHOUT
# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
# License for more details.
#
# Under Section 7 of GPL version 3, you are granted additional
# permissions described in the GCC Runtime Library Exception, version
# 3.1, as published by the Free Software Foundation.
#
# You should have received a copy of the GNU General Public License and
# a copy of the GCC Runtime Library Exception along with this program;
# see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
# <http://www.gnu.org/licenses/>.
#
# umodsi3.asm
#
# Unsigned modulo operation for 32 bit integers.
# Input : op1 in Reg r5
# op2 in Reg r6
# Output: op1 mod op2 in Reg r3
#
#######################################
.globl __umodsi3
.ent __umodsi3
.type __umodsi3,@function
__umodsi3:
.frame r1,0,r15
addik r1,r1,-12
swi r29,r1,0
swi r30,r1,4
swi r31,r1,8
BEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error
BEQId r5,$LaResult_Is_Zero # Result is Zero
ADDIK r3,r0,0 # Clear div
ADDIK r30,r0,0 # clear mod
ADDIK r29,r0,32 # Initialize the loop count
# Check if r6 and r5 are equal # if yes, return 0
rsub r18,r5,r6
beqi r18,$LaRETURN_HERE
# Check if (uns)r6 is greater than (uns)r5. In that case, just return r5
xor r18,r5,r6
bgeid r18,16
addik r3,r5,0
blti r6,$LaRETURN_HERE
bri $LCheckr6
rsub r18,r5,r6 # MICROBLAZEcmp
bgti r18,$LaRETURN_HERE
# If r6 [bit 31] is set, then return result as r5-r6
$LCheckr6:
bgtid r6,$LaDIV0
addik r3,r0,0
addik r18,r0,0x7fffffff
and r5,r5,r18
and r6,r6,r18
brid $LaRETURN_HERE
rsub r3,r6,r5
# First part: try to find the first '1' in the r5
$LaDIV0:
BLTI r5,$LaDIV2
$LaDIV1:
ADD r5,r5,r5 # left shift logical r5
BGEID r5,$LaDIV1 #
ADDIK r29,r29,-1
$LaDIV2:
ADD r5,r5,r5 # left shift logical r5 get the '1' into the Carry
ADDC r3,r3,r3 # Move that bit into the Mod register
rSUB r31,r6,r3 # Try to subtract (r3 a r6)
BLTi r31,$LaMOD_TOO_SMALL
OR r3,r0,r31 # Move the r31 to mod since the result was positive
ADDIK r30,r30,1
$LaMOD_TOO_SMALL:
ADDIK r29,r29,-1
BEQi r29,$LaLOOP_END
ADD r30,r30,r30 # Shift in the '1' into div
BRI $LaDIV2 # Div2
$LaLOOP_END:
BRI $LaRETURN_HERE
$LaDiv_By_Zero:
$LaResult_Is_Zero:
or r3,r0,r0 # set result to 0
$LaRETURN_HERE:
# Restore values of CSRs and that of r3 and the divisor and the dividend
lwi r29,r1,0
lwi r30,r1,4
lwi r31,r1,8
rtsd r15,8
addik r1,r1,12
.end __umodsi3
.size __umodsi3, . - __umodsi3

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@ -1,3 +1,8 @@
2010-09-30 Michael Eager <eager@eagercon.com>
* config/cpu/microblaze/cpu_defines.h: New. Define
_GLIBCXX_NO_VERBOSE_TERMINATE for MicroBlaze.
2010-09-29 Paolo Carlini <paolo.carlini@oracle.com>
* include/Makefile.am: Add debug/forward_list.
@ -75,6 +80,7 @@
* configure: Regenerate.
* include/Makefile.in: Likewise.
>>>>>>> .r164755
2010-09-22 David Krauss <potswa@mac.com>
PR libstdc++/45628

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@ -0,0 +1,34 @@
// Specific definitions for Xilinx MicroBlaze platforms -*- C++ -*-
// Copyright (C) 2009, 2010 Free Software Foundation, Inc.
//
// Contributed by Michael Eager <eager@eagercon.com>.
//
// This file is part of the GNU ISO C++ Library. This library is free
// software; you can redistribute it and/or modify it under the
// terms of the GNU General Public License as published by the
// Free Software Foundation; either version 3, or (at your option)
// any later version.
// This library is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
// Under Section 7 of GPL version 3, you are granted additional
// permissions described in the GCC Runtime Library Exception, version
// 3.1, as published by the Free Software Foundation.
// You should have received a copy of the GNU General Public License and
// a copy of the GCC Runtime Library Exception along with this program;
// see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
// <http://www.gnu.org/licenses/>.
#ifndef _GLIBCXX_CPU_DEFINES
#define _GLIBCXX_CPU_DEFINES 1
// Optimize memory size for embedded systems
// -- Use abort for eh terminate
#define _GLIBCXX_NO_VERBOSE_TERMINATE 1
#endif