iq2000.c (uns_arith_operand, [...]): Move to predicates.md.
* config/iq2000/iq2000.c (uns_arith_operand, arith_operand, small_int, large_int, reg_or_0_operand, simple_memory_operand, equality_op, cmp_op, pc_or_label_operand, call_insn_operand, move_operand, power_of_2_operand): Move to predicates.md. * config/iq2000/iq2000.h (SPECIAL_MODE_PREDICATES, PREDICATE_CODE): Remove. * config/iq2000/iq2000.md: Include predicates.md. * config/iq2000/predicates.md: New. From-SVN: r97472
This commit is contained in:
Kazu Hirata
Kazu Hirata
parent
fc9c289a80
commit
80ad92e985
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@ -1,3 +1,14 @@
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2005-04-02 Kazu Hirata <kazu@cs.umass.edu>
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* config/iq2000/iq2000.c (uns_arith_operand, arith_operand,
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small_int, large_int, reg_or_0_operand, simple_memory_operand,
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equality_op, cmp_op, pc_or_label_operand, call_insn_operand,
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move_operand, power_of_2_operand): Move to predicates.md.
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* config/iq2000/iq2000.h (SPECIAL_MODE_PREDICATES,
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PREDICATE_CODE): Remove.
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* config/iq2000/iq2000.md: Include predicates.md.
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* config/iq2000/predicates.md: New.
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2005-04-02 Richard Sandiford <rsandifo@redhat.com>
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* config/m68hc11/m68hc11.h (target_flags, MASK_SHORT)
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@ -208,217 +208,6 @@ static int iq2000_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
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struct gcc_target targetm = TARGET_INITIALIZER;
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/* Return 1 if OP can be used as an operand where a register or 16 bit unsigned
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integer is needed. */
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int
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uns_arith_operand (rtx op, enum machine_mode mode)
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{
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if (GET_CODE (op) == CONST_INT && SMALL_INT_UNSIGNED (op))
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return 1;
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return register_operand (op, mode);
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}
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/* Return 1 if OP can be used as an operand where a 16 bit integer is needed. */
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int
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arith_operand (rtx op, enum machine_mode mode)
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{
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if (GET_CODE (op) == CONST_INT && SMALL_INT (op))
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return 1;
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return register_operand (op, mode);
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}
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/* Return 1 if OP is a integer which fits in 16 bits. */
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int
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small_int (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
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{
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return (GET_CODE (op) == CONST_INT && SMALL_INT (op));
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}
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/* Return 1 if OP is a 32 bit integer which is too big to be loaded with one
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instruction. */
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int
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large_int (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
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{
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HOST_WIDE_INT value;
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if (GET_CODE (op) != CONST_INT)
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return 0;
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value = INTVAL (op);
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/* IOR reg,$r0,value. */
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if ((value & ~ ((HOST_WIDE_INT) 0x0000ffff)) == 0)
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return 0;
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/* SUBU reg,$r0,value. */
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if (((unsigned HOST_WIDE_INT) (value + 32768)) <= 32767)
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return 0;
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/* LUI reg,value >> 16. */
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if ((value & 0x0000ffff) == 0)
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return 0;
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return 1;
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}
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/* Return 1 if OP is a register or the constant 0. */
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int
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reg_or_0_operand (rtx op, enum machine_mode mode)
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{
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switch (GET_CODE (op))
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{
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case CONST_INT:
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return INTVAL (op) == 0;
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case CONST_DOUBLE:
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return op == CONST0_RTX (mode);
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case REG:
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case SUBREG:
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return register_operand (op, mode);
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default:
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break;
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}
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return 0;
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}
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/* Return 1 if OP is a memory operand that fits in a single instruction
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(i.e., register + small offset). */
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int
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simple_memory_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
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{
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rtx addr, plus0, plus1;
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/* Eliminate non-memory operations. */
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if (GET_CODE (op) != MEM)
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return 0;
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/* Dword operations really put out 2 instructions, so eliminate them. */
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if (GET_MODE_SIZE (GET_MODE (op)) > (unsigned) UNITS_PER_WORD)
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return 0;
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/* Decode the address now. */
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addr = XEXP (op, 0);
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switch (GET_CODE (addr))
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{
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case REG:
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case LO_SUM:
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return 1;
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case CONST_INT:
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return SMALL_INT (addr);
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case PLUS:
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plus0 = XEXP (addr, 0);
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plus1 = XEXP (addr, 1);
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if (GET_CODE (plus0) == REG
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&& GET_CODE (plus1) == CONST_INT && SMALL_INT (plus1)
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&& SMALL_INT_UNSIGNED (plus1) /* No negative offsets. */)
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return 1;
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else if (GET_CODE (plus1) == REG
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&& GET_CODE (plus0) == CONST_INT && SMALL_INT (plus0)
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&& SMALL_INT_UNSIGNED (plus1) /* No negative offsets. */)
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return 1;
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else
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return 0;
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case SYMBOL_REF:
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return 0;
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default:
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break;
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}
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return 0;
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}
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/* Return nonzero if the code of this rtx pattern is EQ or NE. */
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int
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equality_op (rtx op, enum machine_mode mode)
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{
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if (mode != GET_MODE (op))
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return 0;
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return GET_CODE (op) == EQ || GET_CODE (op) == NE;
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}
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/* Return nonzero if the code is a relational operations (EQ, LE, etc). */
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int
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cmp_op (rtx op, enum machine_mode mode)
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{
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if (mode != GET_MODE (op))
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return 0;
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return COMPARISON_P (op);
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}
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/* Return nonzero if the operand is either the PC or a label_ref. */
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int
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pc_or_label_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
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{
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if (op == pc_rtx)
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return 1;
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if (GET_CODE (op) == LABEL_REF)
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return 1;
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return 0;
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}
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/* Return nonzero if OP is a valid operand for a call instruction. */
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int
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call_insn_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
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{
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return (CONSTANT_ADDRESS_P (op)
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|| (GET_CODE (op) == REG && op != arg_pointer_rtx
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&& ! (REGNO (op) >= FIRST_PSEUDO_REGISTER
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&& REGNO (op) <= LAST_VIRTUAL_REGISTER)));
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}
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/* Return nonzero if OP is valid as a source operand for a move instruction. */
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int
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move_operand (rtx op, enum machine_mode mode)
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{
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/* Accept any general operand after reload has started; doing so
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avoids losing if reload does an in-place replacement of a register
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with a SYMBOL_REF or CONST. */
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return (general_operand (op, mode)
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&& (! (iq2000_check_split (op, mode))
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|| reload_in_progress || reload_completed));
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}
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/* Return nonzero if OP is a constant power of 2. */
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int
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power_of_2_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
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{
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int intval;
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if (GET_CODE (op) != CONST_INT)
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return 0;
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else
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intval = INTVAL (op);
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return ((intval & ((unsigned)(intval) - 1)) == 0);
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}
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/* Return nonzero if we split the address into high and low parts. */
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int
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@ -779,23 +779,6 @@ while (0)
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/* Miscellaneous Parameters. */
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#define PREDICATE_CODES \
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{"uns_arith_operand", { REG, CONST_INT, SUBREG }}, \
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{"arith_operand", { REG, CONST_INT, SUBREG }}, \
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{"small_int", { CONST_INT }}, \
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{"large_int", { CONST_INT }}, \
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{"reg_or_0_operand", { REG, CONST_INT, CONST_DOUBLE, SUBREG }}, \
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{"simple_memory_operand", { MEM, SUBREG }}, \
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{"equality_op", { EQ, NE }}, \
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{"cmp_op", { EQ, NE, GT, GE, GTU, GEU, LT, LE, \
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LTU, LEU }}, \
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{"pc_or_label_operand", { PC, LABEL_REF }}, \
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{"call_insn_operand", { CONST_INT, CONST, SYMBOL_REF, REG}}, \
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{"move_operand", { CONST_INT, CONST_DOUBLE, CONST, \
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SYMBOL_REF, LABEL_REF, SUBREG, \
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REG, MEM}}, \
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{"power_of_2_operand", { CONST_INT }},
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#define CASE_VECTOR_MODE SImode
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#define WORD_REGISTER_OPERATIONS
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@ -1062,13 +1045,6 @@ extern void sbss_section (void);
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((LENGTH) = iq2000_adjust_insn_length ((INSN), (LENGTH)))
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/* A list of predicates that do special things with modes, and so
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should not elicit warnings for VOIDmode match_operand. */
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#define SPECIAL_MODE_PREDICATES \
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"pc_or_label_operand",
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/* How to tell the debugger about changes of source files. */
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@ -1,5 +1,5 @@
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;; iq2000.md Machine Description for Vitesse IQ2000 processors
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;; Copyright (C) 2003, 2004 Free Software Foundation, Inc.
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;; Copyright (C) 2003, 2004, 2005 Free Software Foundation, Inc.
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;; This file is part of GCC.
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@ -194,6 +194,7 @@
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(nil)
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(nil)])
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(include "predicates.md")
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;; .........................
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@ -0,0 +1,233 @@
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;; Predicate definitions for Vitesse IQ2000.
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;; Copyright (C) 2005 Free Software Foundation, Inc.
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;;
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;; This file is part of GCC.
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;;
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;; GCC is free software; you can redistribute it and/or modify
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;; it under the terms of the GNU General Public License as published by
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;; the Free Software Foundation; either version 2, or (at your option)
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;; any later version.
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;;
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;; GCC is distributed in the hope that it will be useful,
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;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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;; GNU General Public License for more details.
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;;
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING. If not, write to
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;; the Free Software Foundation, 59 Temple Place - Suite 330,
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;; Boston, MA 02111-1307, USA.
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;; Return 1 if OP can be used as an operand where a register or 16 bit
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;; unsigned integer is needed.
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(define_predicate "uns_arith_operand"
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(match_code "reg,const_int,subreg")
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{
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if (GET_CODE (op) == CONST_INT && SMALL_INT_UNSIGNED (op))
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return 1;
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return register_operand (op, mode);
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})
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;; Return 1 if OP can be used as an operand where a 16 bit integer is
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;; needed.
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(define_predicate "arith_operand"
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(match_code "reg,const_int,subreg")
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{
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if (GET_CODE (op) == CONST_INT && SMALL_INT (op))
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return 1;
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return register_operand (op, mode);
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})
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;; Return 1 if OP is a integer which fits in 16 bits.
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(define_predicate "small_int"
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(match_code "const_int")
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{
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return (GET_CODE (op) == CONST_INT && SMALL_INT (op));
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})
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;; Return 1 if OP is a 32 bit integer which is too big to be loaded
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;; with one instruction.
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(define_predicate "large_int"
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(match_code "const_int")
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{
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HOST_WIDE_INT value;
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if (GET_CODE (op) != CONST_INT)
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return 0;
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value = INTVAL (op);
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/* IOR reg,$r0,value. */
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if ((value & ~ ((HOST_WIDE_INT) 0x0000ffff)) == 0)
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return 0;
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/* SUBU reg,$r0,value. */
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if (((unsigned HOST_WIDE_INT) (value + 32768)) <= 32767)
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return 0;
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/* LUI reg,value >> 16. */
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if ((value & 0x0000ffff) == 0)
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return 0;
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return 1;
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})
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;; Return 1 if OP is a register or the constant 0.
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(define_predicate "reg_or_0_operand"
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(match_code "reg,const_int,const_double,subreg")
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{
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switch (GET_CODE (op))
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{
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case CONST_INT:
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return INTVAL (op) == 0;
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case CONST_DOUBLE:
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return op == CONST0_RTX (mode);
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case REG:
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case SUBREG:
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return register_operand (op, mode);
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default:
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break;
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}
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return 0;
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})
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;; Return 1 if OP is a memory operand that fits in a single
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;; instruction (i.e., register + small offset).
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(define_predicate "simple_memory_operand"
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(match_code "mem,subreg")
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{
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rtx addr, plus0, plus1;
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/* Eliminate non-memory operations. */
|
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if (GET_CODE (op) != MEM)
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return 0;
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|
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/* Dword operations really put out 2 instructions, so eliminate them. */
|
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if (GET_MODE_SIZE (GET_MODE (op)) > (unsigned) UNITS_PER_WORD)
|
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return 0;
|
||||
|
||||
/* Decode the address now. */
|
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addr = XEXP (op, 0);
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switch (GET_CODE (addr))
|
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{
|
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case REG:
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case LO_SUM:
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return 1;
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case CONST_INT:
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return SMALL_INT (addr);
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case PLUS:
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plus0 = XEXP (addr, 0);
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plus1 = XEXP (addr, 1);
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if (GET_CODE (plus0) == REG
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&& GET_CODE (plus1) == CONST_INT && SMALL_INT (plus1)
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&& SMALL_INT_UNSIGNED (plus1) /* No negative offsets. */)
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return 1;
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|
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else if (GET_CODE (plus1) == REG
|
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&& GET_CODE (plus0) == CONST_INT && SMALL_INT (plus0)
|
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&& SMALL_INT_UNSIGNED (plus1) /* No negative offsets. */)
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return 1;
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else
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return 0;
|
||||
|
||||
case SYMBOL_REF:
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return 0;
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||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
return 0;
|
||||
})
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||||
|
||||
;; Return nonzero if the code of this rtx pattern is EQ or NE.
|
||||
|
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(define_predicate "equality_op"
|
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(match_code "eq,ne")
|
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{
|
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if (mode != GET_MODE (op))
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return 0;
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||||
|
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return GET_CODE (op) == EQ || GET_CODE (op) == NE;
|
||||
})
|
||||
|
||||
;; Return nonzero if the code is a relational operations (EQ, LE,
|
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;; etc).
|
||||
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(define_predicate "cmp_op"
|
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(match_code "eq,ne,gt,ge,gtu,geu,lt,le,ltu,leu")
|
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{
|
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if (mode != GET_MODE (op))
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return 0;
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||||
|
||||
return COMPARISON_P (op);
|
||||
})
|
||||
|
||||
;; Return nonzero if the operand is either the PC or a label_ref.
|
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|
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(define_special_predicate "pc_or_label_operand"
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(match_code "pc,label_ref")
|
||||
{
|
||||
if (op == pc_rtx)
|
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return 1;
|
||||
|
||||
if (GET_CODE (op) == LABEL_REF)
|
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return 1;
|
||||
|
||||
return 0;
|
||||
})
|
||||
|
||||
;; Return nonzero if OP is a valid operand for a call instruction.
|
||||
|
||||
(define_predicate "call_insn_operand"
|
||||
(match_code "const_int,const,symbol_ref,reg")
|
||||
{
|
||||
return (CONSTANT_ADDRESS_P (op)
|
||||
|| (GET_CODE (op) == REG && op != arg_pointer_rtx
|
||||
&& ! (REGNO (op) >= FIRST_PSEUDO_REGISTER
|
||||
&& REGNO (op) <= LAST_VIRTUAL_REGISTER)));
|
||||
})
|
||||
|
||||
;; Return nonzero if OP is valid as a source operand for a move
|
||||
;; instruction.
|
||||
|
||||
(define_predicate "move_operand"
|
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(match_code "const_int,const_double,const,symbol_ref,label_ref,subreg,reg,mem")
|
||||
{
|
||||
/* Accept any general operand after reload has started; doing so
|
||||
avoids losing if reload does an in-place replacement of a register
|
||||
with a SYMBOL_REF or CONST. */
|
||||
return (general_operand (op, mode)
|
||||
&& (! (iq2000_check_split (op, mode))
|
||||
|| reload_in_progress || reload_completed));
|
||||
})
|
||||
|
||||
;; Return nonzero if OP is a constant power of 2.
|
||||
|
||||
(define_predicate "power_of_2_operand"
|
||||
(match_code "const_int")
|
||||
{
|
||||
int intval;
|
||||
|
||||
if (GET_CODE (op) != CONST_INT)
|
||||
return 0;
|
||||
else
|
||||
intval = INTVAL (op);
|
||||
|
||||
return ((intval & ((unsigned)(intval) - 1)) == 0);
|
||||
})
|
||||
Loading…
Reference in New Issue