[AArch64] Simplify prologue expand using new helper functions.
From-SVN: r212957
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@ -1,3 +1,10 @@
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2014-07-23 Jiong Wang <jiong.wang@arm.com>
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* config/aarch64/aarch64.c (aarch64_pushwb_pair_reg)
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(aarch64_gen_storewb_pair): New helper function.
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(aarch64_expand_prologue): Simplify code using new helper functions.
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* config/aarch64/aarch64.md (storewb_pair<GPF:mode>_<P:mode>): Define.
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2014-07-23 Jiong Wang <jiong.wang@arm.com>
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2014-07-23 Jiong Wang <jiong.wang@arm.com>
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* config/aarch64/aarch64.md: (aarch64_save_or_restore_callee_saves):
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* config/aarch64/aarch64.md: (aarch64_save_or_restore_callee_saves):
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@ -1916,6 +1916,41 @@ aarch64_next_callee_save (unsigned regno, unsigned limit)
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return regno;
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return regno;
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}
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}
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static rtx
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aarch64_gen_storewb_pair (enum machine_mode mode, rtx base, rtx reg, rtx reg2,
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HOST_WIDE_INT adjustment)
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{
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switch (mode)
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{
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case DImode:
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return gen_storewb_pairdi_di (base, base, reg, reg2,
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GEN_INT (-adjustment),
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GEN_INT (UNITS_PER_WORD - adjustment));
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case DFmode:
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return gen_storewb_pairdf_di (base, base, reg, reg2,
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GEN_INT (-adjustment),
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GEN_INT (UNITS_PER_WORD - adjustment));
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default:
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gcc_unreachable ();
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}
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}
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static void
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aarch64_pushwb_pair_reg (enum machine_mode mode, unsigned regno1,
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unsigned regno2, HOST_WIDE_INT adjustment)
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{
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rtx insn;
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rtx reg1 = gen_rtx_REG (mode, regno1);
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rtx reg2 = gen_rtx_REG (mode, regno2);
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insn = emit_insn (aarch64_gen_storewb_pair (mode, stack_pointer_rtx, reg1,
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reg2, adjustment));
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RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, 2)) = 1;
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RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, 1)) = 1;
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RTX_FRAME_RELATED_P (insn) = 1;
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}
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static rtx
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static rtx
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aarch64_gen_store_pair (enum machine_mode mode, rtx mem1, rtx reg1, rtx mem2,
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aarch64_gen_store_pair (enum machine_mode mode, rtx mem1, rtx reg1, rtx mem2,
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rtx reg2)
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rtx reg2)
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@ -2183,8 +2218,6 @@ aarch64_expand_prologue (void)
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old frame pointer on the stack. */
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old frame pointer on the stack. */
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if (frame_pointer_needed)
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if (frame_pointer_needed)
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{
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{
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rtx mem_fp, mem_lr;
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if (fp_offset)
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if (fp_offset)
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{
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{
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insn = emit_insn (gen_add2_insn (stack_pointer_rtx,
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insn = emit_insn (gen_add2_insn (stack_pointer_rtx,
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@ -2195,38 +2228,12 @@ aarch64_expand_prologue (void)
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gen_rtx_MINUS (Pmode,
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gen_rtx_MINUS (Pmode,
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stack_pointer_rtx,
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stack_pointer_rtx,
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GEN_INT (offset))));
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GEN_INT (offset))));
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mem_fp = gen_frame_mem (DImode,
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plus_constant (Pmode,
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aarch64_save_callee_saves (DImode, fp_offset, R29_REGNUM,
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stack_pointer_rtx,
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R30_REGNUM);
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fp_offset));
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mem_lr = gen_frame_mem (DImode,
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plus_constant (Pmode,
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stack_pointer_rtx,
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fp_offset
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+ UNITS_PER_WORD));
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insn = emit_insn (gen_store_pairdi (mem_fp,
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hard_frame_pointer_rtx,
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mem_lr,
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gen_rtx_REG (DImode,
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LR_REGNUM)));
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}
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}
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else
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else
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{
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aarch64_pushwb_pair_reg (DImode, R29_REGNUM, R30_REGNUM, offset);
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insn = emit_insn (gen_storewb_pairdi_di
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(stack_pointer_rtx, stack_pointer_rtx,
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hard_frame_pointer_rtx,
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gen_rtx_REG (DImode, LR_REGNUM),
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GEN_INT (-offset),
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GEN_INT (GET_MODE_SIZE (DImode) - offset)));
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RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, 2)) = 1;
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}
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/* The first part of a frame-related parallel insn is always
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assumed to be relevant to the frame calculations;
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subsequent parts, are only frame-related if explicitly
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marked. */
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RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, 1)) = 1;
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RTX_FRAME_RELATED_P (insn) = 1;
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/* Set up frame pointer to point to the location of the
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/* Set up frame pointer to point to the location of the
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previous frame pointer on the stack. */
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previous frame pointer on the stack. */
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@ -2241,17 +2248,18 @@ aarch64_expand_prologue (void)
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RTX_FRAME_RELATED_P (insn) = 1;
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RTX_FRAME_RELATED_P (insn) = 1;
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insn = emit_insn (gen_stack_tie (stack_pointer_rtx,
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insn = emit_insn (gen_stack_tie (stack_pointer_rtx,
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hard_frame_pointer_rtx));
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hard_frame_pointer_rtx));
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aarch64_save_callee_saves (DImode, fp_offset, R0_REGNUM, R28_REGNUM);
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}
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}
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else
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else
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{
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{
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insn = emit_insn (gen_add2_insn (stack_pointer_rtx,
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insn = emit_insn (gen_add2_insn (stack_pointer_rtx,
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GEN_INT (-offset)));
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GEN_INT (-offset)));
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RTX_FRAME_RELATED_P (insn) = 1;
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RTX_FRAME_RELATED_P (insn) = 1;
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aarch64_save_callee_saves (DImode, fp_offset, R0_REGNUM, R30_REGNUM);
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}
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}
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aarch64_save_callee_saves (DImode, fp_offset, R0_REGNUM,
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frame_pointer_needed
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? R28_REGNUM : R30_REGNUM);
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aarch64_save_callee_saves (DFmode, fp_offset, V0_REGNUM, V31_REGNUM);
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aarch64_save_callee_saves (DFmode, fp_offset, V0_REGNUM, V31_REGNUM);
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}
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}
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@ -1052,6 +1052,22 @@
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[(set_attr "type" "store2")]
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[(set_attr "type" "store2")]
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)
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)
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(define_insn "storewb_pair<GPF:mode>_<P:mode>"
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[(parallel
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[(set (match_operand:P 0 "register_operand" "=&k")
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(plus:P (match_operand:P 1 "register_operand" "0")
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(match_operand:P 4 "const_int_operand" "n")))
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(set (mem:GPF (plus:P (match_dup 0)
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(match_dup 4)))
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(match_operand:GPF 2 "register_operand" "w"))
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(set (mem:GPF (plus:P (match_dup 0)
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(match_operand:P 5 "const_int_operand" "n")))
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(match_operand:GPF 3 "register_operand" "w"))])]
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"INTVAL (operands[5]) == INTVAL (operands[4]) + GET_MODE_SIZE (<GPF:MODE>mode)"
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"stp\\t%<w>2, %<w>3, [%0, %4]!"
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[(set_attr "type" "neon_store1_2reg<q>")]
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)
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;; -------------------------------------------------------------------
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;; -------------------------------------------------------------------
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;; Sign/Zero extension
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;; Sign/Zero extension
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;; -------------------------------------------------------------------
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;; -------------------------------------------------------------------
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