arm.c (neon_vdup_constant, [...]): New.
gcc/ * config/arm/arm.c (neon_vdup_constant, neon_make_constant): New. (neon_expand_vector_init): Use them. Also handle non-constant vectors with identical elements and vectors with only one non-constant element. (arm_print_operand): Handle 'y' modifier. * config/arm/arm-protos.h (neon_make_constant): Declare. * config/arm/neon.md (neon_vdup_n<mode>): Split into two patterns. Use VX instead of VDQW for the first one. Allow a VFP alternative and V32 modes for the second one. * config/arm/neon.ml (shape_elt): Add Alternatives. (ops): Use Alternatives for vdup lane instructions. * config/arm/neon-testgen.ml (analyze_shape): Handle Alternatives. * config/arm/vec-common.md (mov<mode>): Use neon_make_constant. gcc/testsuite/ * gcc.target/arm/neon: Regenerate generated tests. From-SVN: r154094
This commit is contained in:
Daniel Jacobowitz
Daniel Jacobowitz
parent
40f73786e9
commit
814a4c3b35
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@ -1,3 +1,19 @@
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2009-11-11 Daniel Jacobowitz <dan@codesourcery.com>
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* config/arm/arm.c (neon_vdup_constant, neon_make_constant): New.
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(neon_expand_vector_init): Use them. Also handle non-constant
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vectors with identical elements and vectors with only one
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non-constant element.
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(arm_print_operand): Handle 'y' modifier.
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* config/arm/arm-protos.h (neon_make_constant): Declare.
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* config/arm/neon.md (neon_vdup_n<mode>): Split into two
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patterns. Use VX instead of VDQW for the first one. Allow
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a VFP alternative and V32 modes for the second one.
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* config/arm/neon.ml (shape_elt): Add Alternatives.
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(ops): Use Alternatives for vdup lane instructions.
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* config/arm/neon-testgen.ml (analyze_shape): Handle Alternatives.
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* config/arm/vec-common.md (mov<mode>): Use neon_make_constant.
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2009-11-11 Daniel Jacobowitz <dan@codesourcery.com>
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* config/arm/neon.md (*neon_mov<mode>): Reject two non-register
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@ -68,6 +68,7 @@ extern char *neon_output_logic_immediate (const char *, rtx *,
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enum machine_mode, int, int);
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extern void neon_pairwise_reduce (rtx, rtx, enum machine_mode,
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rtx (*) (rtx, rtx, rtx));
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extern rtx neon_make_constant (rtx);
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extern void neon_expand_vector_init (rtx, rtx);
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extern void neon_lane_bounds (rtx, HOST_WIDE_INT, HOST_WIDE_INT);
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extern void neon_const_bounds (rtx, HOST_WIDE_INT, HOST_WIDE_INT);
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@ -8085,25 +8085,171 @@ neon_pairwise_reduce (rtx op0, rtx op1, enum machine_mode mode,
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}
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}
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/* Initialize a vector with non-constant elements. FIXME: We can do better
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than the current implementation (building a vector on the stack and then
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loading it) in many cases. See rs6000.c. */
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/* If VALS is a vector constant that can be loaded into a register
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using VDUP, generate instructions to do so and return an RTX to
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assign to the register. Otherwise return NULL_RTX. */
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static rtx
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neon_vdup_constant (rtx vals)
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{
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enum machine_mode mode = GET_MODE (vals);
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enum machine_mode inner_mode = GET_MODE_INNER (mode);
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int n_elts = GET_MODE_NUNITS (mode);
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bool all_same = true;
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rtx x;
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int i;
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if (GET_CODE (vals) != CONST_VECTOR || GET_MODE_SIZE (inner_mode) > 4)
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return NULL_RTX;
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for (i = 0; i < n_elts; ++i)
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{
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x = XVECEXP (vals, 0, i);
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if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0)))
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all_same = false;
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}
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if (!all_same)
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/* The elements are not all the same. We could handle repeating
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patterns of a mode larger than INNER_MODE here (e.g. int8x8_t
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{0, C, 0, C, 0, C, 0, C} which can be loaded using
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vdup.i16). */
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return NULL_RTX;
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/* We can load this constant by using VDUP and a constant in a
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single ARM register. This will be cheaper than a vector
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load. */
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x = copy_to_mode_reg (inner_mode, XVECEXP (vals, 0, 0));
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return gen_rtx_UNSPEC (mode, gen_rtvec (1, x),
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UNSPEC_VDUP_N);
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}
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/* Generate code to load VALS, which is a PARALLEL containing only
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constants (for vec_init) or CONST_VECTOR, efficiently into a
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register. Returns an RTX to copy into the register, or NULL_RTX
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for a PARALLEL that can not be converted into a CONST_VECTOR. */
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rtx
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neon_make_constant (rtx vals)
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{
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enum machine_mode mode = GET_MODE (vals);
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rtx target;
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rtx const_vec = NULL_RTX;
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int n_elts = GET_MODE_NUNITS (mode);
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int n_const = 0;
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int i;
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if (GET_CODE (vals) == CONST_VECTOR)
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const_vec = vals;
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else if (GET_CODE (vals) == PARALLEL)
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{
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/* A CONST_VECTOR must contain only CONST_INTs and
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CONST_DOUBLEs, but CONSTANT_P allows more (e.g. SYMBOL_REF).
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Only store valid constants in a CONST_VECTOR. */
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for (i = 0; i < n_elts; ++i)
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{
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rtx x = XVECEXP (vals, 0, i);
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if (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE)
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n_const++;
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}
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if (n_const == n_elts)
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const_vec = gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0));
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}
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else
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gcc_unreachable ();
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if (const_vec != NULL
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&& neon_immediate_valid_for_move (const_vec, mode, NULL, NULL))
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/* Load using VMOV. On Cortex-A8 this takes one cycle. */
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return const_vec;
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else if ((target = neon_vdup_constant (vals)) != NULL_RTX)
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/* Loaded using VDUP. On Cortex-A8 the VDUP takes one NEON
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pipeline cycle; creating the constant takes one or two ARM
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pipeline cycles. */
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return target;
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else if (const_vec != NULL_RTX)
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/* Load from constant pool. On Cortex-A8 this takes two cycles
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(for either double or quad vectors). We can not take advantage
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of single-cycle VLD1 because we need a PC-relative addressing
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mode. */
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return const_vec;
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else
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/* A PARALLEL containing something not valid inside CONST_VECTOR.
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We can not construct an initializer. */
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return NULL_RTX;
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}
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/* Initialize vector TARGET to VALS. */
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void
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neon_expand_vector_init (rtx target, rtx vals)
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{
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enum machine_mode mode = GET_MODE (target);
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enum machine_mode inner = GET_MODE_INNER (mode);
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unsigned int i, n_elts = GET_MODE_NUNITS (mode);
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rtx mem;
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enum machine_mode inner_mode = GET_MODE_INNER (mode);
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int n_elts = GET_MODE_NUNITS (mode);
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int n_var = 0, one_var = -1;
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bool all_same = true;
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rtx x, mem;
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int i;
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gcc_assert (VECTOR_MODE_P (mode));
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for (i = 0; i < n_elts; ++i)
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{
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x = XVECEXP (vals, 0, i);
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if (!CONSTANT_P (x))
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++n_var, one_var = i;
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if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0)))
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all_same = false;
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}
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if (n_var == 0)
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{
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rtx constant = neon_make_constant (vals);
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if (constant != NULL_RTX)
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{
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emit_move_insn (target, constant);
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return;
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}
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}
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/* Splat a single non-constant element if we can. */
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if (all_same && GET_MODE_SIZE (inner_mode) <= 4)
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{
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x = copy_to_mode_reg (inner_mode, XVECEXP (vals, 0, 0));
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emit_insn (gen_rtx_SET (VOIDmode, target,
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gen_rtx_UNSPEC (mode, gen_rtvec (1, x),
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UNSPEC_VDUP_N)));
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return;
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}
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/* One field is non-constant. Load constant then overwrite varying
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field. This is more efficient than using the stack. */
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if (n_var == 1)
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{
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rtx copy = copy_rtx (vals);
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rtvec ops;
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/* Load constant part of vector, substitute neighboring value for
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varying element. */
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XVECEXP (copy, 0, one_var) = XVECEXP (vals, 0, (one_var + 1) % n_elts);
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neon_expand_vector_init (target, copy);
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/* Insert variable. */
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x = copy_to_mode_reg (inner_mode, XVECEXP (vals, 0, one_var));
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ops = gen_rtvec (3, x, target, GEN_INT (one_var));
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emit_insn (gen_rtx_SET (VOIDmode, target,
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gen_rtx_UNSPEC (mode, ops, UNSPEC_VSET_LANE)));
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return;
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}
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/* Construct the vector in memory one field at a time
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and load the whole vector. */
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mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), 0);
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for (i = 0; i < n_elts; i++)
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emit_move_insn (adjust_address_nv (mem, inner, i * GET_MODE_SIZE (inner)),
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XVECEXP (vals, 0, i));
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emit_move_insn (adjust_address_nv (mem, inner_mode,
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i * GET_MODE_SIZE (inner_mode)),
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XVECEXP (vals, 0, i));
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emit_move_insn (target, mem);
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}
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@ -15253,6 +15399,30 @@ arm_print_operand (FILE *stream, rtx x, int code)
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}
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return;
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/* Translate an S register number into a D register number and element index. */
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case 'y':
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{
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int mode = GET_MODE (x);
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int regno;
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if (GET_MODE_SIZE (mode) != 4 || GET_CODE (x) != REG)
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{
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output_operand_lossage ("invalid operand for code '%c'", code);
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return;
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}
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regno = REGNO (x);
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if (!VFP_REGNO_OK_FOR_SINGLE (regno))
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{
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output_operand_lossage ("invalid operand for code '%c'", code);
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return;
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}
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regno = regno - FIRST_VFP_REGNUM;
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fprintf (stream, "d%d[%d]", regno / 2, regno % 2);
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}
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return;
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/* Register specifier for vld1.16/vst1.16. Translate the S register
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number into a D register number and element index. */
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case 'z':
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@ -175,6 +175,7 @@ let rec analyze_shape shape =
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| Element_of_dreg -> (analyze_shape_elt Dreg) ^ "\\\\\\[\\[0-9\\]+\\\\\\]"
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| Element_of_qreg -> (analyze_shape_elt Qreg) ^ "\\\\\\[\\[0-9\\]+\\\\\\]"
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| All_elements_of_dreg -> (analyze_shape_elt Dreg) ^ "\\\\\\[\\\\\\]"
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| Alternatives (elts) -> "(" ^ (String.concat "|" (List.map analyze_shape_elt elts)) ^ ")"
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in
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match shape with
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All (n, elt) -> commas analyze_shape_elt (n_things n elt) ""
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@ -2687,9 +2687,9 @@
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})
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(define_insn "neon_vdup_n<mode>"
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[(set (match_operand:VDQW 0 "s_register_operand" "=w")
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(unspec:VDQW [(match_operand:<V_elem> 1 "s_register_operand" "r")]
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UNSPEC_VDUP_N))]
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[(set (match_operand:VX 0 "s_register_operand" "=w")
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(unspec:VX [(match_operand:<V_elem> 1 "s_register_operand" "r")]
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UNSPEC_VDUP_N))]
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"TARGET_NEON"
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"vdup%?.<V_sz_elem>\t%<V_reg>0, %1"
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;; Assume this schedules like vmov.
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@ -2697,6 +2697,19 @@
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(set_attr "neon_type" "neon_bp_simple")]
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)
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(define_insn "neon_vdup_n<mode>"
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[(set (match_operand:V32 0 "s_register_operand" "=w,w")
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(unspec:V32 [(match_operand:<V_elem> 1 "s_register_operand" "r,t")]
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UNSPEC_VDUP_N))]
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"TARGET_NEON"
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"@
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vdup%?.<V_sz_elem>\t%<V_reg>0, %1
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vdup%?.<V_sz_elem>\t%<V_reg>0, %y1"
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;; Assume this schedules like vmov.
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[(set_attr "predicable" "yes")
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(set_attr "neon_type" "neon_bp_simple")]
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)
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(define_insn "neon_vdup_ndi"
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[(set (match_operand:DI 0 "s_register_operand" "=w")
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(unspec:DI [(match_operand:DI 1 "s_register_operand" "r")]
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@ -68,6 +68,7 @@ type shape_elt = Dreg | Qreg | Corereg | Immed | VecArray of int * shape_elt
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| Element_of_dreg (* Used for "lane" variants. *)
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| Element_of_qreg (* Likewise. *)
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| All_elements_of_dreg (* Used for "dup" variants. *)
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| Alternatives of shape_elt list (* Used for multiple valid operands *)
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type shape_form = All of int * shape_elt
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| Long
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@ -1008,7 +1009,10 @@ let ops =
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pf_su_8_64;
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(* Set all lanes to the same value. *)
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Vdup_n, [],
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Vdup_n,
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[Disassembles_as [Use_operands [| Dreg;
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Alternatives [ Corereg;
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Element_of_dreg ] |]]],
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Use_operands [| Dreg; Corereg |], "vdup_n", bits_1,
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pf_su_8_32;
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Vdup_n,
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@ -1016,7 +1020,10 @@ let ops =
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Disassembles_as [Use_operands [| Dreg; Corereg; Corereg |]]],
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Use_operands [| Dreg; Corereg |], "vdup_n", notype_1,
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[S64; U64];
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Vdup_n, [],
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Vdup_n,
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[Disassembles_as [Use_operands [| Qreg;
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Alternatives [ Corereg;
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Element_of_dreg ] |]]],
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Use_operands [| Qreg; Corereg |], "vdupQ_n", bits_1,
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pf_su_8_32;
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Vdup_n,
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@ -1028,7 +1035,10 @@ let ops =
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(* These are just aliases for the above. *)
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Vmov_n,
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[Builtin_name "vdup_n"],
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[Builtin_name "vdup_n";
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Disassembles_as [Use_operands [| Dreg;
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Alternatives [ Corereg;
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Element_of_dreg ] |]]],
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Use_operands [| Dreg; Corereg |],
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"vmov_n", bits_1, pf_su_8_32;
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Vmov_n,
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@ -1038,7 +1048,10 @@ let ops =
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Use_operands [| Dreg; Corereg |],
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"vmov_n", notype_1, [S64; U64];
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Vmov_n,
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[Builtin_name "vdupQ_n"],
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[Builtin_name "vdupQ_n";
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Disassembles_as [Use_operands [| Qreg;
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Alternatives [ Corereg;
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Element_of_dreg ] |]]],
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Use_operands [| Qreg; Corereg |],
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"vmovQ_n", bits_1, pf_su_8_32;
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Vmov_n,
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|
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@ -42,6 +42,11 @@
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{
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if (GET_CODE (operands[0]) != REG)
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operands[1] = force_reg (<MODE>mode, operands[1]);
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else if (TARGET_NEON && CONSTANT_P (operands[1]))
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{
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operands[1] = neon_make_constant (operands[1]);
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gcc_assert (operands[1] != NULL_RTX);
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}
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}
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})
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|
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@ -1,3 +1,7 @@
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2009-11-11 Daniel Jacobowitz <dan@codesourcery.com>
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* gcc.target/arm/neon: Regenerate generated tests.
|
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|
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2009-11-10 Jason Merrill <jason@redhat.com>
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* g++.dg/init/placement5.C: New.
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@ -15,5 +15,5 @@ void test_vdupQ_nf32 (void)
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out_float32x4_t = vdupq_n_f32 (arg0_float32_t);
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}
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/* { dg-final { scan-assembler "vdup\.32\[ \]+\[qQ\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
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/* { dg-final { scan-assembler "vdup\.32\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
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/* { dg-final { cleanup-saved-temps } } */
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@ -15,5 +15,5 @@ void test_vdupQ_np16 (void)
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out_poly16x8_t = vdupq_n_p16 (arg0_poly16_t);
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}
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/* { dg-final { scan-assembler "vdup\.16\[ \]+\[qQ\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
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/* { dg-final { scan-assembler "vdup\.16\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
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/* { dg-final { cleanup-saved-temps } } */
|
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|
|
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@ -15,5 +15,5 @@ void test_vdupQ_np8 (void)
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out_poly8x16_t = vdupq_n_p8 (arg0_poly8_t);
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}
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|
||||
/* { dg-final { scan-assembler "vdup\.8\[ \]+\[qQ\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
/* { dg-final { scan-assembler "vdup\.8\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
/* { dg-final { cleanup-saved-temps } } */
|
||||
|
|
|
|||
|
|
@ -15,5 +15,5 @@ void test_vdupQ_ns16 (void)
|
|||
out_int16x8_t = vdupq_n_s16 (arg0_int16_t);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vdup\.16\[ \]+\[qQ\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
/* { dg-final { scan-assembler "vdup\.16\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
/* { dg-final { cleanup-saved-temps } } */
|
||||
|
|
|
|||
|
|
@ -15,5 +15,5 @@ void test_vdupQ_ns32 (void)
|
|||
out_int32x4_t = vdupq_n_s32 (arg0_int32_t);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vdup\.32\[ \]+\[qQ\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
/* { dg-final { scan-assembler "vdup\.32\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
/* { dg-final { cleanup-saved-temps } } */
|
||||
|
|
|
|||
|
|
@ -15,5 +15,5 @@ void test_vdupQ_ns8 (void)
|
|||
out_int8x16_t = vdupq_n_s8 (arg0_int8_t);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vdup\.8\[ \]+\[qQ\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
/* { dg-final { scan-assembler "vdup\.8\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
/* { dg-final { cleanup-saved-temps } } */
|
||||
|
|
|
|||
|
|
@ -15,5 +15,5 @@ void test_vdupQ_nu16 (void)
|
|||
out_uint16x8_t = vdupq_n_u16 (arg0_uint16_t);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vdup\.16\[ \]+\[qQ\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
/* { dg-final { scan-assembler "vdup\.16\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
/* { dg-final { cleanup-saved-temps } } */
|
||||
|
|
|
|||
|
|
@ -15,5 +15,5 @@ void test_vdupQ_nu32 (void)
|
|||
out_uint32x4_t = vdupq_n_u32 (arg0_uint32_t);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vdup\.32\[ \]+\[qQ\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
/* { dg-final { scan-assembler "vdup\.32\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
/* { dg-final { cleanup-saved-temps } } */
|
||||
|
|
|
|||
|
|
@ -15,5 +15,5 @@ void test_vdupQ_nu8 (void)
|
|||
out_uint8x16_t = vdupq_n_u8 (arg0_uint8_t);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vdup\.8\[ \]+\[qQ\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
/* { dg-final { scan-assembler "vdup\.8\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
/* { dg-final { cleanup-saved-temps } } */
|
||||
|
|
|
|||
|
|
@ -15,5 +15,5 @@ void test_vdup_nf32 (void)
|
|||
out_float32x2_t = vdup_n_f32 (arg0_float32_t);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vdup\.32\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
/* { dg-final { scan-assembler "vdup\.32\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
/* { dg-final { cleanup-saved-temps } } */
|
||||
|
|
|
|||
|
|
@ -15,5 +15,5 @@ void test_vdup_np16 (void)
|
|||
out_poly16x4_t = vdup_n_p16 (arg0_poly16_t);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vdup\.16\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
/* { dg-final { scan-assembler "vdup\.16\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
/* { dg-final { cleanup-saved-temps } } */
|
||||
|
|
|
|||
|
|
@ -15,5 +15,5 @@ void test_vdup_np8 (void)
|
|||
out_poly8x8_t = vdup_n_p8 (arg0_poly8_t);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vdup\.8\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
/* { dg-final { scan-assembler "vdup\.8\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
/* { dg-final { cleanup-saved-temps } } */
|
||||
|
|
|
|||
|
|
@ -15,5 +15,5 @@ void test_vdup_ns16 (void)
|
|||
out_int16x4_t = vdup_n_s16 (arg0_int16_t);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vdup\.16\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
/* { dg-final { scan-assembler "vdup\.16\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
/* { dg-final { cleanup-saved-temps } } */
|
||||
|
|
|
|||
|
|
@ -15,5 +15,5 @@ void test_vdup_ns32 (void)
|
|||
out_int32x2_t = vdup_n_s32 (arg0_int32_t);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vdup\.32\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
/* { dg-final { scan-assembler "vdup\.32\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
/* { dg-final { cleanup-saved-temps } } */
|
||||
|
|
|
|||
|
|
@ -15,5 +15,5 @@ void test_vdup_ns8 (void)
|
|||
out_int8x8_t = vdup_n_s8 (arg0_int8_t);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vdup\.8\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
/* { dg-final { scan-assembler "vdup\.8\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
/* { dg-final { cleanup-saved-temps } } */
|
||||
|
|
|
|||
|
|
@ -15,5 +15,5 @@ void test_vdup_nu16 (void)
|
|||
out_uint16x4_t = vdup_n_u16 (arg0_uint16_t);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vdup\.16\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
/* { dg-final { scan-assembler "vdup\.16\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
/* { dg-final { cleanup-saved-temps } } */
|
||||
|
|
|
|||
|
|
@ -15,5 +15,5 @@ void test_vdup_nu32 (void)
|
|||
out_uint32x2_t = vdup_n_u32 (arg0_uint32_t);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vdup\.32\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
/* { dg-final { scan-assembler "vdup\.32\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
/* { dg-final { cleanup-saved-temps } } */
|
||||
|
|
|
|||
|
|
@ -15,5 +15,5 @@ void test_vdup_nu8 (void)
|
|||
out_uint8x8_t = vdup_n_u8 (arg0_uint8_t);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vdup\.8\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
/* { dg-final { scan-assembler "vdup\.8\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
/* { dg-final { cleanup-saved-temps } } */
|
||||
|
|
|
|||
|
|
@ -15,5 +15,5 @@ void test_vmovQ_nf32 (void)
|
|||
out_float32x4_t = vmovq_n_f32 (arg0_float32_t);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vdup\.32\[ \]+\[qQ\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
/* { dg-final { scan-assembler "vdup\.32\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
/* { dg-final { cleanup-saved-temps } } */
|
||||
|
|
|
|||
|
|
@ -15,5 +15,5 @@ void test_vmovQ_np16 (void)
|
|||
out_poly16x8_t = vmovq_n_p16 (arg0_poly16_t);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vdup\.16\[ \]+\[qQ\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
/* { dg-final { scan-assembler "vdup\.16\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
/* { dg-final { cleanup-saved-temps } } */
|
||||
|
|
|
|||
|
|
@ -15,5 +15,5 @@ void test_vmovQ_np8 (void)
|
|||
out_poly8x16_t = vmovq_n_p8 (arg0_poly8_t);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vdup\.8\[ \]+\[qQ\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
/* { dg-final { scan-assembler "vdup\.8\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
/* { dg-final { cleanup-saved-temps } } */
|
||||
|
|
|
|||
|
|
@ -15,5 +15,5 @@ void test_vmovQ_ns16 (void)
|
|||
out_int16x8_t = vmovq_n_s16 (arg0_int16_t);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vdup\.16\[ \]+\[qQ\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
/* { dg-final { scan-assembler "vdup\.16\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
/* { dg-final { cleanup-saved-temps } } */
|
||||
|
|
|
|||
|
|
@ -15,5 +15,5 @@ void test_vmovQ_ns32 (void)
|
|||
out_int32x4_t = vmovq_n_s32 (arg0_int32_t);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vdup\.32\[ \]+\[qQ\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
/* { dg-final { scan-assembler "vdup\.32\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
/* { dg-final { cleanup-saved-temps } } */
|
||||
|
|
|
|||
|
|
@ -15,5 +15,5 @@ void test_vmovQ_ns8 (void)
|
|||
out_int8x16_t = vmovq_n_s8 (arg0_int8_t);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vdup\.8\[ \]+\[qQ\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
/* { dg-final { scan-assembler "vdup\.8\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
/* { dg-final { cleanup-saved-temps } } */
|
||||
|
|
|
|||
|
|
@ -15,5 +15,5 @@ void test_vmovQ_nu16 (void)
|
|||
out_uint16x8_t = vmovq_n_u16 (arg0_uint16_t);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vdup\.16\[ \]+\[qQ\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
/* { dg-final { scan-assembler "vdup\.16\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
/* { dg-final { cleanup-saved-temps } } */
|
||||
|
|
|
|||
|
|
@ -15,5 +15,5 @@ void test_vmovQ_nu32 (void)
|
|||
out_uint32x4_t = vmovq_n_u32 (arg0_uint32_t);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vdup\.32\[ \]+\[qQ\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
/* { dg-final { scan-assembler "vdup\.32\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
/* { dg-final { cleanup-saved-temps } } */
|
||||
|
|
|
|||
|
|
@ -15,5 +15,5 @@ void test_vmovQ_nu8 (void)
|
|||
out_uint8x16_t = vmovq_n_u8 (arg0_uint8_t);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vdup\.8\[ \]+\[qQ\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
/* { dg-final { scan-assembler "vdup\.8\[ \]+\[qQ\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
/* { dg-final { cleanup-saved-temps } } */
|
||||
|
|
|
|||
|
|
@ -15,5 +15,5 @@ void test_vmov_nf32 (void)
|
|||
out_float32x2_t = vmov_n_f32 (arg0_float32_t);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vdup\.32\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
/* { dg-final { scan-assembler "vdup\.32\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
/* { dg-final { cleanup-saved-temps } } */
|
||||
|
|
|
|||
|
|
@ -15,5 +15,5 @@ void test_vmov_np16 (void)
|
|||
out_poly16x4_t = vmov_n_p16 (arg0_poly16_t);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vdup\.16\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
/* { dg-final { scan-assembler "vdup\.16\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
/* { dg-final { cleanup-saved-temps } } */
|
||||
|
|
|
|||
|
|
@ -15,5 +15,5 @@ void test_vmov_np8 (void)
|
|||
out_poly8x8_t = vmov_n_p8 (arg0_poly8_t);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vdup\.8\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
/* { dg-final { scan-assembler "vdup\.8\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
/* { dg-final { cleanup-saved-temps } } */
|
||||
|
|
|
|||
|
|
@ -15,5 +15,5 @@ void test_vmov_ns16 (void)
|
|||
out_int16x4_t = vmov_n_s16 (arg0_int16_t);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vdup\.16\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
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/* { dg-final { scan-assembler "vdup\.16\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
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/* { dg-final { cleanup-saved-temps } } */
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|
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|||
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|
@ -15,5 +15,5 @@ void test_vmov_ns32 (void)
|
|||
out_int32x2_t = vmov_n_s32 (arg0_int32_t);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vdup\.32\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
/* { dg-final { scan-assembler "vdup\.32\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
/* { dg-final { cleanup-saved-temps } } */
|
||||
|
|
|
|||
|
|
@ -15,5 +15,5 @@ void test_vmov_ns8 (void)
|
|||
out_int8x8_t = vmov_n_s8 (arg0_int8_t);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vdup\.8\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
/* { dg-final { scan-assembler "vdup\.8\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
/* { dg-final { cleanup-saved-temps } } */
|
||||
|
|
|
|||
|
|
@ -15,5 +15,5 @@ void test_vmov_nu16 (void)
|
|||
out_uint16x4_t = vmov_n_u16 (arg0_uint16_t);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vdup\.16\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
/* { dg-final { scan-assembler "vdup\.16\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
/* { dg-final { cleanup-saved-temps } } */
|
||||
|
|
|
|||
|
|
@ -15,5 +15,5 @@ void test_vmov_nu32 (void)
|
|||
out_uint32x2_t = vmov_n_u32 (arg0_uint32_t);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vdup\.32\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
/* { dg-final { scan-assembler "vdup\.32\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
/* { dg-final { cleanup-saved-temps } } */
|
||||
|
|
|
|||
|
|
@ -15,5 +15,5 @@ void test_vmov_nu8 (void)
|
|||
out_uint8x8_t = vmov_n_u8 (arg0_uint8_t);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "vdup\.8\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
/* { dg-final { scan-assembler "vdup\.8\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
|
||||
/* { dg-final { cleanup-saved-temps } } */
|
||||
|
|
|
|||
Loading…
Reference in New Issue