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[arm] Add support for Neoverse N1

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This patch adds support for the Neoverse N1 [1]. This CPU was previously supported through the Ares codename.
-mcpu=ares is retained as an alias of the new -mcpu=neoverse-n1.

Bootstrapped and tested on arm-none-linux-gnueabihf. 

	* config/arm/arm-cpus.in (ares): Rename to...
	(neoverse-n1): ... This.  Add ares as alias.
	* config/arm/arm-tables.opt: Regenerate.
	* config/arm/arm-tune.md: Likewise.
	* doc/invoke.txt (ARM Options): Document neoverse-n1.

From-SVN: r269101
This commit is contained in:
Kyrylo Tkachov 2019-02-22 08:59:20 +00:00 committed by Kyrylo Tkachov
parent 3f23539cff
commit 81a5f36d66
5 changed files with 17 additions and 8 deletions
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8
gcc/ChangeLog
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@ -1,3 +1,11 @@
2019-02-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/arm/arm-cpus.in (ares): Rename to...
(neoverse-n1): ... This. Add ares as alias.
* config/arm/arm-tables.opt: Regenerate.
* config/arm/arm-tune.md: Likewise.
* doc/invoke.txt (ARM Options): Document neoverse-n1.
2019-02-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/aarch64/aarch64-cores.def (neoverse-e1): Define.

7
gcc/config/arm/arm-cpus.in
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@ -1331,8 +1331,9 @@ begin cpu cortex-a76
part d0b
end cpu cortex-a76
begin cpu ares
cname ares
begin cpu neoverse-n1
cname neoversen1
alias !ares
tune for cortex-a57
tune flags LDSCHED
architecture armv8.2-a+fp16+dotprod+simd
@ -1340,7 +1341,7 @@ begin cpu ares
costs cortex_a57
vendor 41
part d0c
end cpu ares
end cpu neoverse-n1
# ARMv8.2 A-profile ARM DynamIQ big.LITTLE implementations
begin cpu cortex-a75.cortex-a55

2
gcc/config/arm/arm-tables.opt
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@ -235,7 +235,7 @@ EnumValue
Enum(processor_type) String(cortex-a76) Value( TARGET_CPU_cortexa76)
EnumValue
Enum(processor_type) String(ares) Value( TARGET_CPU_ares)
Enum(processor_type) String(neoverse-n1) Value( TARGET_CPU_neoversen1)
EnumValue
Enum(processor_type) String(cortex-a75.cortex-a55) Value( TARGET_CPU_cortexa75cortexa55)

2
gcc/config/arm/arm-tune.md
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@ -44,7 +44,7 @@
cortexa73,exynosm1,xgene1,
cortexa57cortexa53,cortexa72cortexa53,cortexa73cortexa35,
cortexa73cortexa53,cortexa55,cortexa75,
cortexa76,ares,cortexa75cortexa55,
cortexa76,neoversen1,cortexa75cortexa55,
cortexa76cortexa55,cortexm23,cortexm33,
cortexr52"
(const (symbol_ref "((enum attr_tune) arm_tune)")))

6
gcc/doc/invoke.texi
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@ -17475,9 +17475,9 @@ Permissible names are: @samp{arm7tdmi}, @samp{arm7tdmi-s}, @samp{arm710t},
@samp{cortex-m4}, @samp{cortex-m7}, @samp{cortex-m23}, @samp{cortex-m33},
@samp{cortex-m1.small-multiply}, @samp{cortex-m0.small-multiply},
@samp{cortex-m0plus.small-multiply}, @samp{exynos-m1}, @samp{marvell-pj4},
@samp{xscale}, @samp{iwmmxt}, @samp{iwmmxt2}, @samp{ep9312}, @samp{fa526},
@samp{fa626}, @samp{fa606te}, @samp{fa626te}, @samp{fmp626}, @samp{fa726te},
@samp{xgene1}.
@samp{neoverse-n1}, @samp{xscale}, @samp{iwmmxt}, @samp{iwmmxt2},
@samp{ep9312}, @samp{fa526}, @samp{fa626}, @samp{fa606te}, @samp{fa626te},
@samp{fmp626}, @samp{fa726te}, @samp{xgene1}.
Additionally, this option can specify that GCC should tune the performance
of the code for a big.LITTLE system. Permissible names are: