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re PR target/52568 (suboptimal __builtin_shuffle on cycles with AVX)

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PR target/52568
	* config/i386/i386.c (expand_vec_perm_vperm2f128_vblend): New
	function.
	(ix86_expand_vec_perm_const_1): Use it.

	* gcc.dg/torture/vshuf-4.inc: Add two new tests.
	* gcc.dg/torture/vshuf-8.inc: Likewise.
	* gcc.dg/torture/vshuf-16.inc: Likewise.
	* gcc.dg/torture/vshuf-32.inc: Likewise.

From-SVN: r185447
This commit is contained in:
Jakub Jelinek 2012-03-16 00:46:34 +01:00 committed by Jakub Jelinek
parent b82277395e
commit 81de8b03e0
7 changed files with 95 additions and 4 deletions
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5
gcc/ChangeLog
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@ -1,5 +1,10 @@
2012-03-15 Jakub Jelinek <jakub@redhat.com>
PR target/52568
* config/i386/i386.c (expand_vec_perm_vperm2f128_vblend): New
function.
(ix86_expand_vec_perm_const_1): Use it.
PR target/52568
* config/i386/sse.md (UNSPEC_VPERMDF): Remove.
(avx2_permv4df): Remove.

70
gcc/config/i386/i386.c
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@ -36638,6 +36638,73 @@ expand_vec_perm_interleave3 (struct expand_vec_perm_d *d)
return true;
}
/* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement
a single vector permutation using a single intra-lane vector
permutation, vperm2f128 swapping the lanes and vblend* insn blending
the non-swapped and swapped vectors together. */
static bool
expand_vec_perm_vperm2f128_vblend (struct expand_vec_perm_d *d)
{
struct expand_vec_perm_d dfirst, dsecond;
unsigned i, j, msk, nelt = d->nelt, nelt2 = nelt / 2;
rtx seq;
bool ok;
rtx (*blend) (rtx, rtx, rtx, rtx) = NULL;
if (!TARGET_AVX
|| TARGET_AVX2
|| (d->vmode != V8SFmode && d->vmode != V4DFmode)
|| d->op0 != d->op1)
return false;
dfirst = *d;
for (i = 0; i < nelt; i++)
dfirst.perm[i] = 0xff;
for (i = 0, msk = 0; i < nelt; i++)
{
j = (d->perm[i] & nelt2) ? i | nelt2 : i & ~nelt2;
if (dfirst.perm[j] != 0xff && dfirst.perm[j] != d->perm[i])
return false;
dfirst.perm[j] = d->perm[i];
if (j != i)
msk |= (1 << i);
}
for (i = 0; i < nelt; i++)
if (dfirst.perm[i] == 0xff)
dfirst.perm[i] = i;
if (!d->testing_p)
dfirst.target = gen_reg_rtx (dfirst.vmode);
start_sequence ();
ok = expand_vec_perm_1 (&dfirst);
seq = get_insns ();
end_sequence ();
if (!ok)
return false;
if (d->testing_p)
return true;
emit_insn (seq);
dsecond = *d;
dsecond.op0 = dfirst.target;
dsecond.op1 = dfirst.target;
dsecond.target = gen_reg_rtx (dsecond.vmode);
for (i = 0; i < nelt; i++)
dsecond.perm[i] = i ^ nelt2;
ok = expand_vec_perm_1 (&dsecond);
gcc_assert (ok);
blend = d->vmode == V8SFmode ? gen_avx_blendps256 : gen_avx_blendpd256;
emit_insn (blend (d->target, dfirst.target, dsecond.target, GEN_INT (msk)));
return true;
}
/* A subroutine of expand_vec_perm_even_odd_1. Implement the double-word
permutation with two pshufb insns and an ior. We should have already
failed all two instruction sequences. */
@ -37289,6 +37356,9 @@ ix86_expand_vec_perm_const_1 (struct expand_vec_perm_d *d)
if (expand_vec_perm_interleave3 (d))
return true;
if (expand_vec_perm_vperm2f128_vblend (d))
return true;
/* Try sequences of four instructions. */
if (expand_vec_perm_vpshufb2_vpermq (d))

8
gcc/testsuite/ChangeLog
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@ -1,3 +1,11 @@
2012-03-15 Jakub Jelinek <jakub@redhat.com>
PR target/52568
* gcc.dg/torture/vshuf-4.inc: Add two new tests.
* gcc.dg/torture/vshuf-8.inc: Likewise.
* gcc.dg/torture/vshuf-16.inc: Likewise.
* gcc.dg/torture/vshuf-32.inc: Likewise.
2012-03-15 Jason Merrill <jason@redhat.com>
* g++.dg/torture/pr52582.C: New.

4
gcc/testsuite/gcc.dg/torture/vshuf-16.inc
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@ -21,7 +21,9 @@ T (17, 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31) \
T (18, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) \
T (19, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0) \
T (20, 0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23) \
T (21, 8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31)
T (21, 8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31) \
T (22, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 0) \
T (23, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0, 15)
#define EXPTESTS \
T (116, 28, 13, 27, 11, 21, 1, 5, 22, 29, 14, 15, 6, 3, 10, 16, 30) \
T (117, 22, 26, 1, 13, 29, 3, 18, 18, 11, 21, 12, 28, 19, 5, 7, 4) \

4
gcc/testsuite/gcc.dg/torture/vshuf-32.inc
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@ -21,7 +21,9 @@ T (17, 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31, 33, 35, 37, 39
T (18, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) \
T (19, 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0) \
T (20, 0, 32, 1, 33, 2, 34, 3, 35, 4, 36, 5, 37, 6, 38, 7, 39, 8, 40, 9, 41, 10, 42, 11, 43, 12, 44, 13, 45, 14, 46, 15, 47) \
T (21, 16, 48, 17, 49, 18, 50, 19, 51, 20, 52, 21, 53, 22, 54, 23, 55, 24, 56, 25, 57, 26, 58, 27, 59, 28, 60, 29, 61, 30, 62, 31, 63)
T (21, 16, 48, 17, 49, 18, 50, 19, 51, 20, 52, 21, 53, 22, 54, 23, 55, 24, 56, 25, 57, 26, 58, 27, 59, 28, 60, 29, 61, 30, 62, 31, 63) \
T (22, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 0) \
T (23, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0, 31)
#define EXPTESTS \
T (116, 13, 38, 47, 3, 17, 8, 38, 20, 59, 61, 39, 26, 7, 49, 63, 43, 57, 16, 40, 19, 4, 32, 27, 7, 52, 19, 46, 55, 36, 41, 48, 6) \
T (117, 39, 35, 59, 20, 56, 18, 58, 63, 57, 14, 2, 16, 5, 61, 35, 4, 53, 9, 52, 51, 27, 33, 61, 12, 3, 35, 36, 40, 37, 7, 45, 42) \

4
gcc/testsuite/gcc.dg/torture/vshuf-4.inc
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@ -21,7 +21,9 @@ T (17, 1, 3, 5, 7) \
T (18, 3, 3, 3, 3) \
T (19, 3, 2, 1, 0) \
T (20, 0, 4, 1, 5) \
T (21, 2, 6, 3, 7)
T (21, 2, 6, 3, 7) \
T (22, 1, 2, 3, 0) \
T (23, 2, 1, 0, 3)
#define EXPTESTS \
T (116, 1, 2, 4, 3) \
T (117, 7, 3, 3, 0) \

4
gcc/testsuite/gcc.dg/torture/vshuf-8.inc
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@ -21,7 +21,9 @@ T (17, 1, 3, 5, 7, 9, 11, 13, 15) \
T (18, 3, 3, 3, 3, 3, 3, 3, 3) \
T (19, 7, 6, 5, 4, 3, 2, 1, 0) \
T (20, 0, 8, 1, 9, 2, 10, 3, 11) \
T (21, 4, 12, 5, 13, 6, 14, 7, 15)
T (21, 4, 12, 5, 13, 6, 14, 7, 15) \
T (22, 1, 2, 3, 4, 5, 6, 7, 0) \
T (23, 6, 5, 4, 3, 2, 1, 0, 7)
#define EXPTESTS \
T (116, 9, 3, 9, 4, 7, 0, 0, 6) \
T (117, 4, 14, 12, 8, 9, 6, 0, 10) \