re PR target/7693 (Typo in i386 mmintrin.h header)
* mmintrin.h (__m64): typedef it to v2si. (_mm_cvtsi32_si64, _mm_cvtsi32_si64_mm_sll_pi16, _mm_sll_pi32, _mm_sll_pi64, _mm_slli_pi64, _mm_sra_pi16, _mm_sra_pi32, _mm_srl_pi16, _mm_srl_pi32, _mm_srl_pi64, _mm_srli_pi64, _mm_and_si64, _mm_andnot_si64, _mm_or_si64, _mm_xor_si64): Add neccesary casts. * xmmintrin.h (_mm_setzero_si64): Likewise. * i386.h (ALIGN_MODE_128): Update comment; add missing modes (SSE_REG_MODE_P, MMX_REG_MODE_P): New macros. PR target/7693 Patch by Shawn Wagner * mmintrin.h: Replace pi64 by si64. From-SVN: r58306
This commit is contained in:
Jan Hubicka
Jan Hubicka
parent
bf3d8f27d5
commit
822eda1260
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@ -1,3 +1,20 @@
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Sat Oct 19 10:46:52 CEST 2002 Jan Hubicka <jh@suse.cz>
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* mmintrin.h (__m64): typedef it to v2si.
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(_mm_cvtsi32_si64, _mm_cvtsi32_si64_mm_sll_pi16,
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_mm_sll_pi32, _mm_sll_pi64, _mm_slli_pi64, _mm_sra_pi16,
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_mm_sra_pi32, _mm_srl_pi16, _mm_srl_pi32, _mm_srl_pi64,
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_mm_srli_pi64, _mm_and_si64, _mm_andnot_si64,
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_mm_or_si64, _mm_xor_si64): Add neccesary casts.
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* xmmintrin.h (_mm_setzero_si64): Likewise.
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* i386.h (ALIGN_MODE_128): Update comment; add missing modes
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(SSE_REG_MODE_P, MMX_REG_MODE_P): New macros.
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PR target/7693
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Patch by Shawn Wagner
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* mmintrin.h: Replace pi64 by si64.
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2002-10-18 David Edelsohn <edelsohn@gnu.org>
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* rs6000.md (movdf_hardfloat32): Order alternatives consistently.
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@ -730,10 +730,9 @@ extern int x86_prefetch_sse;
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#define BIGGEST_ALIGNMENT 128
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/* Decide whether a variable of mode MODE must be 128 bit aligned. */
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/* Decide whether a variable of mode MODE should be 128 bit aligned. */
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#define ALIGN_MODE_128(MODE) \
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((MODE) == XFmode || (MODE) == TFmode || ((MODE) == TImode) \
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|| (MODE) == V4SFmode || (MODE) == V4SImode)
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((MODE) == XFmode || (MODE) == TFmode || SSE_REG_MODE_P (MODE))
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/* The published ABIs say that doubles should be aligned on word
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boundaries, so lower the aligment for structure fields unless
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@ -1007,6 +1006,17 @@ do { \
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|| (MODE) == CDImode \
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|| (TARGET_64BIT && ((MODE) == TImode || (MODE) == CTImode)))
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/* Return true for modes passed in SSE registers. */
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#define SSE_REG_MODE_P(MODE) \
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((MODE) == TImode || (MODE) == V16QImode \
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|| (MODE) == V8HImode || (MODE) == V2DFmode || (MODE) == V2DImode \
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|| (MODE) == V4SFmode || (MODE) == V4SImode)
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/* Return true for modes passed in MMX registers. */
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#define MMX_REG_MODE_P(MODE) \
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((MODE) == V8QImode || (MODE) == V4HImode || (MODE) == V2SImode \
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|| (MODE) == V2SFmode)
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/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */
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#define HARD_REGNO_MODE_OK(REGNO, MODE) \
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@ -34,7 +34,7 @@
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# error "MMX instruction set not enabled"
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#else
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/* The data type intended for user use. */
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typedef unsigned long long __m64 __attribute__ ((__aligned__ (8)));
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typedef int __m64 __attribute__ ((__mode__ (__V2SI__)));
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/* Internal data types for implementing the intrinsics. */
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typedef int __v2si __attribute__ ((__mode__ (__V2SI__)));
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@ -52,14 +52,16 @@ _mm_empty (void)
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static __inline __m64
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_mm_cvtsi32_si64 (int __i)
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{
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return (unsigned int) __i;
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long long __tmp = (unsigned int)__i;
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return (__m64) __tmp;
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}
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/* Convert the lower 32 bits of the __m64 object into an integer. */
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static __inline int
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_mm_cvtsi64_si32 (__m64 __i)
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{
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return __i;
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long long __tmp = (long long)__i;
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return __tmp;
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}
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/* Pack the four 16-bit values from M1 into the lower four 8-bit values of
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@ -272,7 +274,7 @@ _mm_mullo_pi16 (__m64 __m1, __m64 __m2)
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static __inline __m64
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_mm_sll_pi16 (__m64 __m, __m64 __count)
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{
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return (__m64) __builtin_ia32_psllw ((__v4hi)__m, __count);
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return (__m64) __builtin_ia32_psllw ((__v4hi)__m, (long long)__count);
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}
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static __inline __m64
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@ -285,7 +287,7 @@ _mm_slli_pi16 (__m64 __m, int __count)
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static __inline __m64
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_mm_sll_pi32 (__m64 __m, __m64 __count)
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{
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return (__m64) __builtin_ia32_pslld ((__v2si)__m, __count);
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return (__m64) __builtin_ia32_pslld ((__v2si)__m, (long long)__count);
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}
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static __inline __m64
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@ -296,22 +298,22 @@ _mm_slli_pi32 (__m64 __m, int __count)
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/* Shift the 64-bit value in M left by COUNT. */
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static __inline __m64
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_mm_sll_pi64 (__m64 __m, __m64 __count)
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_mm_sll_si64 (__m64 __m, __m64 __count)
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{
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return (__m64) __builtin_ia32_psllq (__m, __count);
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return (__m64) __builtin_ia32_psllq ((long long)__m, (long long)__count);
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}
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static __inline __m64
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_mm_slli_pi64 (__m64 __m, int __count)
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_mm_slli_si64 (__m64 __m, int __count)
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{
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return (__m64) __builtin_ia32_psllq (__m, __count);
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return (__m64) __builtin_ia32_psllq ((long long)__m, (long long)__count);
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}
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/* Shift four 16-bit values in M right by COUNT; shift in the sign bit. */
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static __inline __m64
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_mm_sra_pi16 (__m64 __m, __m64 __count)
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{
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return (__m64) __builtin_ia32_psraw ((__v4hi)__m, __count);
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return (__m64) __builtin_ia32_psraw ((__v4hi)__m, (long long)__count);
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}
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static __inline __m64
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@ -324,7 +326,7 @@ _mm_srai_pi16 (__m64 __m, int __count)
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static __inline __m64
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_mm_sra_pi32 (__m64 __m, __m64 __count)
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{
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return (__m64) __builtin_ia32_psrad ((__v2si)__m, __count);
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return (__m64) __builtin_ia32_psrad ((__v2si)__m, (long long)__count);
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}
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static __inline __m64
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@ -337,7 +339,7 @@ _mm_srai_pi32 (__m64 __m, int __count)
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static __inline __m64
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_mm_srl_pi16 (__m64 __m, __m64 __count)
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{
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return (__m64) __builtin_ia32_psrlw ((__v4hi)__m, __count);
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return (__m64) __builtin_ia32_psrlw ((__v4hi)__m, (long long)__count);
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}
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static __inline __m64
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@ -350,7 +352,7 @@ _mm_srli_pi16 (__m64 __m, int __count)
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static __inline __m64
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_mm_srl_pi32 (__m64 __m, __m64 __count)
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{
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return (__m64) __builtin_ia32_psrld ((__v2si)__m, __count);
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return (__m64) __builtin_ia32_psrld ((__v2si)__m, (long long)__count);
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}
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static __inline __m64
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@ -361,22 +363,22 @@ _mm_srli_pi32 (__m64 __m, int __count)
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/* Shift the 64-bit value in M left by COUNT; shift in zeros. */
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static __inline __m64
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_mm_srl_pi64 (__m64 __m, __m64 __count)
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_mm_srl_si64 (__m64 __m, __m64 __count)
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{
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return (__m64) __builtin_ia32_psrlq (__m, __count);
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return (__m64) __builtin_ia32_psrlq ((long long)__m, (long long)__count);
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}
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static __inline __m64
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_mm_srli_pi64 (__m64 __m, int __count)
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_mm_srli_si64 (__m64 __m, int __count)
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{
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return (__m64) __builtin_ia32_psrlq (__m, __count);
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return (__m64) __builtin_ia32_psrlq ((long long)__m, (long long)__count);
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}
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/* Bit-wise AND the 64-bit values in M1 and M2. */
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static __inline __m64
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_mm_and_si64 (__m64 __m1, __m64 __m2)
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{
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return __builtin_ia32_pand (__m1, __m2);
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return (__m64) __builtin_ia32_pand ((long long)__m1, (long long)__m2);
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}
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/* Bit-wise complement the 64-bit value in M1 and bit-wise AND it with the
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@ -384,21 +386,21 @@ _mm_and_si64 (__m64 __m1, __m64 __m2)
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static __inline __m64
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_mm_andnot_si64 (__m64 __m1, __m64 __m2)
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{
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return __builtin_ia32_pandn (__m1, __m2);
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return (__m64) __builtin_ia32_pandn ((long long)__m1, (long long)__m2);
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}
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/* Bit-wise inclusive OR the 64-bit values in M1 and M2. */
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static __inline __m64
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_mm_or_si64 (__m64 __m1, __m64 __m2)
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{
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return __builtin_ia32_por (__m1, __m2);
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return (__m64)__builtin_ia32_por ((long long)__m1, (long long)__m2);
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}
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/* Bit-wise exclusive OR the 64-bit values in M1 and M2. */
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static __inline __m64
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_mm_xor_si64 (__m64 __m1, __m64 __m2)
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{
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return __builtin_ia32_pxor (__m1, __m2);
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return (__m64)__builtin_ia32_pxor ((long long)__m1, (long long)__m2);
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}
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/* Compare eight 8-bit values. The result of the comparison is 0xFF if the
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@ -447,7 +449,7 @@ _mm_cmpgt_pi32 (__m64 __m1, __m64 __m2)
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static __inline __m64
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_mm_setzero_si64 (void)
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{
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return __builtin_ia32_mmx_zero ();
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return (__m64)__builtin_ia32_mmx_zero ();
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}
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/* Creates a vector of two 32-bit values; I0 is least significant. */
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