re PR target/63724 ([AArch64] Inefficient immediate expansion and hoisting.)
Fix PR target/63724
2014-11-14 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
PR target/63724
* config/aarch64/aarch64.c (aarch64_expand_mov_immediate): Split out
numerical immediate handling to...
(aarch64_internal_mov_immediate): ...this. New.
(aarch64_rtx_costs): Use aarch64_internal_mov_immediate.
(aarch64_mov_operand_p): Relax predicate.
* config/aarch64/aarch64.md (mov<mode>:GPI): Do not expand CONST_INTs.
(*movsi_aarch64): Turn into define_insn_and_split and new alternative
for 'n'.
(*movdi_aarch64): Likewise.
From-SVN: r217546
This commit is contained in:
Ramana Radhakrishnan
Ramana Radhakrishnan
parent
a7f24614b3
commit
8261494856
@ -1,3 +1,16 @@
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2014-11-14 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
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PR target/63724
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* config/aarch64/aarch64.c (aarch64_expand_mov_immediate): Split out
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numerical immediate handling to...
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(aarch64_internal_mov_immediate): ...this. New.
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(aarch64_rtx_costs): Use aarch64_internal_mov_immediate.
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(aarch64_mov_operand_p): Relax predicate.
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* config/aarch64/aarch64.md (mov<mode>:GPI): Do not expand CONST_INTs.
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(*movsi_aarch64): Turn into define_insn_and_split and new alternative
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for 'n'.
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(*movdi_aarch64): Likewise.
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2014-11-14 Richard Biener <rguenther@suse.de>
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* match.pd: Implement more binary patterns exercised by
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@ -1046,10 +1046,10 @@ aarch64_add_offset (machine_mode mode, rtx temp, rtx reg, HOST_WIDE_INT offset)
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return plus_constant (mode, reg, offset);
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}
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void
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aarch64_expand_mov_immediate (rtx dest, rtx imm)
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static int
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aarch64_internal_mov_immediate (rtx dest, rtx imm, bool generate,
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machine_mode mode)
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{
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machine_mode mode = GET_MODE (dest);
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unsigned HOST_WIDE_INT mask;
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int i;
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bool first;
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@ -1057,6 +1057,271 @@ aarch64_expand_mov_immediate (rtx dest, rtx imm)
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bool subtargets;
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rtx subtarget;
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int one_match, zero_match, first_not_ffff_match;
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int num_insns = 0;
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if (CONST_INT_P (imm) && aarch64_move_imm (INTVAL (imm), mode))
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{
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if (generate)
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emit_insn (gen_rtx_SET (VOIDmode, dest, imm));
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num_insns++;
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return num_insns;
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}
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if (mode == SImode)
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{
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/* We know we can't do this in 1 insn, and we must be able to do it
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in two; so don't mess around looking for sequences that don't buy
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us anything. */
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if (generate)
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{
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emit_insn (gen_rtx_SET (VOIDmode, dest,
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GEN_INT (INTVAL (imm) & 0xffff)));
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emit_insn (gen_insv_immsi (dest, GEN_INT (16),
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GEN_INT ((INTVAL (imm) >> 16) & 0xffff)));
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}
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num_insns += 2;
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return num_insns;
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}
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/* Remaining cases are all for DImode. */
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val = INTVAL (imm);
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subtargets = optimize && can_create_pseudo_p ();
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one_match = 0;
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zero_match = 0;
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mask = 0xffff;
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first_not_ffff_match = -1;
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for (i = 0; i < 64; i += 16, mask <<= 16)
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{
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if ((val & mask) == mask)
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one_match++;
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else
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{
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if (first_not_ffff_match < 0)
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first_not_ffff_match = i;
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if ((val & mask) == 0)
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zero_match++;
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}
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}
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if (one_match == 2)
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{
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/* Set one of the quarters and then insert back into result. */
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mask = 0xffffll << first_not_ffff_match;
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if (generate)
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{
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emit_insn (gen_rtx_SET (VOIDmode, dest, GEN_INT (val | mask)));
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emit_insn (gen_insv_immdi (dest, GEN_INT (first_not_ffff_match),
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GEN_INT ((val >> first_not_ffff_match)
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& 0xffff)));
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}
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num_insns += 2;
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return num_insns;
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}
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if (zero_match == 2)
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goto simple_sequence;
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mask = 0x0ffff0000UL;
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for (i = 16; i < 64; i += 16, mask <<= 16)
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{
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HOST_WIDE_INT comp = mask & ~(mask - 1);
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if (aarch64_uimm12_shift (val - (val & mask)))
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{
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if (generate)
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{
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subtarget = subtargets ? gen_reg_rtx (DImode) : dest;
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emit_insn (gen_rtx_SET (VOIDmode, subtarget,
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GEN_INT (val & mask)));
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emit_insn (gen_adddi3 (dest, subtarget,
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GEN_INT (val - (val & mask))));
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}
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num_insns += 2;
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return num_insns;
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}
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else if (aarch64_uimm12_shift (-(val - ((val + comp) & mask))))
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{
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if (generate)
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{
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subtarget = subtargets ? gen_reg_rtx (DImode) : dest;
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emit_insn (gen_rtx_SET (VOIDmode, subtarget,
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GEN_INT ((val + comp) & mask)));
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emit_insn (gen_adddi3 (dest, subtarget,
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GEN_INT (val - ((val + comp) & mask))));
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}
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num_insns += 2;
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return num_insns;
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}
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else if (aarch64_uimm12_shift (val - ((val - comp) | ~mask)))
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{
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if (generate)
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{
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subtarget = subtargets ? gen_reg_rtx (DImode) : dest;
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emit_insn (gen_rtx_SET (VOIDmode, subtarget,
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GEN_INT ((val - comp) | ~mask)));
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emit_insn (gen_adddi3 (dest, subtarget,
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GEN_INT (val - ((val - comp) | ~mask))));
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}
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num_insns += 2;
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return num_insns;
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}
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else if (aarch64_uimm12_shift (-(val - (val | ~mask))))
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{
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if (generate)
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{
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subtarget = subtargets ? gen_reg_rtx (DImode) : dest;
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emit_insn (gen_rtx_SET (VOIDmode, subtarget,
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GEN_INT (val | ~mask)));
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emit_insn (gen_adddi3 (dest, subtarget,
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GEN_INT (val - (val | ~mask))));
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}
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num_insns += 2;
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return num_insns;
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}
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}
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/* See if we can do it by arithmetically combining two
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immediates. */
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for (i = 0; i < AARCH64_NUM_BITMASKS; i++)
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{
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int j;
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mask = 0xffff;
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if (aarch64_uimm12_shift (val - aarch64_bitmasks[i])
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|| aarch64_uimm12_shift (-val + aarch64_bitmasks[i]))
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{
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if (generate)
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{
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subtarget = subtargets ? gen_reg_rtx (DImode) : dest;
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emit_insn (gen_rtx_SET (VOIDmode, subtarget,
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GEN_INT (aarch64_bitmasks[i])));
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emit_insn (gen_adddi3 (dest, subtarget,
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GEN_INT (val - aarch64_bitmasks[i])));
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}
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num_insns += 2;
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return num_insns;
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}
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for (j = 0; j < 64; j += 16, mask <<= 16)
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{
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if ((aarch64_bitmasks[i] & ~mask) == (val & ~mask))
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{
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if (generate)
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{
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emit_insn (gen_rtx_SET (VOIDmode, dest,
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GEN_INT (aarch64_bitmasks[i])));
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emit_insn (gen_insv_immdi (dest, GEN_INT (j),
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GEN_INT ((val >> j) & 0xffff)));
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}
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num_insns += 2;
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return num_insns;
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}
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}
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}
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/* See if we can do it by logically combining two immediates. */
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for (i = 0; i < AARCH64_NUM_BITMASKS; i++)
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{
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if ((aarch64_bitmasks[i] & val) == aarch64_bitmasks[i])
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{
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int j;
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for (j = i + 1; j < AARCH64_NUM_BITMASKS; j++)
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if (val == (aarch64_bitmasks[i] | aarch64_bitmasks[j]))
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{
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if (generate)
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{
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subtarget = subtargets ? gen_reg_rtx (mode) : dest;
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emit_insn (gen_rtx_SET (VOIDmode, subtarget,
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GEN_INT (aarch64_bitmasks[i])));
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emit_insn (gen_iordi3 (dest, subtarget,
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GEN_INT (aarch64_bitmasks[j])));
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}
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num_insns += 2;
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return num_insns;
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}
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}
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else if ((val & aarch64_bitmasks[i]) == val)
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{
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int j;
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for (j = i + 1; j < AARCH64_NUM_BITMASKS; j++)
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if (val == (aarch64_bitmasks[j] & aarch64_bitmasks[i]))
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{
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if (generate)
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{
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subtarget = subtargets ? gen_reg_rtx (mode) : dest;
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emit_insn (gen_rtx_SET (VOIDmode, subtarget,
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GEN_INT (aarch64_bitmasks[j])));
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emit_insn (gen_anddi3 (dest, subtarget,
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GEN_INT (aarch64_bitmasks[i])));
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}
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num_insns += 2;
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return num_insns;
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}
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}
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}
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if (one_match > zero_match)
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{
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/* Set either first three quarters or all but the third. */
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mask = 0xffffll << (16 - first_not_ffff_match);
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if (generate)
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emit_insn (gen_rtx_SET (VOIDmode, dest,
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GEN_INT (val | mask | 0xffffffff00000000ull)));
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num_insns ++;
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/* Now insert other two quarters. */
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for (i = first_not_ffff_match + 16, mask <<= (first_not_ffff_match << 1);
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i < 64; i += 16, mask <<= 16)
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{
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if ((val & mask) != mask)
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{
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if (generate)
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emit_insn (gen_insv_immdi (dest, GEN_INT (i),
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GEN_INT ((val >> i) & 0xffff)));
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num_insns ++;
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}
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}
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return num_insns;
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}
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simple_sequence:
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first = true;
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mask = 0xffff;
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for (i = 0; i < 64; i += 16, mask <<= 16)
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{
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if ((val & mask) != 0)
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{
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if (first)
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{
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if (generate)
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emit_insn (gen_rtx_SET (VOIDmode, dest,
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GEN_INT (val & mask)));
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num_insns ++;
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first = false;
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}
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else
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{
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if (generate)
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emit_insn (gen_insv_immdi (dest, GEN_INT (i),
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GEN_INT ((val >> i) & 0xffff)));
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num_insns ++;
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}
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}
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}
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return num_insns;
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}
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void
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aarch64_expand_mov_immediate (rtx dest, rtx imm)
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{
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machine_mode mode = GET_MODE (dest);
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gcc_assert (mode == SImode || mode == DImode);
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@ -1118,12 +1383,6 @@ aarch64_expand_mov_immediate (rtx dest, rtx imm)
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}
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}
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if (CONST_INT_P (imm) && aarch64_move_imm (INTVAL (imm), mode))
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{
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emit_insn (gen_rtx_SET (VOIDmode, dest, imm));
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return;
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}
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if (!CONST_INT_P (imm))
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{
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if (GET_CODE (imm) == HIGH)
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@ -1138,203 +1397,7 @@ aarch64_expand_mov_immediate (rtx dest, rtx imm)
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return;
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}
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if (mode == SImode)
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{
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/* We know we can't do this in 1 insn, and we must be able to do it
|
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in two; so don't mess around looking for sequences that don't buy
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us anything. */
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emit_insn (gen_rtx_SET (VOIDmode, dest, GEN_INT (INTVAL (imm) & 0xffff)));
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emit_insn (gen_insv_immsi (dest, GEN_INT (16),
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GEN_INT ((INTVAL (imm) >> 16) & 0xffff)));
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return;
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}
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/* Remaining cases are all for DImode. */
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val = INTVAL (imm);
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subtargets = optimize && can_create_pseudo_p ();
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one_match = 0;
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zero_match = 0;
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mask = 0xffff;
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first_not_ffff_match = -1;
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for (i = 0; i < 64; i += 16, mask <<= 16)
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{
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if ((val & mask) == mask)
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one_match++;
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else
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{
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if (first_not_ffff_match < 0)
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first_not_ffff_match = i;
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if ((val & mask) == 0)
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zero_match++;
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}
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}
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if (one_match == 2)
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{
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/* Set one of the quarters and then insert back into result. */
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mask = 0xffffll << first_not_ffff_match;
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emit_insn (gen_rtx_SET (VOIDmode, dest, GEN_INT (val | mask)));
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emit_insn (gen_insv_immdi (dest, GEN_INT (first_not_ffff_match),
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GEN_INT ((val >> first_not_ffff_match)
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& 0xffff)));
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return;
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}
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if (zero_match == 2)
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goto simple_sequence;
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mask = 0x0ffff0000UL;
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for (i = 16; i < 64; i += 16, mask <<= 16)
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{
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HOST_WIDE_INT comp = mask & ~(mask - 1);
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if (aarch64_uimm12_shift (val - (val & mask)))
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{
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subtarget = subtargets ? gen_reg_rtx (DImode) : dest;
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emit_insn (gen_rtx_SET (VOIDmode, subtarget, GEN_INT (val & mask)));
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emit_insn (gen_adddi3 (dest, subtarget,
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GEN_INT (val - (val & mask))));
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return;
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}
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else if (aarch64_uimm12_shift (-(val - ((val + comp) & mask))))
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{
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subtarget = subtargets ? gen_reg_rtx (DImode) : dest;
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emit_insn (gen_rtx_SET (VOIDmode, subtarget,
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GEN_INT ((val + comp) & mask)));
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emit_insn (gen_adddi3 (dest, subtarget,
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GEN_INT (val - ((val + comp) & mask))));
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return;
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}
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else if (aarch64_uimm12_shift (val - ((val - comp) | ~mask)))
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{
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subtarget = subtargets ? gen_reg_rtx (DImode) : dest;
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emit_insn (gen_rtx_SET (VOIDmode, subtarget,
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GEN_INT ((val - comp) | ~mask)));
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emit_insn (gen_adddi3 (dest, subtarget,
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GEN_INT (val - ((val - comp) | ~mask))));
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return;
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}
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else if (aarch64_uimm12_shift (-(val - (val | ~mask))))
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{
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subtarget = subtargets ? gen_reg_rtx (DImode) : dest;
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emit_insn (gen_rtx_SET (VOIDmode, subtarget,
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GEN_INT (val | ~mask)));
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emit_insn (gen_adddi3 (dest, subtarget,
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GEN_INT (val - (val | ~mask))));
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return;
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}
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}
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/* See if we can do it by arithmetically combining two
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immediates. */
|
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for (i = 0; i < AARCH64_NUM_BITMASKS; i++)
|
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{
|
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int j;
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mask = 0xffff;
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|
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if (aarch64_uimm12_shift (val - aarch64_bitmasks[i])
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|| aarch64_uimm12_shift (-val + aarch64_bitmasks[i]))
|
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{
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subtarget = subtargets ? gen_reg_rtx (DImode) : dest;
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emit_insn (gen_rtx_SET (VOIDmode, subtarget,
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GEN_INT (aarch64_bitmasks[i])));
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emit_insn (gen_adddi3 (dest, subtarget,
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GEN_INT (val - aarch64_bitmasks[i])));
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return;
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}
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|
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for (j = 0; j < 64; j += 16, mask <<= 16)
|
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{
|
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if ((aarch64_bitmasks[i] & ~mask) == (val & ~mask))
|
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{
|
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emit_insn (gen_rtx_SET (VOIDmode, dest,
|
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GEN_INT (aarch64_bitmasks[i])));
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emit_insn (gen_insv_immdi (dest, GEN_INT (j),
|
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GEN_INT ((val >> j) & 0xffff)));
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return;
|
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}
|
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}
|
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}
|
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|
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/* See if we can do it by logically combining two immediates. */
|
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for (i = 0; i < AARCH64_NUM_BITMASKS; i++)
|
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{
|
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if ((aarch64_bitmasks[i] & val) == aarch64_bitmasks[i])
|
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{
|
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int j;
|
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|
||||
for (j = i + 1; j < AARCH64_NUM_BITMASKS; j++)
|
||||
if (val == (aarch64_bitmasks[i] | aarch64_bitmasks[j]))
|
||||
{
|
||||
subtarget = subtargets ? gen_reg_rtx (mode) : dest;
|
||||
emit_insn (gen_rtx_SET (VOIDmode, subtarget,
|
||||
GEN_INT (aarch64_bitmasks[i])));
|
||||
emit_insn (gen_iordi3 (dest, subtarget,
|
||||
GEN_INT (aarch64_bitmasks[j])));
|
||||
return;
|
||||
}
|
||||
}
|
||||
else if ((val & aarch64_bitmasks[i]) == val)
|
||||
{
|
||||
int j;
|
||||
|
||||
for (j = i + 1; j < AARCH64_NUM_BITMASKS; j++)
|
||||
if (val == (aarch64_bitmasks[j] & aarch64_bitmasks[i]))
|
||||
{
|
||||
|
||||
subtarget = subtargets ? gen_reg_rtx (mode) : dest;
|
||||
emit_insn (gen_rtx_SET (VOIDmode, subtarget,
|
||||
GEN_INT (aarch64_bitmasks[j])));
|
||||
emit_insn (gen_anddi3 (dest, subtarget,
|
||||
GEN_INT (aarch64_bitmasks[i])));
|
||||
return;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if (one_match > zero_match)
|
||||
{
|
||||
/* Set either first three quarters or all but the third. */
|
||||
mask = 0xffffll << (16 - first_not_ffff_match);
|
||||
emit_insn (gen_rtx_SET (VOIDmode, dest,
|
||||
GEN_INT (val | mask | 0xffffffff00000000ull)));
|
||||
|
||||
/* Now insert other two quarters. */
|
||||
for (i = first_not_ffff_match + 16, mask <<= (first_not_ffff_match << 1);
|
||||
i < 64; i += 16, mask <<= 16)
|
||||
{
|
||||
if ((val & mask) != mask)
|
||||
emit_insn (gen_insv_immdi (dest, GEN_INT (i),
|
||||
GEN_INT ((val >> i) & 0xffff)));
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
simple_sequence:
|
||||
first = true;
|
||||
mask = 0xffff;
|
||||
for (i = 0; i < 64; i += 16, mask <<= 16)
|
||||
{
|
||||
if ((val & mask) != 0)
|
||||
{
|
||||
if (first)
|
||||
{
|
||||
emit_insn (gen_rtx_SET (VOIDmode, dest,
|
||||
GEN_INT (val & mask)));
|
||||
first = false;
|
||||
}
|
||||
else
|
||||
emit_insn (gen_insv_immdi (dest, GEN_INT (i),
|
||||
GEN_INT ((val >> i) & 0xffff)));
|
||||
}
|
||||
}
|
||||
aarch64_internal_mov_immediate (dest, imm, true, GET_MODE (dest));
|
||||
}
|
||||
|
||||
static bool
|
||||
@ -5240,9 +5303,8 @@ aarch64_rtx_costs (rtx x, int code, int outer ATTRIBUTE_UNUSED,
|
||||
proportionally expensive to the number of instructions
|
||||
required to build that constant. This is true whether we
|
||||
are compiling for SPEED or otherwise. */
|
||||
*cost = COSTS_N_INSNS (aarch64_build_constant (0,
|
||||
INTVAL (x),
|
||||
false));
|
||||
*cost = COSTS_N_INSNS (aarch64_internal_mov_immediate
|
||||
(NULL_RTX, x, false, mode));
|
||||
}
|
||||
return true;
|
||||
|
||||
@ -8041,7 +8103,7 @@ aarch64_mov_operand_p (rtx x,
|
||||
&& aarch64_valid_symref (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
|
||||
return true;
|
||||
|
||||
if (CONST_INT_P (x) && aarch64_move_imm (INTVAL (x), mode))
|
||||
if (CONST_INT_P (x))
|
||||
return true;
|
||||
|
||||
if (GET_CODE (x) == SYMBOL_REF && mode == DImode && CONSTANT_ADDRESS_P (x))
|
||||
|
||||
@ -746,17 +746,20 @@
|
||||
if (GET_CODE (operands[0]) == MEM && operands[1] != const0_rtx)
|
||||
operands[1] = force_reg (<MODE>mode, operands[1]);
|
||||
|
||||
if (CONSTANT_P (operands[1]))
|
||||
{
|
||||
aarch64_expand_mov_immediate (operands[0], operands[1]);
|
||||
DONE;
|
||||
}
|
||||
/* FIXME: RR we still need to fix up what we are doing with
|
||||
symbol_refs and other types of constants. */
|
||||
if (CONSTANT_P (operands[1])
|
||||
&& !CONST_INT_P (operands[1]))
|
||||
{
|
||||
aarch64_expand_mov_immediate (operands[0], operands[1]);
|
||||
DONE;
|
||||
}
|
||||
"
|
||||
)
|
||||
|
||||
(define_insn "*movsi_aarch64"
|
||||
[(set (match_operand:SI 0 "nonimmediate_operand" "=r,k,r,r,r,*w,m, m,r,r ,*w, r,*w")
|
||||
(match_operand:SI 1 "aarch64_mov_operand" " r,r,k,M,m, m,rZ,*w,S,Ush,rZ,*w,*w"))]
|
||||
(define_insn_and_split "*movsi_aarch64"
|
||||
[(set (match_operand:SI 0 "nonimmediate_operand" "=r,k,r,r,r,r,*w,m, m,r,r ,*w, r,*w")
|
||||
(match_operand:SI 1 "aarch64_mov_operand" " r,r,k,M,n,m, m,rZ,*w,S,Ush,rZ,*w,*w"))]
|
||||
"(register_operand (operands[0], SImode)
|
||||
|| aarch64_reg_or_zero (operands[1], SImode))"
|
||||
"@
|
||||
@ -764,6 +767,7 @@
|
||||
mov\\t%w0, %w1
|
||||
mov\\t%w0, %w1
|
||||
mov\\t%w0, %1
|
||||
#
|
||||
ldr\\t%w0, %1
|
||||
ldr\\t%s0, %1
|
||||
str\\t%w1, %0
|
||||
@ -773,14 +777,20 @@
|
||||
fmov\\t%s0, %w1
|
||||
fmov\\t%w0, %s1
|
||||
fmov\\t%s0, %s1"
|
||||
[(set_attr "type" "mov_reg,mov_reg,mov_reg,mov_imm,load1,load1,store1,store1,\
|
||||
"CONST_INT_P (operands[1]) && !aarch64_move_imm (INTVAL (operands[1]), SImode)"
|
||||
[(const_int 0)]
|
||||
"{
|
||||
aarch64_expand_mov_immediate (operands[0], operands[1]);
|
||||
DONE;
|
||||
}"
|
||||
[(set_attr "type" "mov_reg,mov_reg,mov_reg,mov_imm,mov_imm,load1,load1,store1,store1,\
|
||||
adr,adr,f_mcr,f_mrc,fmov")
|
||||
(set_attr "fp" "*,*,*,*,*,yes,*,yes,*,*,yes,yes,yes")]
|
||||
(set_attr "fp" "*,*,*,*,*,*,yes,*,yes,*,*,yes,yes,yes")]
|
||||
)
|
||||
|
||||
(define_insn "*movdi_aarch64"
|
||||
[(set (match_operand:DI 0 "nonimmediate_operand" "=r,k,r,r,r,*w,m, m,r,r, *w, r,*w,w")
|
||||
(match_operand:DI 1 "aarch64_mov_operand" " r,r,k,N,m, m,rZ,*w,S,Ush,rZ,*w,*w,Dd"))]
|
||||
(define_insn_and_split "*movdi_aarch64"
|
||||
[(set (match_operand:DI 0 "nonimmediate_operand" "=r,k,r,r,r,r,*w,m, m,r,r, *w, r,*w,w")
|
||||
(match_operand:DI 1 "aarch64_mov_operand" " r,r,k,N,n,m, m,rZ,*w,S,Ush,rZ,*w,*w,Dd"))]
|
||||
"(register_operand (operands[0], DImode)
|
||||
|| aarch64_reg_or_zero (operands[1], DImode))"
|
||||
"@
|
||||
@ -788,6 +798,7 @@
|
||||
mov\\t%0, %x1
|
||||
mov\\t%x0, %1
|
||||
mov\\t%x0, %1
|
||||
#
|
||||
ldr\\t%x0, %1
|
||||
ldr\\t%d0, %1
|
||||
str\\t%x1, %0
|
||||
@ -798,10 +809,16 @@
|
||||
fmov\\t%x0, %d1
|
||||
fmov\\t%d0, %d1
|
||||
movi\\t%d0, %1"
|
||||
[(set_attr "type" "mov_reg,mov_reg,mov_reg,mov_imm,load1,load1,store1,store1,\
|
||||
"(CONST_INT_P (operands[1]) && !aarch64_move_imm (INTVAL (operands[1]), DImode))"
|
||||
[(const_int 0)]
|
||||
"{
|
||||
aarch64_expand_mov_immediate (operands[0], operands[1]);
|
||||
DONE;
|
||||
}"
|
||||
[(set_attr "type" "mov_reg,mov_reg,mov_reg,mov_imm,mov_imm,load1,load1,store1,store1,\
|
||||
adr,adr,f_mcr,f_mrc,fmov,fmov")
|
||||
(set_attr "fp" "*,*,*,*,*,yes,*,yes,*,*,yes,yes,yes,*")
|
||||
(set_attr "simd" "*,*,*,*,*,*,*,*,*,*,*,*,*,yes")]
|
||||
(set_attr "fp" "*,*,*,*,*,*,yes,*,yes,*,*,yes,yes,yes,*")
|
||||
(set_attr "simd" "*,*,*,*,*,*,*,*,*,*,*,*,*,*,yes")]
|
||||
)
|
||||
|
||||
(define_insn "insv_imm<mode>"
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user