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2014-04-08  Pat Haugen  <pthaugen@us.ibm.com>

        * config/rs6000/sync.md (AINT mode_iterator): Move definition.
        (loadsync_<mode>): Change mode.
        (load_quadpti, store_quadpti): New.
        (atomic_load<mode>, atomic_store<mode>): Add support for TI mode.
        * config/rs6000/rs6000.md (unspec enum): Add UNSPEC_LSQ.
        * config/rs6000/predicates.md (quad_memory_operand): !TARGET_SYNC_TI.

From-SVN: r209253
This commit is contained in:
David Edelsohn 2014-04-09 19:53:39 +00:00 committed by David Edelsohn
parent 51970b3e33
commit 8267f6bb08
4 changed files with 29 additions and 93 deletions
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12
gcc/ChangeLog
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@ -1,3 +1,15 @@
2014-04-09 David Edelsohn <dje.gcc@gmail.com>
Revert
2014-04-08 Pat Haugen <pthaugen@us.ibm.com>
* config/rs6000/sync.md (AINT mode_iterator): Move definition.
(loadsync_<mode>): Change mode.
(load_quadpti, store_quadpti): New.
(atomic_load<mode>, atomic_store<mode>): Add support for TI mode.
* config/rs6000/rs6000.md (unspec enum): Add UNSPEC_LSQ.
* config/rs6000/predicates.md (quad_memory_operand): !TARGET_SYNC_TI.
2014-04-09 Cong Hou <congh@google.com>
PR testsuite/60773

4
gcc/config/rs6000/predicates.md
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@ -624,14 +624,14 @@
(match_test "offsettable_nonstrict_memref_p (op)")))
;; Return 1 if the operand is suitable for load/store quad memory.
;; This predicate only checks for non-atomic loads/stores (not lqarx/stqcx).
;; This predicate only checks for non-atomic loads/stores.
(define_predicate "quad_memory_operand"
(match_code "mem")
{
rtx addr, op0, op1;
int ret;
if (!TARGET_QUAD_MEMORY && !TARGET_SYNC_TI)
if (!TARGET_QUAD_MEMORY)
ret = 0;
else if (!memory_operand (op, mode))

1
gcc/config/rs6000/rs6000.md
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@ -125,7 +125,6 @@
UNSPEC_P8V_MTVSRD
UNSPEC_P8V_XXPERMDI
UNSPEC_P8V_RELOAD_FROM_VSX
UNSPEC_LSQ
])
;;

105
gcc/config/rs6000/sync.md
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@ -107,17 +107,10 @@
"isync"
[(set_attr "type" "isync")])
;; Types that we should provide atomic instructions for.
(define_mode_iterator AINT [QI
HI
SI
(DI "TARGET_POWERPC64")
(TI "TARGET_SYNC_TI")])
;; The control dependency used for load dependency described
;; in B.2.3 of the Power ISA 2.06B.
(define_insn "loadsync_<mode>"
[(unspec_volatile:BLK [(match_operand:AINT 0 "register_operand" "r")]
[(unspec_volatile:BLK [(match_operand:INT1 0 "register_operand" "r")]
UNSPECV_ISYNC)
(clobber (match_scratch:CC 1 "=y"))]
""
@ -125,56 +118,18 @@
[(set_attr "type" "isync")
(set_attr "length" "12")])
(define_insn "load_quadpti"
[(set (match_operand:PTI 0 "quad_int_reg_operand" "=&r")
(unspec:PTI
[(match_operand:TI 1 "quad_memory_operand" "wQ")] UNSPEC_LSQ))]
"TARGET_SYNC_TI
&& !reg_mentioned_p (operands[0], operands[1])"
"lq %0,%1"
[(set_attr "type" "load")
(set_attr "length" "4")])
(define_expand "atomic_load<mode>"
[(set (match_operand:AINT 0 "register_operand" "") ;; output
(match_operand:AINT 1 "memory_operand" "")) ;; memory
[(set (match_operand:INT1 0 "register_operand" "") ;; output
(match_operand:INT1 1 "memory_operand" "")) ;; memory
(use (match_operand:SI 2 "const_int_operand" ""))] ;; model
""
{
if (<MODE>mode == TImode && !TARGET_SYNC_TI)
FAIL;
enum memmodel model = (enum memmodel) INTVAL (operands[2]);
if (model == MEMMODEL_SEQ_CST)
emit_insn (gen_hwsync ());
if (<MODE>mode != TImode)
emit_move_insn (operands[0], operands[1]);
else
{
rtx op0 = operands[0];
rtx op1 = operands[1];
rtx pti_reg = gen_reg_rtx (PTImode);
// Can't have indexed address for 'lq'
if (indexed_address (XEXP (op1, 0), TImode))
{
rtx old_addr = XEXP (op1, 0);
rtx new_addr = force_reg (Pmode, old_addr);
operands[1] = op1 = replace_equiv_address (op1, new_addr);
}
emit_insn (gen_load_quadpti (pti_reg, op1));
if (WORDS_BIG_ENDIAN)
emit_move_insn (op0, gen_lowpart (TImode, pti_reg));
else
{
emit_move_insn (gen_lowpart (DImode, op0), gen_highpart (DImode, pti_reg));
emit_move_insn (gen_highpart (DImode, op0), gen_lowpart (DImode, pti_reg));
}
}
emit_move_insn (operands[0], operands[1]);
switch (model)
{
@ -191,24 +146,12 @@
DONE;
})
(define_insn "store_quadpti"
[(set (match_operand:PTI 0 "quad_memory_operand" "=wQ")
(unspec:PTI
[(match_operand:PTI 1 "quad_int_reg_operand" "r")] UNSPEC_LSQ))]
"TARGET_SYNC_TI"
"stq %1,%0"
[(set_attr "type" "store")
(set_attr "length" "4")])
(define_expand "atomic_store<mode>"
[(set (match_operand:AINT 0 "memory_operand" "") ;; memory
(match_operand:AINT 1 "register_operand" "")) ;; input
[(set (match_operand:INT1 0 "memory_operand" "") ;; memory
(match_operand:INT1 1 "register_operand" "")) ;; input
(use (match_operand:SI 2 "const_int_operand" ""))] ;; model
""
{
if (<MODE>mode == TImode && !TARGET_SYNC_TI)
FAIL;
enum memmodel model = (enum memmodel) INTVAL (operands[2]);
switch (model)
{
@ -223,33 +166,7 @@
default:
gcc_unreachable ();
}
if (<MODE>mode != TImode)
emit_move_insn (operands[0], operands[1]);
else
{
rtx op0 = operands[0];
rtx op1 = operands[1];
rtx pti_reg = gen_reg_rtx (PTImode);
// Can't have indexed address for 'stq'
if (indexed_address (XEXP (op0, 0), TImode))
{
rtx old_addr = XEXP (op0, 0);
rtx new_addr = force_reg (Pmode, old_addr);
operands[0] = op0 = replace_equiv_address (op0, new_addr);
}
if (WORDS_BIG_ENDIAN)
emit_move_insn (pti_reg, gen_lowpart (PTImode, op1));
else
{
emit_move_insn (gen_lowpart (DImode, pti_reg), gen_highpart (DImode, op1));
emit_move_insn (gen_highpart (DImode, pti_reg), gen_lowpart (DImode, op1));
}
emit_insn (gen_store_quadpti (gen_lowpart (PTImode, op0), pti_reg));
}
emit_move_insn (operands[0], operands[1]);
DONE;
})
@ -263,6 +180,14 @@
SI
(DI "TARGET_POWERPC64")])
;; Types that we should provide atomic instructions for.
(define_mode_iterator AINT [QI
HI
SI
(DI "TARGET_POWERPC64")
(TI "TARGET_SYNC_TI")])
(define_insn "load_locked<mode>"
[(set (match_operand:ATOMIC 0 "int_reg_operand" "=r")
(unspec_volatile:ATOMIC