[AArch64] Improve arm_neon.h vml<as>_lane handling.
gcc/ * config/aarch64/aarch64-simd-builtins.def (fma): New. * config/aarch64/aarch64-simd.md (aarch64_mla_elt<mode>): New. (aarch64_mla_elt_<vswap_width_name><mode>): Likewise. (aarch64_mls_elt<mode>): Likewise. (aarch64_mls_elt_<vswap_width_name><mode>): Likewise. (aarch64_fma4_elt<mode>): Likewise. (aarch64_fma4_elt_<vswap_width_name><mode>): Likewise. (aarch64_fma4_elt_to_128v2df): Likewise. (aarch64_fma4_elt_to_64df): Likewise. (fnma<mode>4): Likewise. (aarch64_fnma4_elt<mode>): Likewise. (aarch64_fnma4_elt_<vswap_width_name><mode>): Likewise. (aarch64_fnma4_elt_to_128v2df): Likewise. (aarch64_fnma4_elt_to_64df): Likewise. * config/aarch64/iterators.md (VDQSF): New. * config/aarch64/arm_neon.h (vfm<as><sdq>_lane<q>_f<32, 64>): Convert to C implementation. (vml<sa><q>_lane<q>_<fsu><16, 32, 64>): Likewise. gcc/testsuite/ * gcc.target/aarch64/fmla-intrinsic.c: New. * gcc.target/aarch64/mla-intrinsic.c: Likewise. * gcc.target/aarch64/fmls-intrinsic.c: Likewise. * gcc.target/aarch64/mls-intrinsic.c: Likewise. From-SVN: r202625
This commit is contained in:
James Greenhalgh
James Greenhalgh
parent
779aea46cc
commit
828e70c1d7
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@ -1,3 +1,25 @@
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2013-09-16 James Greenhalgh <james.greenhalgh@arm.com>
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* config/aarch64/aarch64-simd-builtins.def (fma): New.
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* config/aarch64/aarch64-simd.md
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(aarch64_mla_elt<mode>): New.
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(aarch64_mla_elt_<vswap_width_name><mode>): Likewise.
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(aarch64_mls_elt<mode>): Likewise.
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(aarch64_mls_elt_<vswap_width_name><mode>): Likewise.
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(aarch64_fma4_elt<mode>): Likewise.
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(aarch64_fma4_elt_<vswap_width_name><mode>): Likewise.
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(aarch64_fma4_elt_to_128v2df): Likewise.
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(aarch64_fma4_elt_to_64df): Likewise.
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(fnma<mode>4): Likewise.
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(aarch64_fnma4_elt<mode>): Likewise.
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(aarch64_fnma4_elt_<vswap_width_name><mode>): Likewise.
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(aarch64_fnma4_elt_to_128v2df): Likewise.
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(aarch64_fnma4_elt_to_64df): Likewise.
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* config/aarch64/iterators.md (VDQSF): New.
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* config/aarch64/arm_neon.h
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(vfm<as><sdq>_lane<q>_f<32, 64>): Convert to C implementation.
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(vml<sa><q>_lane<q>_<fsu><16, 32, 64>): Likewise.
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2013-09-16 James Greenhalgh <james.greenhalgh@arm.com>
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* config/aarch64/aarch64-simd.md (aarch64_mul3_elt<mode>): New.
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@ -359,3 +359,6 @@
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/* Implemented by aarch64_st1<VALL:mode>. */
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BUILTIN_VALL (STORE1, st1, 0)
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/* Implemented by fma<mode>4. */
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BUILTIN_VDQF (TERNOP, fma, 4)
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@ -1070,6 +1070,38 @@
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(set_attr "simd_mode" "<MODE>")]
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)
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(define_insn "*aarch64_mla_elt<mode>"
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[(set (match_operand:VDQHS 0 "register_operand" "=w")
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(plus:VDQHS
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(mult:VDQHS
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(vec_duplicate:VDQHS
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(vec_select:<VEL>
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(match_operand:VDQHS 1 "register_operand" "<h_con>")
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(parallel [(match_operand:SI 2 "immediate_operand")])))
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(match_operand:VDQHS 3 "register_operand" "w"))
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(match_operand:VDQHS 4 "register_operand" "0")))]
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"TARGET_SIMD"
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"mla\t%0.<Vtype>, %3.<Vtype>, %1.<Vtype>[%2]"
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[(set_attr "simd_type" "simd_mla")
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(set_attr "simd_mode" "<MODE>")]
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)
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(define_insn "*aarch64_mla_elt_<vswap_width_name><mode>"
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[(set (match_operand:VDQHS 0 "register_operand" "=w")
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(plus:VDQHS
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(mult:VDQHS
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(vec_duplicate:VDQHS
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(vec_select:<VEL>
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(match_operand:<VSWAP_WIDTH> 1 "register_operand" "<h_con>")
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(parallel [(match_operand:SI 2 "immediate_operand")])))
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(match_operand:VDQHS 3 "register_operand" "w"))
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(match_operand:VDQHS 4 "register_operand" "0")))]
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"TARGET_SIMD"
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"mla\t%0.<Vtype>, %3.<Vtype>, %1.<Vtype>[%2]"
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[(set_attr "simd_type" "simd_mla")
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(set_attr "simd_mode" "<MODE>")]
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)
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(define_insn "aarch64_mls<mode>"
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[(set (match_operand:VQ_S 0 "register_operand" "=w")
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(minus:VQ_S (match_operand:VQ_S 1 "register_operand" "0")
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@ -1081,6 +1113,38 @@
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(set_attr "simd_mode" "<MODE>")]
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)
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(define_insn "*aarch64_mls_elt<mode>"
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[(set (match_operand:VDQHS 0 "register_operand" "=w")
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(minus:VDQHS
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(match_operand:VDQHS 4 "register_operand" "0")
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(mult:VDQHS
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(vec_duplicate:VDQHS
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(vec_select:<VEL>
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(match_operand:VDQHS 1 "register_operand" "<h_con>")
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(parallel [(match_operand:SI 2 "immediate_operand")])))
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(match_operand:VDQHS 3 "register_operand" "w"))))]
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"TARGET_SIMD"
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"mls\t%0.<Vtype>, %3.<Vtype>, %1.<Vtype>[%2]"
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[(set_attr "simd_type" "simd_mla")
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(set_attr "simd_mode" "<MODE>")]
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)
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(define_insn "*aarch64_mls_elt_<vswap_width_name><mode>"
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[(set (match_operand:VDQHS 0 "register_operand" "=w")
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(minus:VDQHS
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(match_operand:VDQHS 4 "register_operand" "0")
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(mult:VDQHS
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(vec_duplicate:VDQHS
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(vec_select:<VEL>
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(match_operand:<VSWAP_WIDTH> 1 "register_operand" "<h_con>")
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(parallel [(match_operand:SI 2 "immediate_operand")])))
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(match_operand:VDQHS 3 "register_operand" "w"))))]
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"TARGET_SIMD"
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"mls\t%0.<Vtype>, %3.<Vtype>, %1.<Vtype>[%2]"
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[(set_attr "simd_type" "simd_mla")
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(set_attr "simd_mode" "<MODE>")]
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)
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;; Max/Min operations.
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(define_insn "<su><maxmin><mode>3"
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[(set (match_operand:VQ_S 0 "register_operand" "=w")
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@ -1483,6 +1547,137 @@
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(set_attr "simd_mode" "<MODE>")]
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)
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(define_insn "*aarch64_fma4_elt<mode>"
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[(set (match_operand:VDQF 0 "register_operand" "=w")
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(fma:VDQF
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(vec_duplicate:VDQF
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(vec_select:<VEL>
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(match_operand:VDQF 1 "register_operand" "<h_con>")
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(parallel [(match_operand:SI 2 "immediate_operand")])))
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(match_operand:VDQF 3 "register_operand" "w")
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(match_operand:VDQF 4 "register_operand" "0")))]
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"TARGET_SIMD"
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"fmla\\t%0.<Vtype>, %3.<Vtype>, %1.<Vtype>[%2]"
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[(set_attr "simd_type" "simd_fmla_elt")
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(set_attr "simd_mode" "<MODE>")]
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)
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(define_insn "*aarch64_fma4_elt_<vswap_width_name><mode>"
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[(set (match_operand:VDQSF 0 "register_operand" "=w")
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(fma:VDQSF
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(vec_duplicate:VDQSF
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(vec_select:<VEL>
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(match_operand:<VSWAP_WIDTH> 1 "register_operand" "<h_con>")
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(parallel [(match_operand:SI 2 "immediate_operand")])))
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(match_operand:VDQSF 3 "register_operand" "w")
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(match_operand:VDQSF 4 "register_operand" "0")))]
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"TARGET_SIMD"
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"fmla\\t%0.<Vtype>, %3.<Vtype>, %1.<Vtype>[%2]"
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[(set_attr "simd_type" "simd_fmla_elt")
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(set_attr "simd_mode" "<MODE>")]
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)
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(define_insn "*aarch64_fma4_elt_to_128df"
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[(set (match_operand:V2DF 0 "register_operand" "=w")
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(fma:V2DF
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(vec_duplicate:V2DF
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(match_operand:DF 1 "register_operand" "w"))
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(match_operand:V2DF 2 "register_operand" "w")
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(match_operand:V2DF 3 "register_operand" "0")))]
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"TARGET_SIMD"
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"fmla\\t%0.2d, %2.2d, %1.2d[0]"
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[(set_attr "simd_type" "simd_fmla_elt")
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(set_attr "simd_mode" "V2DF")]
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)
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(define_insn "*aarch64_fma4_elt_to_64v2df"
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[(set (match_operand:DF 0 "register_operand" "=w")
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(fma:DF
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(vec_select:DF
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(match_operand:V2DF 1 "register_operand" "w")
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(parallel [(match_operand:SI 2 "immediate_operand")]))
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(match_operand:DF 3 "register_operand" "w")
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(match_operand:DF 4 "register_operand" "0")))]
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"TARGET_SIMD"
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"fmla\\t%0.2d, %3.2d, %1.2d[%2]"
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[(set_attr "simd_type" "simd_fmla_elt")
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(set_attr "simd_mode" "V2DF")]
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)
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(define_insn "fnma<mode>4"
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[(set (match_operand:VDQF 0 "register_operand" "=w")
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(fma:VDQF
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(match_operand:VDQF 1 "register_operand" "w")
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(neg:VDQF
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(match_operand:VDQF 2 "register_operand" "w"))
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(match_operand:VDQF 3 "register_operand" "0")))]
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"TARGET_SIMD"
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"fmls\\t%0.<Vtype>, %1.<Vtype>, %2.<Vtype>"
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[(set_attr "simd_type" "simd_fmla")
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(set_attr "simd_mode" "<MODE>")]
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)
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(define_insn "*aarch64_fnma4_elt<mode>"
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[(set (match_operand:VDQF 0 "register_operand" "=w")
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(fma:VDQF
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(neg:VDQF
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(match_operand:VDQF 3 "register_operand" "w"))
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(vec_duplicate:VDQF
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(vec_select:<VEL>
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(match_operand:VDQF 1 "register_operand" "<h_con>")
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(parallel [(match_operand:SI 2 "immediate_operand")])))
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(match_operand:VDQF 4 "register_operand" "0")))]
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"TARGET_SIMD"
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"fmls\\t%0.<Vtype>, %3.<Vtype>, %1.<Vtype>[%2]"
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[(set_attr "simd_type" "simd_fmla_elt")
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(set_attr "simd_mode" "<MODE>")]
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)
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(define_insn "*aarch64_fnma4_elt_<vswap_width_name><mode>"
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[(set (match_operand:VDQSF 0 "register_operand" "=w")
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(fma:VDQSF
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(neg:VDQSF
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(match_operand:VDQSF 3 "register_operand" "w"))
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(vec_duplicate:VDQSF
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(vec_select:<VEL>
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(match_operand:<VSWAP_WIDTH> 1 "register_operand" "<h_con>")
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(parallel [(match_operand:SI 2 "immediate_operand")])))
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(match_operand:VDQSF 4 "register_operand" "0")))]
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"TARGET_SIMD"
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"fmls\\t%0.<Vtype>, %3.<Vtype>, %1.<Vtype>[%2]"
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[(set_attr "simd_type" "simd_fmla_elt")
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(set_attr "simd_mode" "<MODE>")]
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)
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(define_insn "*aarch64_fnma4_elt_to_128df"
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[(set (match_operand:V2DF 0 "register_operand" "=w")
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(fma:V2DF
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(neg:V2DF
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(match_operand:V2DF 2 "register_operand" "w"))
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(vec_duplicate:V2DF
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(match_operand:DF 1 "register_operand" "w"))
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(match_operand:V2DF 3 "register_operand" "0")))]
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"TARGET_SIMD"
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"fmls\\t%0.2d, %2.2d, %1.2d[0]"
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[(set_attr "simd_type" "simd_fmla_elt")
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(set_attr "simd_mode" "V2DF")]
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)
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(define_insn "*aarch64_fnma4_elt_to_64v2df"
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[(set (match_operand:DF 0 "register_operand" "=w")
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(fma:DF
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(vec_select:DF
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(match_operand:V2DF 1 "register_operand" "w")
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(parallel [(match_operand:SI 2 "immediate_operand")]))
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(neg:DF
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(match_operand:DF 3 "register_operand" "w"))
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(match_operand:DF 4 "register_operand" "0")))]
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"TARGET_SIMD"
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"fmls\\t%0.2d, %3.2d, %1.2d[%2]"
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[(set_attr "simd_type" "simd_fmla_elt")
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(set_attr "simd_mode" "V2DF")]
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)
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;; Vector versions of the floating-point frint patterns.
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;; Expands to btrunc, ceil, floor, nearbyint, rint, round.
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(define_insn "<frint_pattern><mode>2"
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File diff suppressed because it is too large
Load Diff
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@ -89,6 +89,9 @@
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;; Vector Float modes.
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(define_mode_iterator VDQF [V2SF V4SF V2DF])
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;; Vector single Float modes.
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(define_mode_iterator VDQSF [V2SF V4SF])
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;; Modes suitable to use as the return type of a vcond expression.
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(define_mode_iterator VDQF_COND [V2SF V2SI V4SF V4SI V2DF V2DI])
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@ -1,3 +1,10 @@
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2013-09-16 James Greenhalgh <james.greenhalgh@arm.com>
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* gcc.target/aarch64/fmla-intrinsic.c: New.
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* gcc.target/aarch64/mla-intrinsic.c: Likewise.
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* gcc.target/aarch64/fmls-intrinsic.c: Likewise.
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* gcc.target/aarch64/mls-intrinsic.c: Likewise.
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2013-09-16 James Greenhalgh <james.greenhalgh@arm.com>
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* gcc.target/aarch64/mul_intrinsic_1.c: New.
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@ -0,0 +1,116 @@
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/* { dg-do run } */
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/* { dg-options "-O3 --save-temps" } */
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#include <arm_neon.h>
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#define DELTA 0.0001
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extern double fabs (double);
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extern void abort (void);
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#define TEST_VMLA(q1, q2, size, in1_lanes, in2_lanes) \
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static void \
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test_vfma##q1##_lane##q2##_f##size (float##size##_t * res, \
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const float##size##_t *in1, \
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const float##size##_t *in2) \
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{ \
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float##size##x##in1_lanes##_t a = vld1##q1##_f##size (res); \
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float##size##x##in1_lanes##_t b = vld1##q1##_f##size (in1); \
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float##size##x##in2_lanes##_t c; \
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if (in2_lanes > 1) \
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{ \
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c = vld1##q2##_f##size (in2); \
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a = vfma##q1##_lane##q2##_f##size (a, b, c, 1); \
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} \
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else \
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{ \
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c = vld1##q2##_f##size (in2 + 1); \
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a = vfma##q1##_lane##q2##_f##size (a, b, c, 0); \
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} \
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vst1##q1##_f##size (res, a); \
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}
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#define BUILD_VARS(width, n_lanes, n_half_lanes) \
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TEST_VMLA ( , , width, n_half_lanes, n_half_lanes) \
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TEST_VMLA (q, , width, n_lanes, n_half_lanes) \
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TEST_VMLA ( , q, width, n_half_lanes, n_lanes) \
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TEST_VMLA (q, q, width, n_lanes, n_lanes) \
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BUILD_VARS (32, 4, 2)
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BUILD_VARS (64, 2, 1)
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#define POOL2 {0.0, 1.0}
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#define POOL4 {0.0, 1.0, 2.0, 3.0}
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#define EMPTY2 {0.0, 0.0}
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#define EMPTY4 {0.0, 0.0, 0.0, 0.0}
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#define BUILD_TEST(size, lanes) \
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static void \
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test_f##size (void) \
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{ \
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int i; \
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float##size##_t pool[lanes] = POOL##lanes; \
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float##size##_t res[lanes] = EMPTY##lanes; \
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float##size##_t res2[lanes] = EMPTY##lanes; \
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float##size##_t res3[lanes] = EMPTY##lanes; \
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float##size##_t res4[lanes] = EMPTY##lanes; \
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\
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/* Forecfully avoid optimization. */ \
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asm volatile ("" : : : "memory"); \
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test_vfma_lane_f##size (res, pool, pool); \
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for (i = 0; i < lanes / 2; i++) \
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if (fabs (res[i] - pool[i]) > DELTA) \
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abort (); \
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\
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/* Forecfully avoid optimization. */ \
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asm volatile ("" : : : "memory"); \
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test_vfmaq_lane_f##size (res2, pool, pool); \
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||||
for (i = 0; i < lanes; i++) \
|
||||
if (fabs (res2[i] - pool[i]) > DELTA) \
|
||||
abort (); \
|
||||
\
|
||||
/* Forecfully avoid optimization. */ \
|
||||
asm volatile ("" : : : "memory"); \
|
||||
test_vfma_laneq_f##size (res3, pool, pool); \
|
||||
for (i = 0; i < lanes / 2; i++) \
|
||||
if (fabs (res3[i] - pool[i]) > DELTA) \
|
||||
abort (); \
|
||||
\
|
||||
/* Forecfully avoid optimization. */ \
|
||||
asm volatile ("" : : : "memory"); \
|
||||
test_vfmaq_laneq_f##size (res4, pool, pool); \
|
||||
for (i = 0; i < lanes; i++) \
|
||||
if (fabs (res4[i] - pool[i]) > DELTA) \
|
||||
abort (); \
|
||||
}
|
||||
|
||||
BUILD_TEST (32, 4)
|
||||
BUILD_TEST (64, 2)
|
||||
|
||||
int
|
||||
main (int argc, char **argv)
|
||||
{
|
||||
test_f32 ();
|
||||
test_f64 ();
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* vfma_laneq_f32.
|
||||
vfma_lane_f32. */
|
||||
/* { dg-final { scan-assembler-times "fmla\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s, v\[0-9\]+\.2s\\\[\[0-9\]+\\\]" 2 } } */
|
||||
|
||||
/* vfmaq_lane_f32.
|
||||
vfmaq_laneq_f32. */
|
||||
/* { dg-final { scan-assembler-times "fmla\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.4s\\\[\[0-9\]+\\\]" 2 } } */
|
||||
|
||||
/* vfma_lane_f64. */
|
||||
/* { dg-final { scan-assembler-times "fmadd\\td\[0-9\]+\, d\[0-9\]+\, d\[0-9\]+\, d\[0-9\]+" 1 } } */
|
||||
|
||||
/* vfmaq_lane_f64.
|
||||
vfma_laneq_f64.
|
||||
vfmaq_laneq_f64. */
|
||||
/* { dg-final { scan-assembler-times "fmla\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d, v\[0-9\]+\.2d\\\[\[0-9\]+\\\]" 3 } } */
|
||||
|
||||
/* { dg-final { cleanup-saved-temps } } */
|
||||
|
||||
|
|
@ -0,0 +1,117 @@
|
|||
/* { dg-do run } */
|
||||
/* { dg-options "-O3 --save-temps" } */
|
||||
|
||||
#include <arm_neon.h>
|
||||
|
||||
#define DELTA 0.0001
|
||||
|
||||
extern double fabs (double);
|
||||
|
||||
extern void abort (void);
|
||||
|
||||
#define TEST_VMLS(q1, q2, size, in1_lanes, in2_lanes) \
|
||||
static void \
|
||||
test_vfms##q1##_lane##q2##_f##size (float##size##_t * res, \
|
||||
const float##size##_t *in1, \
|
||||
const float##size##_t *in2) \
|
||||
{ \
|
||||
float##size##x##in1_lanes##_t a = vld1##q1##_f##size (res); \
|
||||
float##size##x##in1_lanes##_t b = vld1##q1##_f##size (in1); \
|
||||
float##size##x##in2_lanes##_t c; \
|
||||
if (in2_lanes > 1) \
|
||||
{ \
|
||||
c = vld1##q2##_f##size (in2); \
|
||||
a = vfms##q1##_lane##q2##_f##size (a, b, c, 1); \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
c = vld1##q2##_f##size (in2 + 1); \
|
||||
a = vfms##q1##_lane##q2##_f##size (a, b, c, 0); \
|
||||
} \
|
||||
vst1##q1##_f##size (res, a); \
|
||||
}
|
||||
|
||||
#define BUILD_VARS(width, n_lanes, n_half_lanes) \
|
||||
TEST_VMLS ( , , width, n_half_lanes, n_half_lanes) \
|
||||
TEST_VMLS (q, , width, n_lanes, n_half_lanes) \
|
||||
TEST_VMLS ( , q, width, n_half_lanes, n_lanes) \
|
||||
TEST_VMLS (q, q, width, n_lanes, n_lanes) \
|
||||
|
||||
BUILD_VARS (32, 4, 2)
|
||||
BUILD_VARS (64, 2, 1)
|
||||
|
||||
#define POOL2 {0.0, 1.0}
|
||||
#define POOL4 {0.0, 1.0, 2.0, 3.0}
|
||||
#define EMPTY2 {0.0, 0.0}
|
||||
#define EMPTY4 {0.0, 0.0, 0.0, 0.0}
|
||||
|
||||
#define BUILD_TEST(size, lanes) \
|
||||
static void \
|
||||
test_f##size (void) \
|
||||
{ \
|
||||
int i; \
|
||||
float##size##_t pool[lanes] = POOL##lanes; \
|
||||
float##size##_t res[lanes] = EMPTY##lanes; \
|
||||
float##size##_t res2[lanes] = EMPTY##lanes; \
|
||||
float##size##_t res3[lanes] = EMPTY##lanes; \
|
||||
float##size##_t res4[lanes] = EMPTY##lanes; \
|
||||
\
|
||||
/* Forecfully avoid optimization. */ \
|
||||
asm volatile ("" : : : "memory"); \
|
||||
test_vfms_lane_f##size (res, pool, pool); \
|
||||
asm volatile ("" : :"Q" (res) : "memory"); \
|
||||
for (i = 0; i < lanes / 2; i++) \
|
||||
if (fabs (res[i] + pool[i]) > DELTA) \
|
||||
abort (); \
|
||||
\
|
||||
/* Forecfully avoid optimization. */ \
|
||||
test_vfmsq_lane_f##size (res2, pool, pool); \
|
||||
asm volatile ("" : :"Q" (res2) : "memory"); \
|
||||
for (i = 0; i < lanes; i++) \
|
||||
if (fabs (res2[i] + pool[i]) > DELTA) \
|
||||
abort (); \
|
||||
\
|
||||
/* Forecfully avoid optimization. */ \
|
||||
test_vfms_laneq_f##size (res3, pool, pool); \
|
||||
asm volatile ("" : :"Q" (res3) : "memory"); \
|
||||
for (i = 0; i < lanes / 2; i++) \
|
||||
if (fabs (res3[i] + pool[i]) > DELTA) \
|
||||
abort (); \
|
||||
\
|
||||
/* Forecfully avoid optimization. */ \
|
||||
test_vfmsq_laneq_f##size (res4, pool, pool); \
|
||||
asm volatile ("" : :"Q" (res4) : "memory"); \
|
||||
for (i = 0; i < lanes; i++) \
|
||||
if (fabs (res4[i] + pool[i]) > DELTA) \
|
||||
abort (); \
|
||||
}
|
||||
|
||||
BUILD_TEST (32, 4)
|
||||
BUILD_TEST (64, 2)
|
||||
|
||||
int
|
||||
main (int argc, char **argv)
|
||||
{
|
||||
test_f32 ();
|
||||
test_f64 ();
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* vfms_laneq_f32.
|
||||
vfms_lane_f32. */
|
||||
/* { dg-final { scan-assembler-times "fmls\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s, v\[0-9\]+\.2s\\\[\[0-9\]+\\\]" 2 } } */
|
||||
|
||||
/* vfmsq_lane_f32.
|
||||
vfmsq_laneq_f32. */
|
||||
/* { dg-final { scan-assembler-times "fmls\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.4s\\\[\[0-9\]+\\\]" 2 } } */
|
||||
|
||||
/* vfms_lane_f64. */
|
||||
/* { dg-final { scan-assembler-times "fmsub\\td\[0-9\]+\, d\[0-9\]+\, d\[0-9\]+\, d\[0-9\]+" 1 } } */
|
||||
|
||||
/* vfmsq_lane_f64.
|
||||
vfms_laneq_f64.
|
||||
vfmsq_laneq_f64. */
|
||||
/* { dg-final { scan-assembler-times "fmls\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d, v\[0-9\]+\.2d\\\[\[0-9\]+\\\]" 3 } } */
|
||||
|
||||
/* { dg-final { cleanup-saved-temps } } */
|
||||
|
||||
|
|
@ -0,0 +1,84 @@
|
|||
/* { dg-do run } */
|
||||
/* { dg-options "-O3 --save-temps" } */
|
||||
|
||||
#include <arm_neon.h>
|
||||
|
||||
extern void abort (void);
|
||||
|
||||
#define MAPs(size, xx) int##size##xx##_t
|
||||
#define MAPu(size, xx) uint##size##xx##_t
|
||||
|
||||
|
||||
#define TEST_VMLA(q, su, size, in1_lanes, in2_lanes) \
|
||||
static void \
|
||||
test_vmlaq_lane##q##_##su##size (MAP##su (size, ) * res, \
|
||||
const MAP##su(size, ) *in1, \
|
||||
const MAP##su(size, ) *in2) \
|
||||
{ \
|
||||
MAP##su (size, x##in1_lanes) a = vld1q_##su##size (res); \
|
||||
MAP##su (size, x##in1_lanes) b = vld1q_##su##size (in1); \
|
||||
MAP##su (size, x##in2_lanes) c = vld1##q##_##su##size (in2); \
|
||||
a = vmlaq_lane##q##_##su##size (a, b, c, 1); \
|
||||
vst1q_##su##size (res, a); \
|
||||
}
|
||||
|
||||
#define BUILD_VARS(width, n_lanes, n_half_lanes) \
|
||||
TEST_VMLA (, s, width, n_lanes, n_half_lanes) \
|
||||
TEST_VMLA (q, s, width, n_lanes, n_lanes) \
|
||||
TEST_VMLA (, u, width, n_lanes, n_half_lanes) \
|
||||
TEST_VMLA (q, u, width, n_lanes, n_lanes) \
|
||||
|
||||
BUILD_VARS (32, 4, 2)
|
||||
BUILD_VARS (16, 8, 4)
|
||||
|
||||
#define POOL4 {0, 1, 2, 3}
|
||||
#define POOL8 {0, 1, 2, 3, 4, 5, 6, 7}
|
||||
#define EMPTY4 {0, 0, 0, 0}
|
||||
#define EMPTY8 {0, 0, 0, 0, 0, 0, 0, 0}
|
||||
|
||||
#define BUILD_TEST(su, size, lanes) \
|
||||
static void \
|
||||
test_##su##size (void) \
|
||||
{ \
|
||||
int i; \
|
||||
MAP##su (size,) pool[lanes] = POOL##lanes; \
|
||||
MAP##su (size,) res[lanes] = EMPTY##lanes; \
|
||||
MAP##su (size,) res2[lanes] = EMPTY##lanes; \
|
||||
\
|
||||
/* Forecfully avoid optimization. */ \
|
||||
asm volatile ("" : : : "memory"); \
|
||||
test_vmlaq_lane_##su##size (res, pool, pool); \
|
||||
for (i = 0; i < lanes; i++) \
|
||||
if (res[i] != pool[i]) \
|
||||
abort (); \
|
||||
\
|
||||
/* Forecfully avoid optimization. */ \
|
||||
asm volatile ("" : : : "memory"); \
|
||||
test_vmlaq_laneq_##su##size (res2, pool, pool); \
|
||||
for (i = 0; i < lanes; i++) \
|
||||
if (res2[i] != pool[i]) \
|
||||
abort (); \
|
||||
}
|
||||
|
||||
#undef BUILD_VARS
|
||||
#define BUILD_VARS(size, lanes) \
|
||||
BUILD_TEST (s, size, lanes) \
|
||||
BUILD_TEST (u, size, lanes)
|
||||
|
||||
BUILD_VARS (32, 4)
|
||||
BUILD_VARS (16, 8)
|
||||
|
||||
int
|
||||
main (int argc, char **argv)
|
||||
{
|
||||
test_s32 ();
|
||||
test_u32 ();
|
||||
test_s16 ();
|
||||
test_u16 ();
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "mla\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.4s\\\[\[0-9\]+\\\]" 4 } } */
|
||||
/* { dg-final { scan-assembler-times "mla\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h, v\[0-9\]+\.8h\\\[\[0-9\]+\\\]" 4 } } */
|
||||
/* { dg-final { cleanup-saved-temps } } */
|
||||
|
||||
|
|
@ -0,0 +1,89 @@
|
|||
/* { dg-do run } */
|
||||
/* { dg-options "-O3 --save-temps" } */
|
||||
|
||||
#include <arm_neon.h>
|
||||
|
||||
extern void abort (void);
|
||||
|
||||
#define MAPs(size, xx) int##size##xx##_t
|
||||
#define MAPu(size, xx) uint##size##xx##_t
|
||||
|
||||
|
||||
#define TEST_VMLS(q, su, size, in1_lanes, in2_lanes) \
|
||||
static void \
|
||||
test_vmlsq_lane##q##_##su##size (MAP##su (size, ) * res, \
|
||||
const MAP##su(size, ) *in1, \
|
||||
const MAP##su(size, ) *in2) \
|
||||
{ \
|
||||
MAP##su (size, x##in1_lanes) a = vld1q_##su##size (res); \
|
||||
MAP##su (size, x##in1_lanes) b = vld1q_##su##size (in1); \
|
||||
MAP##su (size, x##in2_lanes) c = vld1##q##_##su##size (in2); \
|
||||
a = vmlsq_lane##q##_##su##size (a, b, c, 1); \
|
||||
vst1q_##su##size (res, a); \
|
||||
}
|
||||
|
||||
#define BUILD_VARS(width, n_lanes, n_half_lanes) \
|
||||
TEST_VMLS (, s, width, n_lanes, n_half_lanes) \
|
||||
TEST_VMLS (q, s, width, n_lanes, n_lanes) \
|
||||
TEST_VMLS (, u, width, n_lanes, n_half_lanes) \
|
||||
TEST_VMLS (q, u, width, n_lanes, n_lanes) \
|
||||
|
||||
BUILD_VARS (32, 4, 2)
|
||||
BUILD_VARS (16, 8, 4)
|
||||
|
||||
#define MAP_OPs +
|
||||
#define MAP_OPu -
|
||||
|
||||
#define POOL4 {0, 1, 2, 3}
|
||||
#define POOL8 {0, 1, 2, 3, 4, 5, 6, 7}
|
||||
#define EMPTY4s {0, 0, 0, 0}
|
||||
#define EMPTY8s {0, 0, 0, 0, 0, 0, 0, 0}
|
||||
#define EMPTY4u {0, 2, 4, 6}
|
||||
#define EMPTY8u {0, 2, 4, 6, 8, 10, 12, 14}
|
||||
|
||||
#define BUILD_TEST(su, size, lanes) \
|
||||
static void \
|
||||
test_##su##size (void) \
|
||||
{ \
|
||||
int i; \
|
||||
MAP##su (size,) pool[lanes] = POOL##lanes; \
|
||||
MAP##su (size,) res[lanes] = EMPTY##lanes##su; \
|
||||
MAP##su (size,) res2[lanes] = EMPTY##lanes##su; \
|
||||
\
|
||||
/* Forecfully avoid optimization. */ \
|
||||
asm volatile ("" : : : "memory"); \
|
||||
test_vmlsq_lane_##su##size (res, pool, pool); \
|
||||
for (i = 0; i < lanes; i++) \
|
||||
if (res[i] MAP_OP##su pool[i] != 0) \
|
||||
abort (); \
|
||||
\
|
||||
/* Forecfully avoid optimization. */ \
|
||||
asm volatile ("" : : : "memory"); \
|
||||
test_vmlsq_laneq_##su##size (res2, pool, pool); \
|
||||
for (i = 0; i < lanes; i++) \
|
||||
if (res2[i] MAP_OP##su pool[i] != 0) \
|
||||
abort (); \
|
||||
}
|
||||
|
||||
#undef BUILD_VARS
|
||||
#define BUILD_VARS(size, lanes) \
|
||||
BUILD_TEST (s, size, lanes) \
|
||||
BUILD_TEST (u, size, lanes)
|
||||
|
||||
BUILD_VARS (32, 4)
|
||||
BUILD_VARS (16, 8)
|
||||
|
||||
int
|
||||
main (int argc, char **argv)
|
||||
{
|
||||
test_s32 ();
|
||||
test_u32 ();
|
||||
test_s16 ();
|
||||
test_u16 ();
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "mls\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.4s\\\[\[0-9\]+\\\]" 4 } } */
|
||||
/* { dg-final { scan-assembler-times "mls\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h, v\[0-9\]+\.8h\\\[\[0-9\]+\\\]" 4 } } */
|
||||
/* { dg-final { cleanup-saved-temps } } */
|
||||
|
||||
Loading…
Reference in New Issue