From 82975c743eac89c9593bfe68946b083949c27fb1 Mon Sep 17 00:00:00 2001
From: Andrew Stubbs <ams@codesourcery.com>
Date: Thu, 19 Dec 2019 17:00:54 +0000
Subject: [PATCH] Allow constants in amdgcn extends and truncates

2019-12-19  Andrew Stubbs  <ams@codesourcery.com>

	gcc/
	* config/gcn/gcn-valu.md
	(<convop><VEC_ALL1REG_INT_ALT:mode><VEC_ALL1REG_INT_MODE:mode>2<exec>):
	Change input predcate to gcn_alu_operand.
	(extend<VEC_ALL1REG_INT_ALT:mode><VEC_ALL1REG_INT_MODE:mode>2<exec>):
	Likewise.
	(truncv64di<mode>2): Likewise.
	(truncv64di<mode>2_exec): Likewise.
	(<convop><mode>v64di2): Likewise.
	(<convop><mode>v64di2_exec): Likewise.

From-SVN: r279587
---
 gcc/ChangeLog              | 12 ++++++++++++
 gcc/config/gcn/gcn-valu.md | 24 ++++++++++++------------
 2 files changed, 24 insertions(+), 12 deletions(-)

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 6340deade11..361697e5407 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,15 @@
+2019-12-19  Andrew Stubbs  <ams@codesourcery.com>
+
+	* config/gcn/gcn-valu.md
+	(<convop><VEC_ALL1REG_INT_ALT:mode><VEC_ALL1REG_INT_MODE:mode>2<exec>):
+	Change input predcate to gcn_alu_operand.
+	(extend<VEC_ALL1REG_INT_ALT:mode><VEC_ALL1REG_INT_MODE:mode>2<exec>):
+	Likewise.
+	(truncv64di<mode>2): Likewise.
+	(truncv64di<mode>2_exec): Likewise.
+	(<convop><mode>v64di2): Likewise.
+	(<convop><mode>v64di2_exec): Likewise.
+
 2019-12-19  Andrew Stubbs  <ams@codesourcery.com>
 
 	* config/gcn/gcn-valu.md (*plus_carry_dpp_shr_<mode>): Rename to ...
diff --git a/gcc/config/gcn/gcn-valu.md b/gcc/config/gcn/gcn-valu.md
index 369aae5bfc5..98dc3e0cb5f 100644
--- a/gcc/config/gcn/gcn-valu.md
+++ b/gcc/config/gcn/gcn-valu.md
@@ -2491,18 +2491,18 @@
 	(truncate "trunc")])
 
 (define_insn "<convop><VEC_ALL1REG_INT_ALT:mode><VEC_ALL1REG_INT_MODE:mode>2<exec>"
-  [(set (match_operand:VEC_ALL1REG_INT_MODE 0 "register_operand"  "=v")
+  [(set (match_operand:VEC_ALL1REG_INT_MODE 0 "register_operand" "=v")
         (zero_convert:VEC_ALL1REG_INT_MODE
-	  (match_operand:VEC_ALL1REG_INT_ALT 1 "register_operand" " v")))]
+	  (match_operand:VEC_ALL1REG_INT_ALT 1 "gcn_alu_operand" " v")))]
   ""
   "v_mov_b32_sdwa\t%0, %1 dst_sel:<VEC_ALL1REG_INT_MODE:sdwa> dst_unused:UNUSED_PAD src0_sel:<VEC_ALL1REG_INT_ALT:sdwa>"
   [(set_attr "type" "vop_sdwa")
    (set_attr "length" "8")])
 
 (define_insn "extend<VEC_ALL1REG_INT_ALT:mode><VEC_ALL1REG_INT_MODE:mode>2<exec>"
-  [(set (match_operand:VEC_ALL1REG_INT_MODE 0 "register_operand"  "=v")
+  [(set (match_operand:VEC_ALL1REG_INT_MODE 0 "register_operand" "=v")
         (sign_extend:VEC_ALL1REG_INT_MODE
-	  (match_operand:VEC_ALL1REG_INT_ALT 1 "register_operand" " v")))]
+	  (match_operand:VEC_ALL1REG_INT_ALT 1 "gcn_alu_operand" " v")))]
   ""
   "v_mov_b32_sdwa\t%0, sext(%1) src0_sel:<VEC_ALL1REG_INT_ALT:sdwa>"
   [(set_attr "type" "vop_sdwa")
@@ -2515,7 +2515,7 @@
 (define_insn_and_split "truncv64di<mode>2"
   [(set (match_operand:VEC_ALL1REG_INT_MODE 0 "register_operand" "=v")
 	(truncate:VEC_ALL1REG_INT_MODE
-	  (match_operand:V64DI 1 "register_operand"              " v")))]
+	  (match_operand:V64DI 1 "gcn_alu_operand"		 " v")))]
   ""
   "#"
   "reload_completed"
@@ -2536,7 +2536,7 @@
   [(set (match_operand:VEC_ALL1REG_INT_MODE 0 "register_operand"       "=v")
 	(vec_merge:VEC_ALL1REG_INT_MODE
 	  (truncate:VEC_ALL1REG_INT_MODE
-	    (match_operand:V64DI 1 "register_operand"		       " v"))
+	    (match_operand:V64DI 1 "gcn_alu_operand"		       " v"))
 	  (match_operand:VEC_ALL1REG_INT_MODE 2 "gcn_alu_or_unspec_operand" 
 								       "U0")
 	  (match_operand:DI 3 "gcn_exec_operand"		       " e")))]
@@ -2559,9 +2559,9 @@
    (set_attr "length" "4")])
 
 (define_insn_and_split "<convop><mode>v64di2"
-  [(set (match_operand:V64DI 0 "register_operand"		   "=v")
+  [(set (match_operand:V64DI 0 "register_operand"		  "=v")
 	(any_extend:V64DI
-	  (match_operand:VEC_ALL1REG_INT_MODE 1 "register_operand" " v")))]
+	  (match_operand:VEC_ALL1REG_INT_MODE 1 "gcn_alu_operand" " v")))]
   ""
   "#"
   "reload_completed"
@@ -2584,12 +2584,12 @@
    (set_attr "length" "12")])
 
 (define_insn_and_split "<convop><mode>v64di2_exec"
-  [(set (match_operand:V64DI 0 "register_operand"		     "=v")
+  [(set (match_operand:V64DI 0 "register_operand"		    "=v")
 	(vec_merge:V64DI
 	  (any_extend:V64DI
-	    (match_operand:VEC_ALL1REG_INT_MODE 1 "register_operand" " v"))
-	  (match_operand:V64DI 2 "gcn_alu_or_unspec_operand"	     "U0")
-	  (match_operand:DI 3 "gcn_exec_operand"		     " e")))]
+	    (match_operand:VEC_ALL1REG_INT_MODE 1 "gcn_alu_operand" " v"))
+	  (match_operand:V64DI 2 "gcn_alu_or_unspec_operand"	    "U0")
+	  (match_operand:DI 3 "gcn_exec_operand"		    " e")))]
   ""
   "#"
   "reload_completed"