Kazu Hirata
Kazu Hirata
parent
508ea1c5fa
commit
832a3292d9
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@ -1,3 +1,7 @@
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2004-02-28 Kazu Hirata <kazu@cs.umass.edu>
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* config/sh/sh.c: Fix formatting.
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2004-02-28 Kazu Hirata <kazu@cs.umass.edu>
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* config/sh/sh.c: Convert to ISO-C.
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@ -1324,7 +1324,7 @@ output_branch (int logic, rtx insn, rtx *operands)
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output_asm_insn ("bra\t%l0", &op0);
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fprintf (asm_out_file, "\tnop\n");
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(*targetm.asm_out.internal_label)(asm_out_file, "LF", label);
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(*targetm.asm_out.internal_label) (asm_out_file, "LF", label);
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return "";
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}
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@ -1567,7 +1567,7 @@ shift_insns_rtx (rtx insn)
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case ASHIFT:
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return shift_insns[shift_count];
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default:
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abort();
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abort ();
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}
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}
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@ -1682,7 +1682,7 @@ addsubcosts (rtx x)
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/* Fall through. */
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default:
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return 5;
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return 5;
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}
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/* Any other constant requires a 2 cycle pc-relative load plus an
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@ -2089,7 +2089,7 @@ shl_and_kind (rtx left_rtx, rtx mask_rtx, int *attrp)
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mask = (unsigned HOST_WIDE_INT) INTVAL (mask_rtx) >> left;
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else
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mask = (unsigned HOST_WIDE_INT) GET_MODE_MASK (SImode) >> left;
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/* Can this be expressed as a right shift / left shift pair ? */
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/* Can this be expressed as a right shift / left shift pair? */
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lsb = ((mask ^ (mask - 1)) >> 1) + 1;
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right = exact_log2 (lsb);
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mask2 = ~(mask + lsb - 1);
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@ -2103,15 +2103,15 @@ shl_and_kind (rtx left_rtx, rtx mask_rtx, int *attrp)
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int late_right = exact_log2 (lsb2);
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best_cost = shift_insns[left + late_right] + shift_insns[late_right];
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}
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/* Try to use zero extend */
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/* Try to use zero extend. */
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if (mask2 == ~(lsb2 - 1))
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{
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int width, first;
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for (width = 8; width <= 16; width += 8)
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{
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/* Can we zero-extend right away? */
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if (lsb2 == (unsigned HOST_WIDE_INT)1 << width)
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/* Can we zero-extend right away? */
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if (lsb2 == (unsigned HOST_WIDE_INT) 1 << width)
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{
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cost
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= 1 + ext_shift_insns[right] + ext_shift_insns[left + right];
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@ -2143,7 +2143,7 @@ shl_and_kind (rtx left_rtx, rtx mask_rtx, int *attrp)
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best_len = cost;
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if (attrp)
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attrp[2] = first;
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}
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}
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}
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}
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}
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@ -2164,7 +2164,7 @@ shl_and_kind (rtx left_rtx, rtx mask_rtx, int *attrp)
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}
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}
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/* Try to use a scratch register to hold the AND operand. */
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can_ext = ((mask << left) & ((unsigned HOST_WIDE_INT)3 << 30)) == 0;
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can_ext = ((mask << left) & ((unsigned HOST_WIDE_INT) 3 << 30)) == 0;
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for (i = 0; i <= 2; i++)
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{
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if (i > right)
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@ -2229,7 +2229,7 @@ gen_shl_and (rtx dest, rtx left_rtx, rtx mask_rtx, rtx source)
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unsigned HOST_WIDE_INT mask;
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int kind = shl_and_kind (left_rtx, mask_rtx, attributes);
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int right, total_shift;
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void (*shift_gen_fun) (int, rtx*) = gen_shifty_hi_op;
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void (*shift_gen_fun) (int, rtx *) = gen_shifty_hi_op;
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right = attributes[0];
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total_shift = INTVAL (left_rtx) + right;
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@ -2246,10 +2246,10 @@ gen_shl_and (rtx dest, rtx left_rtx, rtx mask_rtx, rtx source)
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if (first < 0)
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{
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emit_insn ((mask << right) <= 0xff
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? gen_zero_extendqisi2(dest,
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gen_lowpart (QImode, source))
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: gen_zero_extendhisi2(dest,
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gen_lowpart (HImode, source)));
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? gen_zero_extendqisi2 (dest,
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gen_lowpart (QImode, source))
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: gen_zero_extendhisi2 (dest,
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gen_lowpart (HImode, source)));
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source = dest;
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}
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if (source != dest)
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@ -2269,8 +2269,8 @@ gen_shl_and (rtx dest, rtx left_rtx, rtx mask_rtx, rtx source)
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}
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if (first >= 0)
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emit_insn (mask <= 0xff
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? gen_zero_extendqisi2(dest, gen_lowpart (QImode, dest))
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: gen_zero_extendhisi2(dest, gen_lowpart (HImode, dest)));
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? gen_zero_extendqisi2 (dest, gen_lowpart (QImode, dest))
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: gen_zero_extendhisi2 (dest, gen_lowpart (HImode, dest)));
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if (total_shift > 0)
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{
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operands[2] = GEN_INT (total_shift);
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@ -2284,8 +2284,8 @@ gen_shl_and (rtx dest, rtx left_rtx, rtx mask_rtx, rtx source)
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/* If the topmost bit that matters is set, set the topmost bits
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that don't matter. This way, we might be able to get a shorter
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signed constant. */
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if (mask & ((HOST_WIDE_INT)1 << (31 - total_shift)))
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mask |= (HOST_WIDE_INT)~0 << (31 - total_shift);
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if (mask & ((HOST_WIDE_INT) 1 << (31 - total_shift)))
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mask |= (HOST_WIDE_INT) ~0 << (31 - total_shift);
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case 2:
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/* Don't expand fine-grained when combining, because that will
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make the pattern fail. */
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@ -2502,8 +2502,8 @@ gen_shl_sext (rtx dest, rtx left_rtx, rtx size_rtx, rtx source)
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gen_shifty_hi_op (ASHIFT, operands);
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}
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emit_insn (kind & 1
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? gen_extendqisi2(dest, gen_lowpart (QImode, dest))
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: gen_extendhisi2(dest, gen_lowpart (HImode, dest)));
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? gen_extendqisi2 (dest, gen_lowpart (QImode, dest))
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: gen_extendhisi2 (dest, gen_lowpart (HImode, dest)));
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if (kind <= 2)
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{
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if (shift2)
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@ -2824,7 +2824,7 @@ dump_table (rtx scan)
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{
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lab = XEXP (ref, 0);
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emit_insn_before (gen_consttable_window_end (lab),
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align_insn);
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align_insn);
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}
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delete_insn (align_insn);
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align_insn = NULL_RTX;
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@ -3722,7 +3722,7 @@ barrier_align (rtx barrier_or_label)
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the table to the minimum for proper code alignment. */
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return ((TARGET_SMALLCODE
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|| ((unsigned) XVECLEN (pat, 1) * GET_MODE_SIZE (GET_MODE (pat))
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<= (unsigned)1 << (CACHE_LOG - 2)))
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<= (unsigned) 1 << (CACHE_LOG - 2)))
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? 1 << TARGET_SHMEDIA : align_jumps_log);
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}
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@ -4813,7 +4813,7 @@ push_regs (HARD_REG_SET *mask, int interrupt_handler)
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HARD_REG_SET unsaved;
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push (FPSCR_REG);
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COMPL_HARD_REG_SET(unsaved, *mask);
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COMPL_HARD_REG_SET (unsaved, *mask);
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fpscr_set_from_mem (NORMAL_MODE (FP_MODE), unsaved);
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skip_fpscr = 1;
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}
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@ -5103,8 +5103,8 @@ sh5_schedule_saves (HARD_REG_SET *live_regs_mask, save_schedule *schedule,
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&& ! (current_function_needs_context && i == STATIC_CHAIN_REGNUM)
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&& ! (current_function_calls_eh_return
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&& (i == EH_RETURN_STACKADJ_REGNO
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|| ((unsigned)i <= EH_RETURN_DATA_REGNO (0)
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&& (unsigned)i >= EH_RETURN_DATA_REGNO (3)))))
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|| ((unsigned) i <= EH_RETURN_DATA_REGNO (0)
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&& (unsigned) i >= EH_RETURN_DATA_REGNO (3)))))
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schedule->temps[tmpx++] = i;
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entry->reg = -1;
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entry->mode = VOIDmode;
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@ -6003,7 +6003,7 @@ sh_builtin_saveregs (void)
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regno = first_floatreg;
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if (regno & 1)
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{
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emit_insn (gen_addsi3 (fpregs, fpregs, GEN_INT (- UNITS_PER_WORD)));
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emit_insn (gen_addsi3 (fpregs, fpregs, GEN_INT (-UNITS_PER_WORD)));
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mem = gen_rtx_MEM (SFmode, fpregs);
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set_mem_alias_set (mem, alias_set);
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emit_move_insn (mem,
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@ -6016,7 +6016,7 @@ sh_builtin_saveregs (void)
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{
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rtx mem;
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emit_insn (gen_addsi3 (fpregs, fpregs, GEN_INT (- UNITS_PER_WORD)));
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emit_insn (gen_addsi3 (fpregs, fpregs, GEN_INT (-UNITS_PER_WORD)));
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mem = gen_rtx_MEM (SFmode, fpregs);
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set_mem_alias_set (mem, alias_set);
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emit_move_insn (mem,
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@ -6402,11 +6402,11 @@ sh_function_arg (CUMULATIVE_ARGS *ca, enum machine_mode mode,
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BASE_ARG_REG (mode)
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+ (ROUND_REG (*ca, mode) ^ 1)),
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const0_rtx);
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rtx r2 = gen_rtx_EXPR_LIST(VOIDmode,
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gen_rtx_REG (SFmode,
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BASE_ARG_REG (mode)
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+ ((ROUND_REG (*ca, mode) + 1) ^ 1)),
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GEN_INT (4));
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rtx r2 = gen_rtx_EXPR_LIST (VOIDmode,
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gen_rtx_REG (SFmode,
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BASE_ARG_REG (mode)
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+ ((ROUND_REG (*ca, mode) + 1) ^ 1)),
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GEN_INT (4));
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return gen_rtx_PARALLEL(SCmode, gen_rtvec(2, r1, r2));
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}
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@ -6473,144 +6473,144 @@ void
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sh_function_arg_advance (CUMULATIVE_ARGS *ca, enum machine_mode mode,
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tree type, int named)
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{
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if (ca->force_mem)
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ca->force_mem = 0;
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else if (TARGET_SH5)
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{
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tree type2 = (ca->byref && type
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? TREE_TYPE (type)
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: type);
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enum machine_mode mode2 = (ca->byref && type
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? TYPE_MODE (type2)
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: mode);
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int dwords = ((ca->byref
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? ca->byref
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: mode2 == BLKmode
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? int_size_in_bytes (type2)
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: GET_MODE_SIZE (mode2)) + 7) / 8;
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int numregs = MIN (dwords, NPARM_REGS (SImode)
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- ca->arg_count[(int) SH_ARG_INT]);
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if (ca->force_mem)
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ca->force_mem = 0;
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else if (TARGET_SH5)
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{
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tree type2 = (ca->byref && type
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? TREE_TYPE (type)
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: type);
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enum machine_mode mode2 = (ca->byref && type
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? TYPE_MODE (type2)
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: mode);
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int dwords = ((ca->byref
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? ca->byref
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: mode2 == BLKmode
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? int_size_in_bytes (type2)
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: GET_MODE_SIZE (mode2)) + 7) / 8;
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int numregs = MIN (dwords, NPARM_REGS (SImode)
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- ca->arg_count[(int) SH_ARG_INT]);
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if (numregs)
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{
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ca->arg_count[(int) SH_ARG_INT] += numregs;
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if (TARGET_SHCOMPACT
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&& SHCOMPACT_FORCE_ON_STACK (mode2, type2))
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{
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ca->call_cookie
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|= CALL_COOKIE_INT_REG (ca->arg_count[(int) SH_ARG_INT]
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- numregs, 1);
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/* N.B. We want this also for outgoing. */
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ca->stack_regs += numregs;
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}
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else if (ca->byref)
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{
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if (! ca->outgoing)
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ca->stack_regs += numregs;
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ca->byref_regs += numregs;
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ca->byref = 0;
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do
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ca->call_cookie
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|= CALL_COOKIE_INT_REG (ca->arg_count[(int) SH_ARG_INT]
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- numregs, 2);
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while (--numregs);
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ca->call_cookie
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|= CALL_COOKIE_INT_REG (ca->arg_count[(int) SH_ARG_INT]
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- 1, 1);
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}
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else if (dwords > numregs)
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{
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int pushregs = numregs;
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if (numregs)
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{
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ca->arg_count[(int) SH_ARG_INT] += numregs;
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if (TARGET_SHCOMPACT
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&& SHCOMPACT_FORCE_ON_STACK (mode2, type2))
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{
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ca->call_cookie
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|= CALL_COOKIE_INT_REG (ca->arg_count[(int) SH_ARG_INT]
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- numregs, 1);
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/* N.B. We want this also for outgoing. */
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ca->stack_regs += numregs;
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}
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else if (ca->byref)
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{
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if (! ca->outgoing)
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ca->stack_regs += numregs;
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ca->byref_regs += numregs;
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ca->byref = 0;
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do
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ca->call_cookie
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|= CALL_COOKIE_INT_REG (ca->arg_count[(int) SH_ARG_INT]
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- numregs, 2);
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while (--numregs);
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ca->call_cookie
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|= CALL_COOKIE_INT_REG (ca->arg_count[(int) SH_ARG_INT]
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- 1, 1);
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}
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else if (dwords > numregs)
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{
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int pushregs = numregs;
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if (TARGET_SHCOMPACT)
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ca->stack_regs += numregs;
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while (pushregs < NPARM_REGS (SImode) - 1
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&& (CALL_COOKIE_INT_REG_GET
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(ca->call_cookie,
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NPARM_REGS (SImode) - pushregs)
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== 1))
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{
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ca->call_cookie
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&= ~ CALL_COOKIE_INT_REG (NPARM_REGS (SImode)
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- pushregs, 1);
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pushregs++;
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}
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if (numregs == NPARM_REGS (SImode))
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ca->call_cookie
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|= CALL_COOKIE_INT_REG (0, 1)
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| CALL_COOKIE_STACKSEQ (numregs - 1);
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else
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ca->call_cookie
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|= CALL_COOKIE_STACKSEQ (numregs);
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}
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}
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if (GET_SH_ARG_CLASS (mode2) == SH_ARG_FLOAT
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&& (named || ! ca->prototype_p))
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{
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if (mode2 == SFmode && ca->free_single_fp_reg)
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ca->free_single_fp_reg = 0;
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else if (ca->arg_count[(int) SH_ARG_FLOAT]
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< NPARM_REGS (SFmode))
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{
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int numfpregs
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= MIN ((GET_MODE_SIZE (mode2) + 7) / 8 * 2,
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NPARM_REGS (SFmode)
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- ca->arg_count[(int) SH_ARG_FLOAT]);
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if (TARGET_SHCOMPACT)
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ca->stack_regs += numregs;
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while (pushregs < NPARM_REGS (SImode) - 1
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&& (CALL_COOKIE_INT_REG_GET
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(ca->call_cookie,
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NPARM_REGS (SImode) - pushregs)
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== 1))
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{
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ca->call_cookie
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&= ~ CALL_COOKIE_INT_REG (NPARM_REGS (SImode)
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- pushregs, 1);
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pushregs++;
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}
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if (numregs == NPARM_REGS (SImode))
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ca->call_cookie
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|= CALL_COOKIE_INT_REG (0, 1)
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| CALL_COOKIE_STACKSEQ (numregs - 1);
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else
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ca->call_cookie
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|= CALL_COOKIE_STACKSEQ (numregs);
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}
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}
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if (GET_SH_ARG_CLASS (mode2) == SH_ARG_FLOAT
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&& (named || ! ca->prototype_p))
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{
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if (mode2 == SFmode && ca->free_single_fp_reg)
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ca->free_single_fp_reg = 0;
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else if (ca->arg_count[(int) SH_ARG_FLOAT]
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< NPARM_REGS (SFmode))
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{
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int numfpregs
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= MIN ((GET_MODE_SIZE (mode2) + 7) / 8 * 2,
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NPARM_REGS (SFmode)
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- ca->arg_count[(int) SH_ARG_FLOAT]);
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ca->arg_count[(int) SH_ARG_FLOAT] += numfpregs;
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ca->arg_count[(int) SH_ARG_FLOAT] += numfpregs;
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if (TARGET_SHCOMPACT && ! ca->prototype_p)
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{
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if (ca->outgoing && numregs > 0)
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do
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{
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ca->call_cookie
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|= (CALL_COOKIE_INT_REG
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(ca->arg_count[(int) SH_ARG_INT]
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- numregs + ((numfpregs - 2) / 2),
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4 + (ca->arg_count[(int) SH_ARG_FLOAT]
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- numfpregs) / 2));
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}
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while (numfpregs -= 2);
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}
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else if (mode2 == SFmode && (named)
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&& (ca->arg_count[(int) SH_ARG_FLOAT]
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< NPARM_REGS (SFmode)))
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ca->free_single_fp_reg
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= FIRST_FP_PARM_REG - numfpregs
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+ ca->arg_count[(int) SH_ARG_FLOAT] + 1;
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}
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}
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return;
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}
|
||||
if (TARGET_SHCOMPACT && ! ca->prototype_p)
|
||||
{
|
||||
if (ca->outgoing && numregs > 0)
|
||||
do
|
||||
{
|
||||
ca->call_cookie
|
||||
|= (CALL_COOKIE_INT_REG
|
||||
(ca->arg_count[(int) SH_ARG_INT]
|
||||
- numregs + ((numfpregs - 2) / 2),
|
||||
4 + (ca->arg_count[(int) SH_ARG_FLOAT]
|
||||
- numfpregs) / 2));
|
||||
}
|
||||
while (numfpregs -= 2);
|
||||
}
|
||||
else if (mode2 == SFmode && (named)
|
||||
&& (ca->arg_count[(int) SH_ARG_FLOAT]
|
||||
< NPARM_REGS (SFmode)))
|
||||
ca->free_single_fp_reg
|
||||
= FIRST_FP_PARM_REG - numfpregs
|
||||
+ ca->arg_count[(int) SH_ARG_FLOAT] + 1;
|
||||
}
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
if ((TARGET_HITACHI || ca->renesas_abi) && TARGET_FPU_DOUBLE)
|
||||
{
|
||||
/* Note that we've used the skipped register. */
|
||||
if (mode == SFmode && ca->free_single_fp_reg)
|
||||
{
|
||||
ca->free_single_fp_reg = 0;
|
||||
return;
|
||||
}
|
||||
/* When we have a DF after an SF, there's an SF register that get
|
||||
skipped in order to align the DF value. We note this skipped
|
||||
register, because the next SF value will use it, and not the
|
||||
SF that follows the DF. */
|
||||
if (mode == DFmode
|
||||
&& ROUND_REG (*ca, DFmode) != ROUND_REG (*ca, SFmode))
|
||||
{
|
||||
ca->free_single_fp_reg = (ROUND_REG (*ca, SFmode)
|
||||
+ BASE_ARG_REG (mode));
|
||||
}
|
||||
}
|
||||
if ((TARGET_HITACHI || ca->renesas_abi) && TARGET_FPU_DOUBLE)
|
||||
{
|
||||
/* Note that we've used the skipped register. */
|
||||
if (mode == SFmode && ca->free_single_fp_reg)
|
||||
{
|
||||
ca->free_single_fp_reg = 0;
|
||||
return;
|
||||
}
|
||||
/* When we have a DF after an SF, there's an SF register that get
|
||||
skipped in order to align the DF value. We note this skipped
|
||||
register, because the next SF value will use it, and not the
|
||||
SF that follows the DF. */
|
||||
if (mode == DFmode
|
||||
&& ROUND_REG (*ca, DFmode) != ROUND_REG (*ca, SFmode))
|
||||
{
|
||||
ca->free_single_fp_reg = (ROUND_REG (*ca, SFmode)
|
||||
+ BASE_ARG_REG (mode));
|
||||
}
|
||||
}
|
||||
|
||||
if (! (TARGET_SH4 || ca->renesas_abi)
|
||||
|| PASS_IN_REG_P (*ca, mode, type))
|
||||
(ca->arg_count[(int) GET_SH_ARG_CLASS (mode)]
|
||||
= (ROUND_REG (*ca, mode)
|
||||
+ (mode == BLKmode
|
||||
? ROUND_ADVANCE (int_size_in_bytes (type))
|
||||
: ROUND_ADVANCE (GET_MODE_SIZE (mode)))));
|
||||
if (! (TARGET_SH4 || ca->renesas_abi)
|
||||
|| PASS_IN_REG_P (*ca, mode, type))
|
||||
(ca->arg_count[(int) GET_SH_ARG_CLASS (mode)]
|
||||
= (ROUND_REG (*ca, mode)
|
||||
+ (mode == BLKmode
|
||||
? ROUND_ADVANCE (int_size_in_bytes (type))
|
||||
: ROUND_ADVANCE (GET_MODE_SIZE (mode)))));
|
||||
}
|
||||
|
||||
/* The Renesas calling convention doesn't quite fit into this scheme since
|
||||
|
|
@ -7252,7 +7252,7 @@ and_operand (rtx op, enum machine_mode mode)
|
|||
&& mode == DImode
|
||||
&& GET_CODE (op) == CONST_INT
|
||||
&& CONST_OK_FOR_J16 (INTVAL (op)))
|
||||
return 1;
|
||||
return 1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -7429,7 +7429,8 @@ equality_comparison_operator (rtx op, enum machine_mode mode)
|
|||
&& (GET_CODE (op) == EQ || GET_CODE (op) == NE));
|
||||
}
|
||||
|
||||
int greater_comparison_operator (rtx op, enum machine_mode mode)
|
||||
int
|
||||
greater_comparison_operator (rtx op, enum machine_mode mode)
|
||||
{
|
||||
if (mode != VOIDmode && GET_MODE (op) == mode)
|
||||
return 0;
|
||||
|
|
@ -7445,7 +7446,8 @@ int greater_comparison_operator (rtx op, enum machine_mode mode)
|
|||
}
|
||||
}
|
||||
|
||||
int less_comparison_operator (rtx op, enum machine_mode mode)
|
||||
int
|
||||
less_comparison_operator (rtx op, enum machine_mode mode)
|
||||
{
|
||||
if (mode != VOIDmode && GET_MODE (op) == mode)
|
||||
return 0;
|
||||
|
|
@ -7508,7 +7510,7 @@ mextr_bit_offset (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
|
|||
if (GET_CODE (op) != CONST_INT)
|
||||
return 0;
|
||||
i = INTVAL (op);
|
||||
return i >= 1*8 && i <= 7*8 && (i & 7) == 0;
|
||||
return i >= 1 * 8 && i <= 7 * 8 && (i & 7) == 0;
|
||||
}
|
||||
|
||||
int
|
||||
|
|
@ -7571,7 +7573,7 @@ sh_rep_vec (rtx v, enum machine_mode mode)
|
|||
if (GET_MODE_UNIT_SIZE (mode) == 1)
|
||||
{
|
||||
y = XVECEXP (v, 0, i);
|
||||
for (i -= 2 ; i >= 0; i -= 2)
|
||||
for (i -= 2; i >= 0; i -= 2)
|
||||
if (! rtx_equal_p (XVECEXP (v, 0, i + 1), x)
|
||||
|| ! rtx_equal_p (XVECEXP (v, 0, i), y))
|
||||
return 0;
|
||||
|
|
@ -7791,7 +7793,7 @@ void
|
|||
expand_df_binop (rtx (*fun) (rtx, rtx, rtx, rtx), rtx *operands)
|
||||
{
|
||||
emit_df_insn ((*fun) (operands[0], operands[1], operands[2],
|
||||
get_fpscr_rtx ()));
|
||||
get_fpscr_rtx ()));
|
||||
}
|
||||
|
||||
/* ??? gcc does flow analysis strictly after common subexpression
|
||||
|
|
@ -8029,7 +8031,7 @@ nonpic_symbol_mentioned_p (rtx x)
|
|||
|| XINT (x, 1) == UNSPEC_GOTTPOFF
|
||||
|| XINT (x, 1) == UNSPEC_DTPOFF
|
||||
|| XINT (x, 1) == UNSPEC_PLT))
|
||||
return 0;
|
||||
return 0;
|
||||
|
||||
fmt = GET_RTX_FORMAT (GET_CODE (x));
|
||||
for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
|
||||
|
|
@ -8182,15 +8184,14 @@ int
|
|||
sh_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED,
|
||||
unsigned int new_reg)
|
||||
{
|
||||
|
||||
/* Interrupt functions can only use registers that have already been
|
||||
saved by the prologue, even if they would normally be
|
||||
call-clobbered. */
|
||||
/* Interrupt functions can only use registers that have already been
|
||||
saved by the prologue, even if they would normally be
|
||||
call-clobbered. */
|
||||
|
||||
if (sh_cfun_interrupt_handler_p () && !regs_ever_live[new_reg])
|
||||
return 0;
|
||||
return 0;
|
||||
|
||||
return 1;
|
||||
return 1;
|
||||
}
|
||||
|
||||
/* Function to update the integer COST
|
||||
|
|
@ -8266,7 +8267,7 @@ sh_adjust_cost (rtx insn, rtx link ATTRIBUTE_UNUSED, rtx dep_insn, int cost)
|
|||
&& get_attr_type (insn) == TYPE_DYN_SHIFT
|
||||
&& get_attr_any_int_load (dep_insn) == ANY_INT_LOAD_YES
|
||||
&& reg_overlap_mentioned_p (SET_DEST (PATTERN (dep_insn)),
|
||||
XEXP (SET_SRC (single_set(insn)),
|
||||
XEXP (SET_SRC (single_set (insn)),
|
||||
1)))
|
||||
cost++;
|
||||
/* When an LS group instruction with a latency of less than
|
||||
|
|
@ -8338,7 +8339,7 @@ sh_pr_n_sets (void)
|
|||
/* This Function returns nonzero if the DFA based scheduler interface
|
||||
is to be used. At present this is supported for the SH4 only. */
|
||||
static int
|
||||
sh_use_dfa_interface(void)
|
||||
sh_use_dfa_interface (void)
|
||||
{
|
||||
if (TARGET_HARD_SH4)
|
||||
return 1;
|
||||
|
|
@ -8349,7 +8350,7 @@ sh_use_dfa_interface(void)
|
|||
/* This function returns "2" to indicate dual issue for the SH4
|
||||
processor. To be used by the DFA pipeline description. */
|
||||
static int
|
||||
sh_issue_rate(void)
|
||||
sh_issue_rate (void)
|
||||
{
|
||||
if (TARGET_SUPERSCALAR)
|
||||
return 2;
|
||||
|
|
@ -8467,12 +8468,15 @@ swap_reorder (rtx *a, int n)
|
|||
a[i + 1] = insn;
|
||||
}
|
||||
|
||||
#define SCHED_REORDER(READY, N_READY) \
|
||||
do { if ((N_READY) == 2) \
|
||||
swap_reorder (READY, N_READY); \
|
||||
else if ((N_READY) > 2) \
|
||||
qsort (READY, N_READY, sizeof (rtx), rank_for_reorder); } \
|
||||
while (0)
|
||||
#define SCHED_REORDER(READY, N_READY) \
|
||||
do \
|
||||
{ \
|
||||
if ((N_READY) == 2) \
|
||||
swap_reorder (READY, N_READY); \
|
||||
else if ((N_READY) > 2) \
|
||||
qsort (READY, N_READY, sizeof (rtx), rank_for_reorder); \
|
||||
} \
|
||||
while (0)
|
||||
|
||||
/* Sort the ready list READY by ascending priority, using the SCHED_REORDER
|
||||
macro. */
|
||||
|
|
@ -8631,22 +8635,22 @@ sh_dfa_new_cycle (FILE *sched_dump ATTRIBUTE_UNUSED,
|
|||
int *sort_p)
|
||||
{
|
||||
if (reload_completed)
|
||||
return 0;
|
||||
return 0;
|
||||
|
||||
if (skip_cycles)
|
||||
{
|
||||
if ((clock_var - last_clock_var) < MAX_SKIPS)
|
||||
{
|
||||
*sort_p = 0;
|
||||
return 1;
|
||||
if ((clock_var - last_clock_var) < MAX_SKIPS)
|
||||
{
|
||||
*sort_p = 0;
|
||||
return 1;
|
||||
}
|
||||
/* If this is the last cycle we are skipping, allow reordering of R. */
|
||||
if ((clock_var - last_clock_var) == MAX_SKIPS)
|
||||
{
|
||||
*sort_p = 1;
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
/* If this is the last cycle we are skipping, allow reordering of R. */
|
||||
if ((clock_var - last_clock_var) == MAX_SKIPS)
|
||||
{
|
||||
*sort_p = 1;
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
|
||||
skip_cycles = 0;
|
||||
|
||||
|
|
@ -9195,16 +9199,16 @@ sh_cannot_change_mode_class (enum machine_mode from, enum machine_mode to,
|
|||
{
|
||||
if (GET_MODE_SIZE (from) != GET_MODE_SIZE (to))
|
||||
{
|
||||
if (TARGET_LITTLE_ENDIAN)
|
||||
{
|
||||
if (GET_MODE_SIZE (to) < 8 || GET_MODE_SIZE (from) < 8)
|
||||
return reg_classes_intersect_p (DF_REGS, class);
|
||||
}
|
||||
else
|
||||
{
|
||||
if (GET_MODE_SIZE (from) < 8)
|
||||
return reg_classes_intersect_p (DF_HI_REGS, class);
|
||||
}
|
||||
if (TARGET_LITTLE_ENDIAN)
|
||||
{
|
||||
if (GET_MODE_SIZE (to) < 8 || GET_MODE_SIZE (from) < 8)
|
||||
return reg_classes_intersect_p (DF_REGS, class);
|
||||
}
|
||||
else
|
||||
{
|
||||
if (GET_MODE_SIZE (from) < 8)
|
||||
return reg_classes_intersect_p (DF_HI_REGS, class);
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -9252,15 +9256,15 @@ sh_register_move_cost (enum machine_mode mode,
|
|||
return 4;
|
||||
|
||||
if ((REGCLASS_HAS_FP_REG (dstclass) && srcclass == MAC_REGS)
|
||||
|| (dstclass== MAC_REGS && REGCLASS_HAS_FP_REG (srcclass)))
|
||||
|| (dstclass == MAC_REGS && REGCLASS_HAS_FP_REG (srcclass)))
|
||||
return 9;
|
||||
|
||||
if ((REGCLASS_HAS_FP_REG (dstclass)
|
||||
&& REGCLASS_HAS_GENERAL_REG (srcclass))
|
||||
|| (REGCLASS_HAS_GENERAL_REG (dstclass)
|
||||
&& REGCLASS_HAS_FP_REG (srcclass)))
|
||||
return ((TARGET_SHMEDIA ? 4 : TARGET_FMOVD ? 8 : 12)
|
||||
* ((GET_MODE_SIZE (mode) + 7) / 8U));
|
||||
return ((TARGET_SHMEDIA ? 4 : TARGET_FMOVD ? 8 : 12)
|
||||
* ((GET_MODE_SIZE (mode) + 7) / 8U));
|
||||
|
||||
if ((dstclass == FPUL_REGS
|
||||
&& REGCLASS_HAS_GENERAL_REG (srcclass))
|
||||
|
|
@ -9430,7 +9434,7 @@ sh_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
|
|||
abort (); /* FIXME */
|
||||
emit_load_ptr (scratch0, offset_addr);
|
||||
|
||||
if (Pmode != ptr_mode)
|
||||
if (Pmode != ptr_mode)
|
||||
scratch0 = gen_rtx_TRUNCATE (ptr_mode, scratch0);
|
||||
emit_insn (gen_add2_insn (this, scratch0));
|
||||
}
|
||||
|
|
@ -9469,7 +9473,7 @@ sh_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
|
|||
sh_reorg ();
|
||||
|
||||
if (optimize > 0 && flag_delayed_branch)
|
||||
dbr_schedule (insns, dump_file);
|
||||
dbr_schedule (insns, dump_file);
|
||||
shorten_branches (insns);
|
||||
final_start_function (insns, file, 1);
|
||||
final (insns, file, 1, 0);
|
||||
|
|
|
|||
Loading…
Reference in New Issue