vxlib.c: Fix comment typos.
* config/vxlib.c: Fix comment typos. * config/alpha/alpha.c: Likewise. * config/arm/arm.c: Likewise. * config/arm/arm.md: Likewise. * config/c4x/c4x.c: Likewise. * config/c4x/c4x.md: Likewise. * config/cris/cris.h: Likewise. * config/cris/cris.md: Likewise. * config/fr30/fr30.c: Likewise. * config/fr30/fr30.h: Likewise. * config/fr30/fr30.md: Likewise. * config/frv/frv.c: Likewise. * config/frv/frv.md: Likewise. * config/frv/frvbegin.c: Likewise. * config/i386/athlon.md: Likewise. * config/i386/i386.c: Likewise. * config/i386/i386.md: Likewise. * config/i386/sco5.h: Likewise. * config/ia64/ia64.md: Likewise. * config/ip2k/ip2k.c: Likewise. * config/ip2k/ip2k.md: Likewise. * config/m68hc11/m68hc11.h: Likewise. * config/m68k/m68k.h: Likewise. * config/mips/mips.c: Likewise. * config/rs6000/rs6000.c: Likewise. * config/s390/s390.md: Likewise. * config/sh/sh.h: Likewise. * config/sparc/sparc.md: Likewise. * config/v850/v850.c: Likewise. * config/v850/v850.h: Likewise. * config/v850/v850.md: Likewise. * config/xtensa/xtensa.c: Likewise. From-SVN: r74596
This commit is contained in:
Kazu Hirata
parent
da1d7781e4
commit
839a499276
@ -6677,7 +6677,7 @@ alpha_expand_builtin (tree exp, rtx target,
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/* These variables are used for communication between the following functions.
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They indicate various things about the current function being compiled
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that are used to tell what kind of prologue, epilogue and procedure
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descriptior to generate. */
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descriptor to generate. */
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/* Nonzero if we need a stack procedure. */
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enum alpha_procedure_types {PT_NULL = 0, PT_REGISTER = 1, PT_STACK = 2};
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@ -8829,7 +8829,7 @@ alpha_align_insns (unsigned int max_align,
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int nop_count = (align - ofs) / 4;
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rtx where;
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/* Insert nops before labels, branches, and calls to truely merge
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/* Insert nops before labels, branches, and calls to truly merge
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the execution of the nops with the previous instruction group. */
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where = prev_nonnote_insn (i);
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if (where)
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@ -849,7 +849,7 @@ arm_override_options (void)
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{
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/* There's some dispute as to whether this should be 1 or 2. However,
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experiments seem to show that in pathological cases a setting of
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1 degrades less severly than a setting of 2. This could change if
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1 degrades less severely than a setting of 2. This could change if
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other parts of the compiler change their behavior. */
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arm_constant_limit = 1;
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@ -1051,7 +1051,7 @@ use_return_insn (int iscond, rtx sibling)
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triggers a bug on most SA-110 based devices, such that the stack
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pointer won't be correctly restored if the instruction takes a
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page fault. We work around this problem by poping r3 along with
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page fault. We work around this problem by popping r3 along with
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the other registers, since that is never slower than executing
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another instruction.
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@ -1230,7 +1230,7 @@
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(set_attr "type" "mult")]
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)
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;; Unnamed template to match long long multiply-accumlate (smlal)
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;; Unnamed template to match long long multiply-accumulate (smlal)
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(define_insn "*mulsidi3adddi"
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[(set (match_operand:DI 0 "s_register_operand" "=&r")
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@ -1267,7 +1267,7 @@
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(set_attr "predicable" "yes")]
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)
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;; Unnamed template to match long long unsigned multiply-accumlate (umlal)
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;; Unnamed template to match long long unsigned multiply-accumulate (umlal)
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(define_insn "*umulsidi3adddi"
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[(set (match_operand:DI 0 "s_register_operand" "=&r")
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@ -1088,7 +1088,7 @@ c4x_expand_epilogue(void)
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dont_pop_ar3 = 0; /* If we use ar3, we need to pop it. */
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if (size || current_function_args_size)
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{
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/* If we are ommitting the frame pointer, we still have
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/* If we are omitting the frame pointer, we still have
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to make space for it so the offsets are correct
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unless we don't use anything on the stack at all. */
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size += 1;
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@ -157,7 +157,7 @@
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; a register satisying the 'f' constraint is used as a dst operand,
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; the CC gets clobbered (except for LDFcond).
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; The ! in front of the 'b' constaint says to GCC to disparage the
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; The ! in front of the 'b' constraint says to GCC to disparage the
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; use of this constraint. The 'b' constraint applies only to the SP.
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; Note that we deal with the condition code CC like some of the RISC
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@ -173,7 +173,7 @@
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; delayed branch slots.
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; Since the C[34]x has many instructions that set the CC, we pay the
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; price of having to explicity define which insns clobber the CC
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; price of having to explicitly define which insns clobber the CC
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; (rather than using the macro NOTICE_UPDATE_CC).
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; Note that many patterns say that the CC is clobbered when in fact
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@ -6265,7 +6265,7 @@
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;
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; MULF
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;
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; The C3x MPYF only uses 24 bit precision while the C4x uses 32 bit precison.
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; The C3x MPYF only uses 24-bit precision while the C4x uses 32-bit precision.
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;
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(define_expand "mulhf3"
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[(parallel [(set (match_operand:HF 0 "reg_operand" "=h")
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@ -7320,7 +7320,7 @@
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"stf\\t%1,*%0++\\n\\tstf\\t%2,*%0++")
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; The following two peepholes remove an unecessary load
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; The following two peepholes remove an unnecessary load
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; often found at the end of a function. These peepholes
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; could be generalized to other binary operators. They shouldn't
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; be required if we run a post reload mop-up pass.
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@ -259,7 +259,7 @@ extern const char *cris_elinux_stacksize_str;
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/* This needs to be at least 32 bits. */
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extern int target_flags;
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/* Currently this just affects aligment. FIXME: Redundant with
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/* Currently this just affects alignment. FIXME: Redundant with
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TARGET_ALIGN_BY_32, or put machine stuff here? */
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#define TARGET_MASK_SVINTO 1
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#define TARGET_SVINTO (target_flags & TARGET_MASK_SVINTO)
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@ -850,7 +850,7 @@ enum reg_class {NO_REGS, ALL_REGS, LIM_REG_CLASSES};
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/* If we would ever need an exact mapping between canonical register
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number and dwarf frame register, we would either need to include all
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registers in the gcc decription (with some marked fixed of course), or
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registers in the gcc description (with some marked fixed of course), or
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an inverse mapping from dwarf register to gcc register. There is one
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need in dwarf2out.c:expand_builtin_init_dwarf_reg_sizes. Right now, I
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don't see that we need exact correspondence between DWARF *frame*
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@ -31,7 +31,7 @@
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;; There are several instructions that are orthogonal in size, and seems
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;; they could be matched by a single pattern without a specified size
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;; for the operand that is orthogonal. However, this did not work on
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;; gcc-2.7.2 (and problably not on gcc-2.8.1), relating to that when a
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;; gcc-2.7.2 (and probably not on gcc-2.8.1), relating to that when a
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;; constant is substituted into an operand, the actual mode must be
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;; deduced from the pattern. There is reasonable hope that that has been
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;; fixed, so FIXME: try again.
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@ -77,7 +77,7 @@
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;; The possible values are "yes", "no" and "has_slot". Yes/no means if
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;; the insn is slottable or not. Has_slot means that the insn is a
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;; return insn or branch insn (which are not considered slottable since
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;; that is generally true). Having the semmingly illogical value
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;; that is generally true). Having the seemingly illogical value
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;; "has_slot" means we do not have to add another attribute just to say
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;; that an insn has a delay-slot, since it also infers that it is not
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;; slottable. Better names for the attribute were found to be longer and
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@ -1354,7 +1354,7 @@
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"movs.b %1,%0"
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[(set_attr "slottable" "yes,yes,no")])
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;; To do a byte->word exension, extend to dword, exept that the top half
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;; To do a byte->word extension, extend to dword, exept that the top half
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;; of the register will be clobbered. FIXME: Perhaps this is not needed.
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(define_insn "extendqihi2"
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@ -110,7 +110,7 @@ struct fr30_frame_info
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unsigned int frame_size; /* # Bytes in current frame. */
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unsigned int gmask; /* Mask of saved registers. */
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unsigned int save_fp; /* Nonzero if frame pointer must be saved. */
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unsigned int save_rp; /* Nonzero if return popinter must be saved. */
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unsigned int save_rp; /* Nonzero if return pointer must be saved. */
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int initialised; /* Nonzero if frame size already calculated. */
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};
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@ -686,7 +686,7 @@ fr30_num_arg_regs (int_mode, type)
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/* Implements the FUNCTION_ARG_PARTIAL_NREGS macro.
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Returns the number of argument registers required to hold *part* of
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a parameter of machine mode MODE and tree type TYPE (which may be
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NULL if the type is not known). If the argument fits entirly in
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NULL if the type is not known). If the argument fits entirely in
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the argument registers, or entirely on the stack, then 0 is returned.
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CUM is the number of argument registers already used by earlier
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parameters to the function. */
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@ -973,7 +973,7 @@ fr30_const_double_is_zero (operand)
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/* Output a double word move.
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It must be REG<-REG, REG<-MEM, MEM<-REG or REG<-CONST.
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On the FR30 we are contrained by the fact that it does not
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On the FR30 we are constrained by the fact that it does not
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support offsetable addresses, and so we have to load the
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address of the secnd word into the second destination register
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before we can use it. */
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@ -926,7 +926,7 @@ enum reg_class
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jmp @r0
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The no-ops are to guarantee that the static chain and final
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target are 32 bit ailgned within the trampoline. That allows us to
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target are 32 bit aligned within the trampoline. That allows us to
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initialize those locations with simple SImode stores. The alternative
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would be to use HImode stores. */
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@ -639,7 +639,7 @@
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;; We need some trickery to be able to handle the addition of
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;; large (ie outside +/- 16) constants. We need to be able to
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;; handle this because reload assumes that it can generate add
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;; instructions with arbitary sized constants.
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;; instructions with arbitrary sized constants.
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(define_expand "addsi3"
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[(set (match_operand:SI 0 "register_operand" "")
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(plus:SI (match_operand:SI 1 "register_operand" "")
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@ -151,7 +151,7 @@ typedef struct
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nested compares can be done. The csubcc and caddcc instructions don't
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have enough bits to specify both a CC register to be set and a CR register
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to do the test on, so the same bit number is used for both. Needless to
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say, this is rather inconvient for GCC. */
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say, this is rather inconvenient for GCC. */
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rtx nested_cc_reg;
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/* Extra CR registers used for &&, ||. */
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@ -1644,7 +1644,7 @@ frv_expand_prologue (void)
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/* Under frv, all of the work is done via frv_expand_epilogue, but
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this function provides a convient place to do cleanup. */
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this function provides a convenient place to do cleanup. */
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static void
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frv_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
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@ -2300,7 +2300,7 @@ frv_final_prescan_insn (rtx insn, rtx *opvec, int noperands ATTRIBUTE_UNUSED)
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/* Set frv_insn_packing_flag to FALSE if the next instruction should
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be packed with this one. Set it to TRUE otherwise. If the next
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instruction is an asm insntruction, this statement will set the
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instruction is an asm instruction, this statement will set the
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flag to TRUE, and that value will still hold when the asm operands
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themselves are printed. */
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frv_insn_packing_flag = ! (insn && INSN_P (insn)
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@ -3757,7 +3757,7 @@ pic_register_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
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}
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/* Return 1 if operand is a symbolic reference when a PIC option is specified
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that takes 3 seperate instructions to form. */
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that takes 3 separate instructions to form. */
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int
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pic_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
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@ -5830,7 +5830,7 @@ frv_emit_scc (enum rtx_code test, rtx target)
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/* Split a SCC instruction into component parts, returning a SEQUENCE to hold
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the seperate insns. */
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the separate insns. */
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rtx
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frv_split_scc (rtx dest, rtx test, rtx cc_reg, rtx cr_reg, HOST_WIDE_INT value)
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@ -5941,7 +5941,7 @@ frv_emit_cond_move (rtx dest, rtx test_rtx, rtx src1, rtx src2)
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}
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/* Split a conditonal move into constituent parts, returning a SEQUENCE
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/* Split a conditional move into constituent parts, returning a SEQUENCE
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containing all of the insns. */
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rtx
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@ -8444,7 +8444,7 @@ frv_pack_insns (void)
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}
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/* Clear the VLIW start flag on random USE and CLOBBER insns, which is
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set on the USE insn that preceeds the return, and potentially on
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set on the USE insn that precedes the return, and potentially on
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CLOBBERs for setting multiword variables. Also skip the ADDR_VEC
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holding the case table labels. */
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pattern_code = GET_CODE (PATTERN (insn));
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@ -9000,7 +9000,7 @@ frv_legitimize_target (enum insn_code icode, rtx target)
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}
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/* Given that ARG is being passed as operand OPNUM to instruction ICODE,
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check whether ARG satisfies the operand's contraints. If it doesn't,
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check whether ARG satisfies the operand's constraints. If it doesn't,
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copy ARG to a temporary register and return that. Otherwise return ARG
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itself. */
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@ -463,7 +463,7 @@
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first regular expression *and* the reservation described by
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the second regular expression *and* etc.
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4. "*" is used for convinience and simply means sequence in
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4. "*" is used for convenience and simply means sequence in
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which the regular expression are repeated NUMBER times with
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cycle advancing (see ",").
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@ -1118,7 +1118,7 @@
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;; Note - it is the backend's responsibility to fill any unfilled delay slots
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;; at assembler generation time. This is usually done by adding a special print
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;; operand to the delayed insrtuction, and then in the PRINT_OPERAND function
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;; operand to the delayed instruction, and then in the PRINT_OPERAND function
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;; calling dbr_sequence_length() to determine how many delay slots were filled.
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;; For example:
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;;
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@ -1364,7 +1364,7 @@
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;; Note - it is best to only have one movsi pattern and to handle
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;; all the various contingencies by the use of alternatives. This
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;; allows reload the greatest amount of flexability (since reload will
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;; allows reload the greatest amount of flexibility (since reload will
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;; only choose amoungst alternatives for a selected insn, it will not
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;; replace the insn with another one).
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@ -1374,7 +1374,7 @@
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;; constants into memory when the destination is a floating-point register.
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;; That may make a function use a PIC pointer when it didn't before, and we
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;; cannot change PIC usage (and hence stack layout) so late in the game.
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;; The resulting sequences for loading cosntants into FPRs are preferable
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;; The resulting sequences for loading constants into FPRs are preferable
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;; even when we're not generating PIC code.
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(define_insn "*movsi_load"
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@ -3328,7 +3328,7 @@
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;; "anddi3 %0,%1,%2"
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;; [(set_attr "length" "4")])
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;; Includive OR, 64 bit integers
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;; Inclusive OR, 64 bit integers
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;; (define_insn "iordi3"
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;; [(set (match_operand:DI 0 "register_operand" "=r")
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;; (ior:DI (match_operand:DI 1 "register_operand" "%r")
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@ -7393,7 +7393,7 @@
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[(set_attr "length" "4")
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(set_attr "type" "mqsath")])
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;; Set hi/lo instrctions: type "mset"
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;; Set hi/lo instructions: type "mset"
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(define_insn "mhsetlos"
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[(set (match_operand:SI 0 "fpr_operand" "=f")
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@ -81,7 +81,7 @@ extern void __frv_deregister_eh(void) __attribute__((__destructor__));
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extern func_ptr __EH_FRAME_BEGIN__[];
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/* Register the exeception handling table as the first constructor */
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/* Register the exception handling table as the first constructor */
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void
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__frv_register_eh (void)
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{
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@ -93,7 +93,7 @@ __frv_register_eh (void)
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/* Note, do not declare __{,de}register_frame_info weak as it seems
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to interfere with the pic support. */
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/* Unregister the exeception handling table as a deconstructor */
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/* Unregister the exception handling table as a deconstructor */
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void
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__frv_deregister_eh (void)
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{
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@ -220,7 +220,7 @@
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(and (eq_attr "type" "idiv")
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(eq_attr "memory" "load,both")))
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"athlon-vector,((athlon-load,athlon-ieu0*6)+(athlon-fpsched,athlon-fvector))")
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;; The paralelism of string instructions is not documented. Model it same way
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;; The parallelism of string instructions is not documented. Model it same way
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;; as idiv to create smaller automata. This probably does not matter much.
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(define_insn_reservation "athlon_str" 6
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(and (eq_attr "cpu" "athlon,k8")
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@ -831,7 +831,7 @@
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(and (eq_attr "cpu" "k8")
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(eq_attr "type" "ssemul"))
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"athlon-double,athlon-fpsched,(athlon-fmul*2)")
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;; divsd timmings. divss is faster
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;; divsd timings. divss is faster
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(define_insn_reservation "athlon_ssediv_load" 20
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(and (eq_attr "cpu" "athlon")
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(and (eq_attr "type" "ssediv")
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@ -1666,7 +1666,7 @@ ix86_comp_type_attributes (tree type1, tree type2)
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/* Return the regparm value for a fuctio with the indicated TYPE and DECL.
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DECL may be NULL when calling function indirectly
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or considerling a libcall. */
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or considering a libcall. */
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static int
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ix86_function_regparm (tree type, tree decl)
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@ -5082,7 +5082,7 @@ ix86_emit_save_regs_using_mov (rtx pointer, HOST_WIDE_INT offset)
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}
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}
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/* Expand prologue or epilogue stack adjustement.
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/* Expand prologue or epilogue stack adjustment.
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The pattern exist to put a dependency on all ebp-based memory accesses.
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STYLE should be negative if instructions should be marked as frame related,
|
||||
zero if %r11 register is live and cannot be freely used and positive
|
||||
|
||||
@ -2133,7 +2133,7 @@
|
||||
return "push{l}\t%1";
|
||||
|
||||
default:
|
||||
/* This insn should be already splitted before reg-stack. */
|
||||
/* This insn should be already split before reg-stack. */
|
||||
abort ();
|
||||
}
|
||||
}
|
||||
@ -2151,7 +2151,7 @@
|
||||
return "push{q}\t%q1";
|
||||
|
||||
default:
|
||||
/* This insn should be already splitted before reg-stack. */
|
||||
/* This insn should be already split before reg-stack. */
|
||||
abort ();
|
||||
}
|
||||
}
|
||||
@ -2409,7 +2409,7 @@
|
||||
(match_operand:DF 1 "general_no_elim_operand" "f#Y,Fo#fY,*r#fY,Y#f"))]
|
||||
"!TARGET_64BIT && !TARGET_INTEGER_DFMODE_MOVES"
|
||||
{
|
||||
/* This insn should be already splitted before reg-stack. */
|
||||
/* This insn should be already split before reg-stack. */
|
||||
abort ();
|
||||
}
|
||||
[(set_attr "type" "multi")
|
||||
@ -2420,7 +2420,7 @@
|
||||
(match_operand:DF 1 "general_no_elim_operand" "f#rY,rFo#fY,Y#rf"))]
|
||||
"TARGET_64BIT || TARGET_INTEGER_DFMODE_MOVES"
|
||||
{
|
||||
/* This insn should be already splitted before reg-stack. */
|
||||
/* This insn should be already split before reg-stack. */
|
||||
abort ();
|
||||
}
|
||||
[(set_attr "type" "multi")
|
||||
@ -2726,7 +2726,7 @@
|
||||
(match_operand:XF 1 "general_no_elim_operand" "f,Fo,*r"))]
|
||||
"optimize_size"
|
||||
{
|
||||
/* This insn should be already splitted before reg-stack. */
|
||||
/* This insn should be already split before reg-stack. */
|
||||
abort ();
|
||||
}
|
||||
[(set_attr "type" "multi")
|
||||
@ -2737,7 +2737,7 @@
|
||||
(match_operand:XF 1 "general_no_elim_operand" "f#r,ro#f"))]
|
||||
"!optimize_size"
|
||||
{
|
||||
/* This insn should be already splitted before reg-stack. */
|
||||
/* This insn should be already split before reg-stack. */
|
||||
abort ();
|
||||
}
|
||||
[(set_attr "type" "multi")
|
||||
|
||||
@ -146,7 +146,7 @@ Boston, MA 02111-1307, USA. */
|
||||
assume that /usr/gnu is the prefix for the GNU tools, because thats
|
||||
where the SCO provided ones go. This is especially important for
|
||||
include and library search path ordering. We want to look in /usr/gnu
|
||||
first, becuase frequently people are linking against -lintl, and they
|
||||
first because frequently people are linking against -lintl, and they
|
||||
MEAN to link with gettext. What they get is the SCO intl library. Its
|
||||
a REAL pity that GNU gettext chose that name; perhaps in a future
|
||||
version they can be persuaded to change it to -lgnuintl and have a
|
||||
|
||||
@ -5589,7 +5589,7 @@
|
||||
;; ::
|
||||
;; ::::::::::::::::::::
|
||||
|
||||
;; ??? Emiting a NOP instruction isn't very useful. This should probably
|
||||
;; ??? Emitting a NOP instruction isn't very useful. This should probably
|
||||
;; be emitting ";;" to force a break in the instruction packing.
|
||||
|
||||
;; No operation, needed in case the user uses -g but not -O.
|
||||
|
||||
@ -368,7 +368,7 @@ function_epilogue (file, size)
|
||||
OUT_AS2 (mov, w, %L0);
|
||||
OUT_AS2 (add, spl, w);
|
||||
epilogue_size += 4;
|
||||
/* fall-thru */
|
||||
/* fall-through */
|
||||
case 0:
|
||||
break;
|
||||
case 1:
|
||||
@ -383,7 +383,7 @@ function_epilogue (file, size)
|
||||
OUT_AS2 (mov, w, %H0);
|
||||
OUT_AS2 (add, sph, w);
|
||||
epilogue_size += 4;
|
||||
/* fall-thru */
|
||||
/* fall-through */
|
||||
case 0:
|
||||
break;
|
||||
case 0x100:
|
||||
@ -498,7 +498,7 @@ function_epilogue (file, size)
|
||||
OUT_AS2 (mov, w, %L0);
|
||||
OUT_AS2 (add, spl, w);
|
||||
epilogue_size += 4;
|
||||
/* fall-thru */
|
||||
/* fall-through */
|
||||
|
||||
case 0:
|
||||
break;
|
||||
@ -515,7 +515,7 @@ function_epilogue (file, size)
|
||||
OUT_AS2 (mov, w, %H0);
|
||||
OUT_AS2 (add, sph, w);
|
||||
epilogue_size += 4;
|
||||
/* fall-thru */
|
||||
/* fall-through */
|
||||
|
||||
case 0:
|
||||
break;
|
||||
@ -615,7 +615,7 @@ legitimate_address_p (mode, x, strict)
|
||||
if (REGNO (x) == REG_IP)
|
||||
return (GET_MODE_SIZE (mode) == 1) ? 'R' : 0;
|
||||
|
||||
/* We can indirect thru DP or SP register. */
|
||||
/* We can indirect through DP or SP register. */
|
||||
if (strict ? REG_OK_FOR_BASE_STRICT_P (x)
|
||||
: REG_OK_FOR_BASE_NOSTRICT_P (x))
|
||||
return 'S';
|
||||
@ -636,7 +636,7 @@ legitimate_address_p (mode, x, strict)
|
||||
op2 = tmp;
|
||||
}
|
||||
|
||||
/* Don't let anything but R+I thru.. */
|
||||
/* Don't let anything but R+I through.. */
|
||||
if (! REG_P (op1)
|
||||
|| REG_P (op2)
|
||||
|| GET_CODE (op2) != CONST_INT)
|
||||
@ -783,7 +783,7 @@ print_operand_address (file, addr)
|
||||
{
|
||||
case SUBREG:
|
||||
addr = alter_subreg (&addr);
|
||||
/* fall-thru */
|
||||
/* fall-through */
|
||||
|
||||
case REG:
|
||||
fprintf (file, "(%s)",
|
||||
@ -906,7 +906,7 @@ print_operand (file, x, code)
|
||||
{
|
||||
case SUBREG:
|
||||
x = alter_subreg (&x);
|
||||
/* fall-thru */
|
||||
/* fall-through */
|
||||
|
||||
case REG:
|
||||
fprintf (file, reg_names[true_regnum (x) + abcd]);
|
||||
@ -1757,7 +1757,7 @@ ip2k_gen_unsigned_comp_branch (insn, code, label)
|
||||
|
||||
case GTU:
|
||||
code = NE; /* Anything nonzero is GTU. */
|
||||
/* fall-thru */
|
||||
/* fall-through */
|
||||
|
||||
case EQ:
|
||||
case NE: /* Test all the bits, result in
|
||||
@ -2077,7 +2077,7 @@ ip2k_gen_unsigned_comp_branch (insn, code, label)
|
||||
case GTU:
|
||||
if (imm_sub)
|
||||
{
|
||||
/* > 0xffff never suceeds! */
|
||||
/* > 0xffff never succeeds! */
|
||||
if ((INTVAL (operands[1]) & 0xffff) != 0xffff)
|
||||
{
|
||||
operands[3] = GEN_INT (INTVAL (operands[1]) + 1);
|
||||
@ -2177,7 +2177,7 @@ ip2k_gen_unsigned_comp_branch (insn, code, label)
|
||||
{
|
||||
if ((INTVAL (operands[1]) & 0xffff) == 0xffff)
|
||||
{
|
||||
/* <= 0xffff always suceeds. */
|
||||
/* <= 0xffff always succeeds. */
|
||||
OUT_AS1 (page, %2);
|
||||
OUT_AS1 (jmp, %2);
|
||||
}
|
||||
@ -2306,7 +2306,7 @@ ip2k_gen_unsigned_comp_branch (insn, code, label)
|
||||
case GTU:
|
||||
if (imm_sub)
|
||||
{
|
||||
/* > 0xffffffff never suceeds! */
|
||||
/* > 0xffffffff never succeeds! */
|
||||
if ((unsigned HOST_WIDE_INT)(INTVAL (operands[1]) & 0xffffffff)
|
||||
!= 0xffffffff)
|
||||
{
|
||||
@ -2436,7 +2436,7 @@ ip2k_gen_unsigned_comp_branch (insn, code, label)
|
||||
if ((unsigned HOST_WIDE_INT)(INTVAL (operands[1]) & 0xffffffff)
|
||||
== 0xffffffff)
|
||||
{
|
||||
/* <= 0xffffffff always suceeds. */
|
||||
/* <= 0xffffffff always succeeds. */
|
||||
OUT_AS1 (page, %2);
|
||||
OUT_AS1 (jmp, %2);
|
||||
}
|
||||
@ -3856,7 +3856,7 @@ track_dp_reload (insn, dp_current, dp_current_ok, modifying)
|
||||
/* As part of the machine-dependent reorg we scan loads and reloads of
|
||||
DP to see where any are redundant. This does happens because we
|
||||
are able to subsequently transform things in interesting ways. Sometimes
|
||||
gcc also does unecessary reloads too so we try to eliminate these too. */
|
||||
gcc also does unnecessary reloads too so we try to eliminate these too. */
|
||||
|
||||
static void
|
||||
mdr_try_dp_reload_elim (first_insn)
|
||||
@ -4017,7 +4017,7 @@ mdr_try_dp_reload_elim (first_insn)
|
||||
}
|
||||
|
||||
/* When we're looking to see if we've finished we count the number of
|
||||
paths throught the code labels where we weren't able to definitively
|
||||
paths through the code labels where we weren't able to definitively
|
||||
track DP.
|
||||
This number is used to see if we're converging on a solution.
|
||||
If this hits zero then we've fully converged, but if this stays the
|
||||
@ -5262,7 +5262,7 @@ mdr_try_wreg_elim (first_insn)
|
||||
}
|
||||
|
||||
/* When we're looking to see if we've finished we count the number of
|
||||
paths throught the code labels where we weren't able to definitively
|
||||
paths through the code labels where we weren't able to definitively
|
||||
track WREG. This number is used to see if we're converging on a
|
||||
solution.
|
||||
If this hits zero then we've fully converged, but if this stays the
|
||||
@ -6191,7 +6191,7 @@ ip2k_short_operand (x, mode)
|
||||
|
||||
x = XEXP (x, 0);
|
||||
|
||||
/* fall thru */
|
||||
/* fall through */
|
||||
|
||||
case REG:
|
||||
if (IS_PSEUDO_P (x))
|
||||
|
||||
@ -65,7 +65,7 @@
|
||||
;; d - non-pointer registers (not SP, DP, IP)
|
||||
;; u - non-SP registers (everything except SP)
|
||||
;;
|
||||
;; R - Indirect thru IP - Avoid this except for QI mode, since we
|
||||
;; R - Indirect through IP - Avoid this except for QI mode, since we
|
||||
;; can't access extra bytes.
|
||||
;; S - Short (stack/dp address). Pointer with 0..127 displacement
|
||||
;; Note that 0(SP) has undefined contents due to post-decrement push
|
||||
|
||||
@ -1420,7 +1420,7 @@ extern unsigned char m68hc11_reg_valid_for_index[FIRST_PSEUDO_REGISTER];
|
||||
macro is used in only one place: `find_reloads_address' in reload.c.
|
||||
|
||||
For M68HC11, we handle large displacements of a base register
|
||||
by splitting the addend accors an addhi3 insn.
|
||||
by splitting the addend across an addhi3 insn.
|
||||
|
||||
For M68HC12, the 64K offset range is available.
|
||||
*/
|
||||
|
||||
@ -213,7 +213,7 @@ extern int target_flags;
|
||||
#define MASK_RTD (1<<16)
|
||||
#define TARGET_RTD (target_flags & MASK_RTD)
|
||||
|
||||
/* Support A5 relative data seperate from text.
|
||||
/* Support A5 relative data separate from text.
|
||||
* This option implies -fPIC, however it inhibits the generation of the
|
||||
* A5 save/restore in functions and the loading of a5 with a got pointer.
|
||||
*/
|
||||
|
||||
@ -6649,7 +6649,7 @@ mips_expand_prologue (void)
|
||||
/* Set up the frame pointer, if we're using one. In mips16 code,
|
||||
we point the frame pointer ahead of the outgoing argument area.
|
||||
This should allow more variables & incoming arguments to be
|
||||
acceesed with unextended instructions. */
|
||||
accessed with unextended instructions. */
|
||||
if (frame_pointer_needed)
|
||||
{
|
||||
if (TARGET_MIPS16 && cfun->machine->frame.args_size != 0)
|
||||
|
||||
@ -4249,7 +4249,7 @@ function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
|
||||
value in GPRs is reported here. */
|
||||
if (align_words + CLASS_MAX_NREGS (mode, GENERAL_REGS)
|
||||
> GP_ARG_NUM_REG)
|
||||
/* Fortunately, there are only two possibilites, the value
|
||||
/* Fortunately, there are only two possibilities, the value
|
||||
is either wholly in GPRs or half in GPRs and half not. */
|
||||
part_mode = DImode;
|
||||
|
||||
@ -13643,7 +13643,7 @@ rs6000_adjust_cost (rtx insn, rtx link, rtx dep_insn ATTRIBUTE_UNUSED,
|
||||
}
|
||||
|
||||
/* The function returns a true if INSN is microcoded.
|
||||
Return false ptherwise. */
|
||||
Return false otherwise. */
|
||||
|
||||
static bool
|
||||
is_microcoded_insn (rtx insn)
|
||||
@ -14030,7 +14030,7 @@ get_next_active_insn (rtx insn, rtx tail)
|
||||
return next_insn;
|
||||
}
|
||||
|
||||
/* Return whether the presence of INSN causes a dispatch group terminatation
|
||||
/* Return whether the presence of INSN causes a dispatch group termination
|
||||
of group WHICH_GROUP.
|
||||
|
||||
If WHICH_GROUP == current_group, this function will return true if INSN
|
||||
@ -14072,7 +14072,7 @@ insn_terminates_group_p (rtx insn, enum group_termination which_group)
|
||||
return false;
|
||||
}
|
||||
|
||||
/* Return true if it is recommended to keep NEXT_INSN "far" (in a seperate
|
||||
/* Return true if it is recommended to keep NEXT_INSN "far" (in a separate
|
||||
dispatch group) from the insns in GROUP_INSNS. Return false otherwise. */
|
||||
|
||||
static bool
|
||||
@ -14110,7 +14110,7 @@ is_costly_group (rtx *group_insns, rtx next_insn)
|
||||
one of the following schemes, depending on the value of the flag
|
||||
-minsert_sched_nops = X:
|
||||
(1) X == sched_finish_regroup_exact: insert exactly as many nops as needed
|
||||
in order to force NEXT_INSN into a seperate group.
|
||||
in order to force NEXT_INSN into a separate group.
|
||||
(2) X < sched_finish_regroup_exact: insert exactly X nops.
|
||||
GROUP_END, CAN_ISSUE_MORE and GROUP_COUNT record the state after nop
|
||||
insertion (has a group just ended, how many vacant issue slots remain in the
|
||||
|
||||
@ -7415,7 +7415,7 @@
|
||||
|
||||
|
||||
;; Instruction definition to extend a 31-bit pointer into a 64-bit
|
||||
;; pointer. This is used for compatability.
|
||||
;; pointer. This is used for compatibility.
|
||||
|
||||
(define_expand "ptr_extend"
|
||||
[(set (match_operand:DI 0 "register_operand" "=r")
|
||||
|
||||
@ -2875,7 +2875,7 @@ struct sh_args {
|
||||
used to use the encodings 245..260, but that doesn't make sense:
|
||||
PR_REG and PR_MEDIA_REG are actually the same register, and likewise
|
||||
the FP registers stay the same when switching between compact and media
|
||||
mode. Hence, we also need to use the same dwarf frame coloumns.
|
||||
mode. Hence, we also need to use the same dwarf frame columns.
|
||||
Likewise, we need to support unwind information for SHmedia registers
|
||||
even in compact code. */
|
||||
#define SH_DBX_REGISTER_NUMBER(REGNO) \
|
||||
|
||||
@ -8641,7 +8641,7 @@
|
||||
"TARGET_TLS && TARGET_ARCH64"
|
||||
"xor\\t%1, %%tle_lox10(%a2), %0")
|
||||
|
||||
;; Now patterns combinding tldo_add{32,64} with some integer loads or stores
|
||||
;; Now patterns combining tldo_add{32,64} with some integer loads or stores
|
||||
(define_insn "*tldo_ldub_sp32"
|
||||
[(set (match_operand:QI 0 "register_operand" "=r")
|
||||
(mem:QI (plus:SI (unspec:SI [(match_operand:SI 2 "register_operand" "r")
|
||||
|
||||
@ -2270,7 +2270,7 @@ v850_encode_data_area (tree decl, rtx symbol)
|
||||
{
|
||||
int flags;
|
||||
|
||||
/* Map explict sections into the appropriate attribute */
|
||||
/* Map explicit sections into the appropriate attribute */
|
||||
if (v850_get_data_area (decl) == DATA_AREA_NORMAL)
|
||||
{
|
||||
if (DECL_SECTION_NAME (decl))
|
||||
@ -3155,8 +3155,8 @@ pattern_is_ok_for_prepare (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
|
||||
return 0;
|
||||
|
||||
/* If the register is being pushed somewhere other than the stack
|
||||
space just aquired by the first operand then abandon this quest.
|
||||
Note: the test is <= becuase both values are negative. */
|
||||
space just acquired by the first operand then abandon this quest.
|
||||
Note: the test is <= because both values are negative. */
|
||||
if (INTVAL (XEXP (plus, 1))
|
||||
<= INTVAL (XEXP (SET_SRC (XVECEXP (op, 0, 0)), 1)))
|
||||
return 0;
|
||||
|
||||
@ -1349,7 +1349,7 @@ zbss_section () \
|
||||
can appear in the "ghs section" pragma. These names are used to index
|
||||
into the GHS_default_section_names[] and GHS_current_section_names[]
|
||||
that are defined in v850.c, and so the ordering of each must remain
|
||||
consistant.
|
||||
consistent.
|
||||
|
||||
These arrays give the default and current names for each kind of
|
||||
section defined by the GHS pragmas. The current names can be changed
|
||||
|
||||
@ -1716,7 +1716,7 @@
|
||||
"TARGET_V850E && !TARGET_DISABLE_CALLT"
|
||||
;; The CALLT instruction stores the next address of CALLT to CTPC register
|
||||
;; without saving its previous value. So if the interrupt handler
|
||||
;; or its caller could possibily execute the CALLT insn, save_interrupt
|
||||
;; or its caller could possibly execute the CALLT insn, save_interrupt
|
||||
;; MUST NOT be called via CALLT.
|
||||
"*
|
||||
{
|
||||
|
||||
@ -198,7 +198,7 @@ tsd_init (void)
|
||||
/* External interface */
|
||||
|
||||
/* Store in KEYP a value which can be passed to __gthread_setspecific/
|
||||
__gthread_getspecific to store and retrive a value which is
|
||||
__gthread_getspecific to store and retrieve a value which is
|
||||
specific to each calling thread. If DTOR is not NULL, it will be
|
||||
called when a thread terminates with a non-NULL specific value for
|
||||
this key, with the value as its sole argument. */
|
||||
|
||||
@ -1585,10 +1585,10 @@ xtensa_setup_frame_addresses (void)
|
||||
a comment showing where the end of the loop is. However, if there is a
|
||||
label or a branch at the end of the loop then we need to place a nop
|
||||
there. If the loop ends with a label we need the nop so that branches
|
||||
targetting that label will target the nop (and thus remain in the loop),
|
||||
instead of targetting the instruction after the loop (and thus exiting
|
||||
targeting that label will target the nop (and thus remain in the loop),
|
||||
instead of targeting the instruction after the loop (and thus exiting
|
||||
the loop). If the loop ends with a branch, we need the nop in case the
|
||||
branch is targetting a location inside the loop. When the branch
|
||||
branch is targeting a location inside the loop. When the branch
|
||||
executes it will cause the loop count to be decremented even if it is
|
||||
taken (because it is the last instruction in the loop), so we need to
|
||||
nop after the branch to prevent the loop count from being decremented
|
||||
|
||||
Loading…
Reference in New Issue
Block a user