i386.md (SWIM1248s): Rename from SWIM1248x.
* config/i386/i386.md (SWIM1248s): Rename from SWIM1248x. Update all uses. (and<mode>3): Use gen_extend_insn instead of indirect functions. Do not generate DImode extends for 32bit targets. (and->zext post-reload splitter): Use gen_extend_insn instead of indirect functions. (anddi->zext pre-reload splitter): New. * config/i386/i386-expand.c (ix86_expand_int_sse_cmp): Use gen_sub3_insn instead of indirect function. (ix86_expand_ashl_const): Use gen_add2_insn instead of indirect function. (ix86_adjust_counter): Ditto. From-SVN: r272270
This commit is contained in:
Uros Bizjak
Uros Bizjak
parent
1d53751dd5
commit
83bc5e44d8
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@ -1,3 +1,21 @@
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2019-06-13 Uroš Bizjak <ubizjak@gmail.com>
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* config/i386/i386.md (SWIM1248s): Rename from SWIM1248x.
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Update all uses.
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(and<mode>3): Use gen_extend_insn instead of indirect functions.
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Do not generate DImode extends for 32bit targets.
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(and->zext post-reload splitter): Use gen_extend_insn
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instead of indirect functions.
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(anddi->zext pre-reload splitter): New.
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2019-06-13 Uroš Bizjak <ubizjak@gmail.com>
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* config/i386/i386-expand.c (ix86_expand_int_sse_cmp):
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Use gen_sub3_insn instead of indirect function.
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(ix86_expand_ashl_const): Use gen_add2_insn instead of
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indirect function.
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(ix86_adjust_counter): Ditto.
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2019-06-13 Jiufu Guo <guojiufu@linux.ibm.com>
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Lijia He <helijia@linux.ibm.com>
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@ -4303,27 +4303,15 @@ ix86_expand_int_sse_cmp (rtx dest, enum rtx_code code, rtx cop0, rtx cop1,
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case E_V2DImode:
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{
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rtx t1, t2, mask;
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rtx (*gen_sub3) (rtx, rtx, rtx);
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switch (mode)
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{
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case E_V16SImode: gen_sub3 = gen_subv16si3; break;
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case E_V8DImode: gen_sub3 = gen_subv8di3; break;
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case E_V8SImode: gen_sub3 = gen_subv8si3; break;
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case E_V4DImode: gen_sub3 = gen_subv4di3; break;
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case E_V4SImode: gen_sub3 = gen_subv4si3; break;
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case E_V2DImode: gen_sub3 = gen_subv2di3; break;
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default:
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gcc_unreachable ();
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}
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/* Subtract (-(INT MAX) - 1) from both operands to make
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them signed. */
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mask = ix86_build_signbit_mask (mode, true, false);
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t1 = gen_reg_rtx (mode);
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emit_insn (gen_sub3 (t1, cop0, mask));
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emit_insn (gen_sub3_insn (t1, cop0, mask));
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t2 = gen_reg_rtx (mode);
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emit_insn (gen_sub3 (t2, cop1, mask));
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emit_insn (gen_sub3_insn (t2, cop1, mask));
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cop0 = t1;
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cop1 = t2;
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@ -4339,9 +4327,8 @@ ix86_expand_int_sse_cmp (rtx dest, enum rtx_code code, rtx cop0, rtx cop1,
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case E_V8HImode:
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/* Perform a parallel unsigned saturating subtraction. */
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x = gen_reg_rtx (mode);
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emit_insn (gen_rtx_SET (x, gen_rtx_US_MINUS (mode, cop0,
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cop1)));
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emit_insn (gen_rtx_SET
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(x, gen_rtx_US_MINUS (mode, cop0, cop1)));
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cop0 = x;
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cop1 = CONST0_RTX (mode);
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code = EQ;
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@ -5562,18 +5549,17 @@ ix86_split_long_move (rtx operands[])
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static void
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ix86_expand_ashl_const (rtx operand, int count, machine_mode mode)
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{
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rtx (*insn)(rtx, rtx, rtx);
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if (count == 1
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|| (count * ix86_cost->add <= ix86_cost->shift_const
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&& !optimize_insn_for_size_p ()))
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{
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insn = mode == DImode ? gen_addsi3 : gen_adddi3;
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while (count-- > 0)
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emit_insn (insn (operand, operand, operand));
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emit_insn (gen_add2_insn (operand, operand));
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}
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else
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{
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rtx (*insn)(rtx, rtx, rtx);
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insn = mode == DImode ? gen_ashlsi3 : gen_ashldi3;
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emit_insn (insn (operand, operand, GEN_INT (count)));
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}
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@ -6506,10 +6492,7 @@ expand_setmem_epilogue (rtx destmem, rtx destptr, rtx value, rtx vec_value,
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static void
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ix86_adjust_counter (rtx countreg, HOST_WIDE_INT value)
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{
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rtx (*gen_add)(rtx, rtx, rtx)
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= GET_MODE (countreg) == DImode ? gen_adddi3 : gen_addsi3;
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emit_insn (gen_add (countreg, countreg, GEN_INT (-value)));
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emit_insn (gen_add2_insn (countreg, GEN_INT (-value)));
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}
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/* Depending on ISSETMEM, copy enough from SRCMEM to DESTMEM or set enough to
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@ -1018,10 +1018,11 @@
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(HI "TARGET_HIMODE_MATH")
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SI])
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;; Math-dependant integer modes with DImode.
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(define_mode_iterator SWIM1248x [(QI "TARGET_QIMODE_MATH")
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(HI "TARGET_HIMODE_MATH")
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SI (DI "(TARGET_STV && TARGET_SSE2) || TARGET_64BIT")])
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;; Math-dependant integer modes with DImode (enabled for 32bit with STV).
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(define_mode_iterator SWIM1248s
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[(QI "TARGET_QIMODE_MATH")
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(HI "TARGET_HIMODE_MATH")
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SI (DI "TARGET_64BIT || (TARGET_STV && TARGET_SSE2)")])
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;; Math-dependant single word integer modes without QImode.
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(define_mode_iterator SWIM248 [(HI "TARGET_HIMODE_MATH")
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@ -4076,45 +4077,6 @@
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[(set_attr "isa" "*,avx512dq,avx512dq")
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(set_attr "type" "imovx,mskmov,mskmov")
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(set_attr "mode" "SI,QI,QI")])
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(define_insn_and_split "*zext<mode>_doubleword_and"
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[(set (match_operand:DI 0 "register_operand" "=&<r>")
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(zero_extend:DI (match_operand:SWI12 1 "nonimmediate_operand" "<r>m")))]
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"!TARGET_64BIT && TARGET_STV && TARGET_SSE2
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&& TARGET_ZERO_EXTEND_WITH_AND && optimize_function_for_speed_p (cfun)"
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"#"
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"&& reload_completed && GENERAL_REG_P (operands[0])"
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[(set (match_dup 2) (const_int 0))]
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{
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split_double_mode (DImode, &operands[0], 1, &operands[0], &operands[2]);
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emit_move_insn (operands[0], const0_rtx);
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gcc_assert (!TARGET_PARTIAL_REG_STALL);
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emit_insn (gen_movstrict<mode>
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(gen_lowpart (<MODE>mode, operands[0]), operands[1]));
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})
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(define_insn_and_split "*zext<mode>_doubleword"
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[(set (match_operand:DI 0 "register_operand" "=r")
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(zero_extend:DI (match_operand:SWI12 1 "nonimmediate_operand" "<r>m")))]
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"!TARGET_64BIT && TARGET_STV && TARGET_SSE2
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&& !(TARGET_ZERO_EXTEND_WITH_AND && optimize_function_for_speed_p (cfun))"
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"#"
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"&& reload_completed && GENERAL_REG_P (operands[0])"
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[(set (match_dup 0) (zero_extend:SI (match_dup 1)))
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(set (match_dup 2) (const_int 0))]
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"split_double_mode (DImode, &operands[0], 1, &operands[0], &operands[2]);")
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(define_insn_and_split "*zextsi_doubleword"
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[(set (match_operand:DI 0 "register_operand" "=r")
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(zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "rm")))]
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"!TARGET_64BIT && TARGET_STV && TARGET_SSE2"
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"#"
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"&& reload_completed && GENERAL_REG_P (operands[0])"
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[(set (match_dup 0) (match_dup 1))
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(set (match_dup 2) (const_int 0))]
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"split_double_mode (DImode, &operands[0], 1, &operands[0], &operands[2]);")
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;; Sign extension instructions
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@ -8394,48 +8356,34 @@
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;; it should be done with splitters.
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(define_expand "and<mode>3"
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[(set (match_operand:SWIM1248x 0 "nonimmediate_operand")
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(and:SWIM1248x (match_operand:SWIM1248x 1 "nonimmediate_operand")
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(match_operand:SWIM1248x 2 "<general_szext_operand>")))]
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[(set (match_operand:SWIM1248s 0 "nonimmediate_operand")
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(and:SWIM1248s (match_operand:SWIM1248s 1 "nonimmediate_operand")
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(match_operand:SWIM1248s 2 "<general_szext_operand>")))]
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""
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{
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machine_mode mode = <MODE>mode;
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rtx (*insn) (rtx, rtx);
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if (CONST_INT_P (operands[2]) && REG_P (operands[0]))
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if (<MODE>mode == DImode && !TARGET_64BIT)
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;
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else if (CONST_INT_P (operands[2]) && REG_P (operands[0]))
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{
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HOST_WIDE_INT ival = INTVAL (operands[2]);
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unsigned HOST_WIDE_INT ival = UINTVAL (operands[2]);
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if (ival == (HOST_WIDE_INT) 0xffffffff)
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if (ival == GET_MODE_MASK (SImode))
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mode = SImode;
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else if (ival == 0xffff)
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else if (ival == GET_MODE_MASK (HImode))
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mode = HImode;
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else if (ival == 0xff)
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else if (ival == GET_MODE_MASK (QImode))
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mode = QImode;
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}
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if (mode == <MODE>mode)
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{
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ix86_expand_binary_operator (AND, <MODE>mode, operands);
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DONE;
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}
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if (<MODE>mode == DImode)
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insn = (mode == SImode)
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? gen_zero_extendsidi2
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: (mode == HImode)
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? gen_zero_extendhidi2
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: gen_zero_extendqidi2;
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else if (<MODE>mode == SImode)
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insn = (mode == HImode)
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? gen_zero_extendhisi2
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: gen_zero_extendqisi2;
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else if (<MODE>mode == HImode)
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insn = gen_zero_extendqihi2;
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if (mode != <MODE>mode)
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emit_insn (gen_extend_insn
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(operands[0], gen_lowpart (mode, operands[1]),
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<MODE>mode, mode, 1));
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else
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gcc_unreachable ();
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ix86_expand_binary_operator (AND, <MODE>mode, operands);
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emit_insn (insn (operands[0], gen_lowpart (mode, operands[1])));
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DONE;
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})
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@ -8471,6 +8419,40 @@
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DONE;
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})
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(define_split
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[(set (match_operand:DI 0 "register_operand")
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(and:DI
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(match_operand:DI 1 "nonimmediate_operand")
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(match_operand:DI 2 "const_int_operand")))
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(clobber (reg:CC FLAGS_REG))]
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"!TARGET_64BIT && TARGET_STV && TARGET_SSE2
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&& can_create_pseudo_p ()"
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[(const_int 0)]
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{
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unsigned HOST_WIDE_INT ival = UINTVAL (operands[2]);
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machine_mode mode;
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if (ival == GET_MODE_MASK (SImode))
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mode = SImode;
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else if (ival == GET_MODE_MASK (HImode))
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mode = HImode;
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else if (ival == GET_MODE_MASK (QImode))
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mode = QImode;
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else
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FAIL;
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split_double_mode (DImode, &operands[0], 3, &operands[0], &operands[3]);
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if (mode == SImode)
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emit_move_insn (operands[0], operands[1]);
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else
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emit_insn (gen_extend_insn
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(operands[0], gen_lowpart (mode, operands[1]),
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SImode, mode, 1));
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emit_move_insn (operands[3], const0_rtx);
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DONE;
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})
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(define_insn "*anddi_1"
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[(set (match_operand:DI 0 "nonimmediate_operand" "=r,rm,r,r")
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(and:DI
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@ -8617,37 +8599,25 @@
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|| REGNO (operands[0]) != REGNO (operands[1]))"
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[(const_int 0)]
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{
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HOST_WIDE_INT ival = INTVAL (operands[2]);
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unsigned HOST_WIDE_INT ival = UINTVAL (operands[2]);
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machine_mode mode;
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rtx (*insn) (rtx, rtx);
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if (ival == (HOST_WIDE_INT) 0xffffffff)
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if (ival == GET_MODE_MASK (SImode))
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mode = SImode;
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else if (ival == 0xffff)
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else if (ival == GET_MODE_MASK (HImode))
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mode = HImode;
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else if (ival == GET_MODE_MASK (QImode))
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mode = QImode;
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else
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{
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gcc_assert (ival == 0xff);
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mode = QImode;
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}
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gcc_unreachable ();
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if (<MODE>mode == DImode)
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insn = (mode == SImode)
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? gen_zero_extendsidi2
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: (mode == HImode)
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? gen_zero_extendhidi2
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: gen_zero_extendqidi2;
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else
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{
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if (<MODE>mode != SImode)
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/* Zero extend to SImode to avoid partial register stalls. */
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operands[0] = gen_lowpart (SImode, operands[0]);
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/* Zero extend to SImode to avoid partial register stalls. */
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if (<MODE_SIZE> < GET_MODE_SIZE (SImode))
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operands[0] = gen_lowpart (SImode, operands[0]);
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insn = (mode == HImode)
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? gen_zero_extendhisi2
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: gen_zero_extendqisi2;
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}
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emit_insn (insn (operands[0], gen_lowpart (mode, operands[1])));
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emit_insn (gen_extend_insn
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(operands[0], gen_lowpart (mode, operands[1]),
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GET_MODE (operands[0]), mode, 1));
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DONE;
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})
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@ -9003,9 +8973,9 @@
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;; If this is considered useful, it should be done with splitters.
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(define_expand "<code><mode>3"
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[(set (match_operand:SWIM1248x 0 "nonimmediate_operand")
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(any_or:SWIM1248x (match_operand:SWIM1248x 1 "nonimmediate_operand")
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(match_operand:SWIM1248x 2 "<general_operand>")))]
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[(set (match_operand:SWIM1248s 0 "nonimmediate_operand")
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(any_or:SWIM1248s (match_operand:SWIM1248s 1 "nonimmediate_operand")
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(match_operand:SWIM1248s 2 "<general_operand>")))]
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""
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"ix86_expand_binary_operator (<CODE>, <MODE>mode, operands); DONE;")
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@ -9697,8 +9667,8 @@
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;; One complement instructions
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(define_expand "one_cmpl<mode>2"
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[(set (match_operand:SWIM1248x 0 "nonimmediate_operand")
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(not:SWIM1248x (match_operand:SWIM1248x 1 "nonimmediate_operand")))]
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[(set (match_operand:SWIM1248s 0 "nonimmediate_operand")
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(not:SWIM1248s (match_operand:SWIM1248s 1 "nonimmediate_operand")))]
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""
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"ix86_expand_unary_operator (NOT, <MODE>mode, operands); DONE;")
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