re PR target/41484 (Please add memory forms of pmovzx* (SSE4.1))
PR target/41484 * config/i386/sse.md (sse4_1_extendv8qiv8hi2): Also accept memory operands for operand 1. (sse4_1_extendv4qiv4si2): Ditto. (sse4_1_extendv2qiv2di2): Ditto. (sse4_1_extendv4hiv4si2): Ditto. (sse4_1_extendv2hiv2di2): Ditto. (sse4_1_extendv2siv2di2): Ditto. (sse4_1_zero_extendv8qiv8hi2): Ditto. (sse4_1_zero_extendv4qiv4si2): Ditto. (sse4_1_zero_extendv2qiv2di2): Ditto. (sse4_1_zero_extendv4hiv4si2): Ditto. (sse4_1_zero_extendv2hiv2di2): Ditto. (sse4_1_zero_extendv2siv2di2): Ditto. (*sse4_1_extendv8qiv8hi2): Remove insn pattern. (*sse4_1_extendv4qiv4si2): Ditto. (*sse4_1_extendv2qiv2di2): Ditto. (*sse4_1_extendv4hiv4si2): Ditto. (*sse4_1_extendv2hiv2di2): Ditto. (*sse4_1_extendv2siv2di2): Ditto. (*sse4_1_zero_extendv8qiv8hi2): Ditto. (*sse4_1_zero_extendv4qiv4si2): Ditto. (*sse4_1_zero_extendv2qiv2di2): Ditto. (*sse4_1_zero_extendv4hiv4si2): Ditto. (*sse4_1_zero_extendv2hiv2di2): Ditto. (*sse4_1_zero_extendv2siv2di2): Ditto. From-SVN: r163591
This commit is contained in:
Uros Bizjak
parent
757fc8ed22
commit
83d5896129
@ -1,3 +1,32 @@
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2010-08-27 Uros Bizjak <ubizjak@gmail.com>
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PR target/41484
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* config/i386/sse.md (sse4_1_extendv8qiv8hi2): Also accept memory
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operands for operand 1.
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(sse4_1_extendv4qiv4si2): Ditto.
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(sse4_1_extendv2qiv2di2): Ditto.
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(sse4_1_extendv4hiv4si2): Ditto.
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(sse4_1_extendv2hiv2di2): Ditto.
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(sse4_1_extendv2siv2di2): Ditto.
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(sse4_1_zero_extendv8qiv8hi2): Ditto.
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(sse4_1_zero_extendv4qiv4si2): Ditto.
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(sse4_1_zero_extendv2qiv2di2): Ditto.
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(sse4_1_zero_extendv4hiv4si2): Ditto.
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(sse4_1_zero_extendv2hiv2di2): Ditto.
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(sse4_1_zero_extendv2siv2di2): Ditto.
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(*sse4_1_extendv8qiv8hi2): Remove insn pattern.
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(*sse4_1_extendv4qiv4si2): Ditto.
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(*sse4_1_extendv2qiv2di2): Ditto.
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(*sse4_1_extendv4hiv4si2): Ditto.
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(*sse4_1_extendv2hiv2di2): Ditto.
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(*sse4_1_extendv2siv2di2): Ditto.
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(*sse4_1_zero_extendv8qiv8hi2): Ditto.
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(*sse4_1_zero_extendv4qiv4si2): Ditto.
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(*sse4_1_zero_extendv2qiv2di2): Ditto.
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(*sse4_1_zero_extendv4hiv4si2): Ditto.
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(*sse4_1_zero_extendv2hiv2di2): Ditto.
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(*sse4_1_zero_extendv2siv2di2): Ditto.
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2010-08-27 Nathan Froyd <froydnj@codesourcery.com>
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* config/mips/mips-protos.h (mips_function_arg_advance): Delete
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@ -23,8 +52,7 @@
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(rs6000_parm_start): Likewise.
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(rs6000_arg_size): Likewise.
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(rs6000_darwin64_record_arg_advance_recurse): Likewise.
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(rs6000_darwin64_record_arg): Likewise. Take a bool instead of
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an int.
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(rs6000_darwin64_record_arg): Likewise. Take a bool instead of an int.
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(rs6000_mixed_function_arg): Likewise.
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(function_arg): Rename to...
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(rs6000_function_arg): ...this.
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@ -62,8 +90,8 @@
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2010-08-26 Richard Guenther <rguenther@suse.de>
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PR tree-optimization/45255
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* tree.c (decl_address_invariant_p): DECL_DLLIMPORT_P
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statics and externals are also invariant.
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* tree.c (decl_address_invariant_p): DECL_DLLIMPORT_P statics
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and externals are also invariant.
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2010-08-25 Jakub Jelinek <jakub@redhat.com>
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@ -85,8 +113,7 @@
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2010-08-25 Richard Guenther <rguenther@suse.de>
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* alias.c (get_alias_set): Assign a single alias-set to
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all pointers.
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* alias.c (get_alias_set): Assign a single alias-set to all pointers.
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* gimple.c (gimple_get_alias_set): Remove special handling
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for pointers.
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@ -136,8 +163,7 @@
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* config/arm/iterators.md (VU, SE, V_widen_l): New.
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(V_unpack, US): New.
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* config/arm/neon.md (vec_unpack<US>_hi_<mode>): Expansion for
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vmovl.
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* config/arm/neon.md (vec_unpack<US>_hi_<mode>): Expansion for vmovl.
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(vec_unpack<US>_lo_<mode>): Likewise.
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(neon_vec_unpack<US>_hi_<mode>): Instruction pattern for vmovl.
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(neon_vec_unpack<US>_lo_<mode>): Likewise.
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@ -239,8 +265,7 @@
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TARGET_MEM_REF more properly.
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(indirect_ref_may_alias_decl_p): Likewise.
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* emit-rtl.c (set_mem_attributes_minus_bitpos): Keep TARGET_MEM_REFs.
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* alias.c (ao_ref_from_mem): Handle TARGET_MEM_REF more
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properly.
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* alias.c (ao_ref_from_mem): Handle TARGET_MEM_REF more properly.
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2010-08-23 Anatoly Sokolov <aesok@post.ru>
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@ -268,10 +293,10 @@
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* tree-flow.h (may_be_nonaddressable_p): New definition. Make the
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existing static function global.
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*tree-ssa-loop-ivopts.c (may_be_nonaddressable_p): This function
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* tree-ssa-loop-ivopts.c (may_be_nonaddressable_p): This function
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is changed to global.
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*tree-ssa-loop-prefetch.c (gather_memory_references_ref): Call
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* tree-ssa-loop-prefetch.c (gather_memory_references_ref): Call
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may_be_nonaddressable_p on base, and don't collect this reference
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if the address of the base could not be taken.
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@ -377,7 +402,7 @@
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priority.
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(compare_ctor, compare_dtor): Move to ipa.c; use DECL_UID to stabilize
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sort; reverse order of constructors.
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(cgraph_build_cdtor_fns):Move to ipa.c; rename to build_cdtor_fns.
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(cgraph_build_cdtor_fns): Move to ipa.c; rename to build_cdtor_fns.
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(cgraph_finalize_function): Do not call record_cdtor_fn.
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(cgraph_finalize_compilation_unit): Do not call cgraph_build_cdtor_fns.
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(cgraph_build_static_cdtor): Move to ipa.c.
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@ -407,7 +432,8 @@
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* lto-cgraph.c (lto_output_edge): Use gimple_has_body_p instead of
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flag_wpa.
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* lto-streamer-out.c (lto_output): Likewise.
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* passes.c (ipa_write_optimization_summaries): Initialize statement uids.
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* passes.c (ipa_write_optimization_summaries): Initialize statement
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uids.
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2010-08-20 Olivier Hainque <hainque@adacore.com>
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@ -451,9 +477,9 @@
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revert r163410, partially revert r163267.
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* config/rs6000/darwin.h (LIB_SPEC): Remove.
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* config/darwin.h (REAL_LIBGCC_SPEC): Link lgcc for all
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* config/darwin.h (REAL_LIBGCC_SPEC): Link lgcc for all
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Darwin versions.
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2010-08-20 Jakub Jelinek <jakub@redhat.com>
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PR middle-end/44974
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@ -462,7 +488,7 @@
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2010-08-20 Uros Bizjak <ubizjak@gmail.com>
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* config/i386/i386.md (ashift RSP splitter): Remove splitter.
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* config/i386/i386.md (ashift %rsp splitter): Remove splitter.
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(pro_epilogue_adjust_stack_di_2): Use "l" constraint for
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alternative 1 of operand 2.
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@ -9596,28 +9596,7 @@
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[(set (match_operand:V8HI 0 "register_operand" "=x")
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(sign_extend:V8HI
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(vec_select:V8QI
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(match_operand:V16QI 1 "register_operand" "x")
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(parallel [(const_int 0)
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(const_int 1)
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(const_int 2)
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(const_int 3)
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(const_int 4)
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(const_int 5)
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(const_int 6)
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(const_int 7)]))))]
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"TARGET_SSE4_1"
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"%vpmovsxbw\t{%1, %0|%0, %1}"
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[(set_attr "type" "ssemov")
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(set_attr "prefix_extra" "1")
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(set_attr "prefix" "maybe_vex")
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(set_attr "mode" "TI")])
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(define_insn "*sse4_1_extendv8qiv8hi2"
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[(set (match_operand:V8HI 0 "register_operand" "=x")
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(sign_extend:V8HI
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(vec_select:V8QI
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(vec_duplicate:V16QI
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(match_operand:V8QI 1 "nonimmediate_operand" "xm"))
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(match_operand:V16QI 1 "nonimmediate_operand" "xm")
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(parallel [(const_int 0)
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(const_int 1)
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(const_int 2)
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@ -9637,24 +9616,7 @@
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[(set (match_operand:V4SI 0 "register_operand" "=x")
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(sign_extend:V4SI
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(vec_select:V4QI
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(match_operand:V16QI 1 "register_operand" "x")
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(parallel [(const_int 0)
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(const_int 1)
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(const_int 2)
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(const_int 3)]))))]
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"TARGET_SSE4_1"
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"%vpmovsxbd\t{%1, %0|%0, %1}"
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[(set_attr "type" "ssemov")
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(set_attr "prefix_extra" "1")
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(set_attr "prefix" "maybe_vex")
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(set_attr "mode" "TI")])
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(define_insn "*sse4_1_extendv4qiv4si2"
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[(set (match_operand:V4SI 0 "register_operand" "=x")
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(sign_extend:V4SI
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(vec_select:V4QI
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(vec_duplicate:V16QI
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(match_operand:V4QI 1 "nonimmediate_operand" "xm"))
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(match_operand:V16QI 1 "nonimmediate_operand" "xm")
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(parallel [(const_int 0)
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(const_int 1)
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(const_int 2)
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@ -9670,22 +9632,7 @@
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[(set (match_operand:V2DI 0 "register_operand" "=x")
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(sign_extend:V2DI
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(vec_select:V2QI
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(match_operand:V16QI 1 "register_operand" "x")
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(parallel [(const_int 0)
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(const_int 1)]))))]
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"TARGET_SSE4_1"
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"%vpmovsxbq\t{%1, %0|%0, %1}"
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[(set_attr "type" "ssemov")
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(set_attr "prefix_extra" "1")
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(set_attr "prefix" "maybe_vex")
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(set_attr "mode" "TI")])
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(define_insn "*sse4_1_extendv2qiv2di2"
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[(set (match_operand:V2DI 0 "register_operand" "=x")
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(sign_extend:V2DI
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(vec_select:V2QI
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(vec_duplicate:V16QI
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(match_operand:V2QI 1 "nonimmediate_operand" "xm"))
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(match_operand:V16QI 1 "nonimmediate_operand" "xm")
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(parallel [(const_int 0)
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(const_int 1)]))))]
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"TARGET_SSE4_1"
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@ -9699,24 +9646,7 @@
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[(set (match_operand:V4SI 0 "register_operand" "=x")
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(sign_extend:V4SI
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(vec_select:V4HI
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(match_operand:V8HI 1 "register_operand" "x")
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(parallel [(const_int 0)
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(const_int 1)
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(const_int 2)
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(const_int 3)]))))]
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"TARGET_SSE4_1"
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"%vpmovsxwd\t{%1, %0|%0, %1}"
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[(set_attr "type" "ssemov")
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(set_attr "prefix_extra" "1")
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(set_attr "prefix" "maybe_vex")
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(set_attr "mode" "TI")])
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(define_insn "*sse4_1_extendv4hiv4si2"
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[(set (match_operand:V4SI 0 "register_operand" "=x")
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(sign_extend:V4SI
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(vec_select:V4HI
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(vec_duplicate:V8HI
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(match_operand:V2HI 1 "nonimmediate_operand" "xm"))
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(match_operand:V8HI 1 "nonimmediate_operand" "xm")
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(parallel [(const_int 0)
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(const_int 1)
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(const_int 2)
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@ -9732,22 +9662,7 @@
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[(set (match_operand:V2DI 0 "register_operand" "=x")
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(sign_extend:V2DI
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(vec_select:V2HI
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(match_operand:V8HI 1 "register_operand" "x")
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(parallel [(const_int 0)
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(const_int 1)]))))]
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"TARGET_SSE4_1"
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"%vpmovsxwq\t{%1, %0|%0, %1}"
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[(set_attr "type" "ssemov")
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(set_attr "prefix_extra" "1")
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(set_attr "prefix" "maybe_vex")
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(set_attr "mode" "TI")])
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(define_insn "*sse4_1_extendv2hiv2di2"
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[(set (match_operand:V2DI 0 "register_operand" "=x")
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(sign_extend:V2DI
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(vec_select:V2HI
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(vec_duplicate:V8HI
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(match_operand:V8HI 1 "nonimmediate_operand" "xm"))
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(match_operand:V8HI 1 "nonimmediate_operand" "xm")
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(parallel [(const_int 0)
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(const_int 1)]))))]
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"TARGET_SSE4_1"
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@ -9761,22 +9676,7 @@
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[(set (match_operand:V2DI 0 "register_operand" "=x")
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(sign_extend:V2DI
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(vec_select:V2SI
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(match_operand:V4SI 1 "register_operand" "x")
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(parallel [(const_int 0)
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(const_int 1)]))))]
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"TARGET_SSE4_1"
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"%vpmovsxdq\t{%1, %0|%0, %1}"
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[(set_attr "type" "ssemov")
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(set_attr "prefix_extra" "1")
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(set_attr "prefix" "maybe_vex")
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(set_attr "mode" "TI")])
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(define_insn "*sse4_1_extendv2siv2di2"
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[(set (match_operand:V2DI 0 "register_operand" "=x")
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(sign_extend:V2DI
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(vec_select:V2SI
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(vec_duplicate:V4SI
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(match_operand:V2SI 1 "nonimmediate_operand" "xm"))
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(match_operand:V4SI 1 "nonimmediate_operand" "xm")
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(parallel [(const_int 0)
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(const_int 1)]))))]
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"TARGET_SSE4_1"
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@ -9790,28 +9690,7 @@
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[(set (match_operand:V8HI 0 "register_operand" "=x")
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(zero_extend:V8HI
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(vec_select:V8QI
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(match_operand:V16QI 1 "register_operand" "x")
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(parallel [(const_int 0)
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(const_int 1)
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(const_int 2)
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(const_int 3)
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(const_int 4)
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(const_int 5)
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(const_int 6)
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(const_int 7)]))))]
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"TARGET_SSE4_1"
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"%vpmovzxbw\t{%1, %0|%0, %1}"
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[(set_attr "type" "ssemov")
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(set_attr "prefix_extra" "1")
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(set_attr "prefix" "maybe_vex")
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(set_attr "mode" "TI")])
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(define_insn "*sse4_1_zero_extendv8qiv8hi2"
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[(set (match_operand:V8HI 0 "register_operand" "=x")
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(zero_extend:V8HI
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(vec_select:V8QI
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(vec_duplicate:V16QI
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(match_operand:V8QI 1 "nonimmediate_operand" "xm"))
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(match_operand:V16QI 1 "nonimmediate_operand" "xm")
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(parallel [(const_int 0)
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(const_int 1)
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(const_int 2)
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@ -9831,24 +9710,7 @@
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[(set (match_operand:V4SI 0 "register_operand" "=x")
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(zero_extend:V4SI
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(vec_select:V4QI
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(match_operand:V16QI 1 "register_operand" "x")
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(parallel [(const_int 0)
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(const_int 1)
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(const_int 2)
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(const_int 3)]))))]
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"TARGET_SSE4_1"
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"%vpmovzxbd\t{%1, %0|%0, %1}"
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[(set_attr "type" "ssemov")
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(set_attr "prefix_extra" "1")
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(set_attr "prefix" "maybe_vex")
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(set_attr "mode" "TI")])
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|
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(define_insn "*sse4_1_zero_extendv4qiv4si2"
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[(set (match_operand:V4SI 0 "register_operand" "=x")
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(zero_extend:V4SI
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(vec_select:V4QI
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(vec_duplicate:V16QI
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(match_operand:V4QI 1 "nonimmediate_operand" "xm"))
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(match_operand:V16QI 1 "nonimmediate_operand" "xm")
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(parallel [(const_int 0)
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(const_int 1)
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(const_int 2)
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@ -9864,22 +9726,7 @@
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[(set (match_operand:V2DI 0 "register_operand" "=x")
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(zero_extend:V2DI
|
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(vec_select:V2QI
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(match_operand:V16QI 1 "register_operand" "x")
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(parallel [(const_int 0)
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(const_int 1)]))))]
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"TARGET_SSE4_1"
|
||||
"%vpmovzxbq\t{%1, %0|%0, %1}"
|
||||
[(set_attr "type" "ssemov")
|
||||
(set_attr "prefix_extra" "1")
|
||||
(set_attr "prefix" "maybe_vex")
|
||||
(set_attr "mode" "TI")])
|
||||
|
||||
(define_insn "*sse4_1_zero_extendv2qiv2di2"
|
||||
[(set (match_operand:V2DI 0 "register_operand" "=x")
|
||||
(zero_extend:V2DI
|
||||
(vec_select:V2QI
|
||||
(vec_duplicate:V16QI
|
||||
(match_operand:V2QI 1 "nonimmediate_operand" "xm"))
|
||||
(match_operand:V16QI 1 "nonimmediate_operand" "xm")
|
||||
(parallel [(const_int 0)
|
||||
(const_int 1)]))))]
|
||||
"TARGET_SSE4_1"
|
||||
@ -9893,24 +9740,7 @@
|
||||
[(set (match_operand:V4SI 0 "register_operand" "=x")
|
||||
(zero_extend:V4SI
|
||||
(vec_select:V4HI
|
||||
(match_operand:V8HI 1 "register_operand" "x")
|
||||
(parallel [(const_int 0)
|
||||
(const_int 1)
|
||||
(const_int 2)
|
||||
(const_int 3)]))))]
|
||||
"TARGET_SSE4_1"
|
||||
"%vpmovzxwd\t{%1, %0|%0, %1}"
|
||||
[(set_attr "type" "ssemov")
|
||||
(set_attr "prefix_extra" "1")
|
||||
(set_attr "prefix" "maybe_vex")
|
||||
(set_attr "mode" "TI")])
|
||||
|
||||
(define_insn "*sse4_1_zero_extendv4hiv4si2"
|
||||
[(set (match_operand:V4SI 0 "register_operand" "=x")
|
||||
(zero_extend:V4SI
|
||||
(vec_select:V4HI
|
||||
(vec_duplicate:V8HI
|
||||
(match_operand:V4HI 1 "nonimmediate_operand" "xm"))
|
||||
(match_operand:V8HI 1 "nonimmediate_operand" "xm")
|
||||
(parallel [(const_int 0)
|
||||
(const_int 1)
|
||||
(const_int 2)
|
||||
@ -9926,22 +9756,7 @@
|
||||
[(set (match_operand:V2DI 0 "register_operand" "=x")
|
||||
(zero_extend:V2DI
|
||||
(vec_select:V2HI
|
||||
(match_operand:V8HI 1 "register_operand" "x")
|
||||
(parallel [(const_int 0)
|
||||
(const_int 1)]))))]
|
||||
"TARGET_SSE4_1"
|
||||
"%vpmovzxwq\t{%1, %0|%0, %1}"
|
||||
[(set_attr "type" "ssemov")
|
||||
(set_attr "prefix_extra" "1")
|
||||
(set_attr "prefix" "maybe_vex")
|
||||
(set_attr "mode" "TI")])
|
||||
|
||||
(define_insn "*sse4_1_zero_extendv2hiv2di2"
|
||||
[(set (match_operand:V2DI 0 "register_operand" "=x")
|
||||
(zero_extend:V2DI
|
||||
(vec_select:V2HI
|
||||
(vec_duplicate:V8HI
|
||||
(match_operand:V2HI 1 "nonimmediate_operand" "xm"))
|
||||
(match_operand:V8HI 1 "nonimmediate_operand" "xm")
|
||||
(parallel [(const_int 0)
|
||||
(const_int 1)]))))]
|
||||
"TARGET_SSE4_1"
|
||||
@ -9955,22 +9770,7 @@
|
||||
[(set (match_operand:V2DI 0 "register_operand" "=x")
|
||||
(zero_extend:V2DI
|
||||
(vec_select:V2SI
|
||||
(match_operand:V4SI 1 "register_operand" "x")
|
||||
(parallel [(const_int 0)
|
||||
(const_int 1)]))))]
|
||||
"TARGET_SSE4_1"
|
||||
"%vpmovzxdq\t{%1, %0|%0, %1}"
|
||||
[(set_attr "type" "ssemov")
|
||||
(set_attr "prefix_extra" "1")
|
||||
(set_attr "prefix" "maybe_vex")
|
||||
(set_attr "mode" "TI")])
|
||||
|
||||
(define_insn "*sse4_1_zero_extendv2siv2di2"
|
||||
[(set (match_operand:V2DI 0 "register_operand" "=x")
|
||||
(zero_extend:V2DI
|
||||
(vec_select:V2SI
|
||||
(vec_duplicate:V4SI
|
||||
(match_operand:V2SI 1 "nonimmediate_operand" "xm"))
|
||||
(match_operand:V4SI 1 "nonimmediate_operand" "xm")
|
||||
(parallel [(const_int 0)
|
||||
(const_int 1)]))))]
|
||||
"TARGET_SSE4_1"
|
||||
|
||||
Loading…
Reference in New Issue
Block a user