re PR target/41900 (call *%esp shouldn't be generated because of CPU errata)
2009-11-13 Uros Bizjak <ubizjak@gmail.com> PR target/41900 (*call_pop_1, *call_1, *call_value_pop_1, *call_value_1): Use "lsm" as operand 1 constraint. * config/i386/predicates.md (call_insn_operand): Depend on index_register_operand to avoid %esp register. 2009-11-13 Uros Bizjak <ubizjak@gmail.com> Revert: 2009-11-03 Uros Bizjak <ubizjak@gmail.com> PR target/41900 * config/i386/i386.h (ix86_arch_indices) <X86_ARCH_CALL_ESP>: New. (TARGET_CALL_ESP): New define. * config/i386/i386.c (initial_ix86_tune_features): Initialize X86_ARCH_CALL_ESP. * config/i386/i386.md (*call_pop_1_esp, *call_1_esp, *call_value_pop_1_esp, *call_value_1_esp): Rename from *call_pop_1, *call_1, *call_value_pop_1 and *call_value_1. Depend on TARGET_CALL_ESP. (*call_pop_1, *call_1, *call_value_pop_1, *call_value_1): New patterns, use "lsm" as operand 1 constraint. * config/i386/predicates.md (call_insn_operand): Depend on index_register_operand for !TARGET_CALL_ESP to avoid %esp register. From-SVN: r154160
This commit is contained in:
Uros Bizjak
parent
0761b46229
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8410737add
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@ -1,3 +1,30 @@
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2009-11-13 Uros Bizjak <ubizjak@gmail.com>
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PR target/41900
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(*call_pop_1, *call_1, *call_value_pop_1, *call_value_1): Use "lsm"
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as operand 1 constraint.
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* config/i386/predicates.md (call_insn_operand): Depend on
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index_register_operand to avoid %esp register.
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2009-11-13 Uros Bizjak <ubizjak@gmail.com>
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Revert:
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2009-11-03 Uros Bizjak <ubizjak@gmail.com>
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PR target/41900
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* config/i386/i386.h (ix86_arch_indices) <X86_ARCH_CALL_ESP>: New.
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(TARGET_CALL_ESP): New define.
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* config/i386/i386.c (initial_ix86_tune_features): Initialize
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X86_ARCH_CALL_ESP.
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* config/i386/i386.md (*call_pop_1_esp, *call_1_esp,
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*call_value_pop_1_esp, *call_value_1_esp): Rename from *call_pop_1,
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*call_1, *call_value_pop_1 and *call_value_1. Depend on
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TARGET_CALL_ESP.
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(*call_pop_1, *call_1, *call_value_pop_1, *call_value_1):
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New patterns, use "lsm" as operand 1 constraint.
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* config/i386/predicates.md (call_insn_operand): Depend on
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index_register_operand for !TARGET_CALL_ESP to avoid %esp register.
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2009-11-13 Jason Merrill <jason@redhat.com>
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PR debug/26965
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@ -6,9 +33,9 @@
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2009-11-13 Andrey Belevantsev <abel@ispras.ru>
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PR rtl-optimization/41697
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* sel-sched-ir.c (fallthru_bb_of_jump): Bail out when a block with
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a conditional jump has a single successor.
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PR rtl-optimization/41697
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* sel-sched-ir.c (fallthru_bb_of_jump): Bail out when a block with
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a conditional jump has a single successor.
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2009-11-13 Andrey Belevantsev <abel@ispras.ru>
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@ -31,8 +58,8 @@
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per-insn data in smaller chunks.
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* sel-sched-ir.h (free_data_for_scheduled_insn): Export.
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* sel-sched.c (update_seqnos_and_stage): Free INSN_DEPS_CONTEXT
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in scheduled insn.
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in scheduled insn.
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2009-11-13 Uros Bizjak <ubizjak@gmail.com>
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* config/i386/i386.md (call_value): Fix comment.
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@ -101,7 +128,7 @@
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PR middle-end/41440
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* cfgexpand.c (expand_gimple_basic_block): Append NOP to a fallthru,
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single successor block, ending with jump created by RTL expander.
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2009-11-11 Jan Hubicka <jh@suse.cz>
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PR middle-end/41729
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@ -1553,11 +1553,6 @@ static unsigned int initial_ix86_arch_features[X86_ARCH_LAST] = {
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/* X86_ARCH_BSWAP: Byteswap was added for 80486. */
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~m_386,
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/* X86_ARCH_CALL_ESP: P6 processors will jump to the address after
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the decrement (so they will execute return address as code). See
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Pentium Pro errata 70, Pentium 2 errata A33, Pentium 3 errata E17. */
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~(m_386 | m_486 | m_PENT | m_PPRO),
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};
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static const unsigned int x86_accumulate_outgoing_args
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@ -402,7 +402,6 @@ enum ix86_arch_indices {
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X86_ARCH_CMPXCHG8B,
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X86_ARCH_XADD,
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X86_ARCH_BSWAP,
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X86_ARCH_CALL_ESP,
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X86_ARCH_LAST
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};
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@ -414,7 +413,6 @@ extern unsigned char ix86_arch_features[X86_ARCH_LAST];
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#define TARGET_CMPXCHG8B ix86_arch_features[X86_ARCH_CMPXCHG8B]
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#define TARGET_XADD ix86_arch_features[X86_ARCH_XADD]
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#define TARGET_BSWAP ix86_arch_features[X86_ARCH_BSWAP]
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#define TARGET_CALL_ESP ix86_arch_features[X86_ARCH_CALL_ESP]
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#define TARGET_FISTTP (TARGET_SSE3 && TARGET_80387)
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@ -14562,6 +14562,10 @@
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;; checked for calls. This is a bug in the generic code, but it isn't that
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;; easy to fix. Ignore it for now and be prepared to fix things up.
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;; P6 processors will jump to the address after the decrement when %esp
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;; is used as a call operand, so they will execute return address as a code.
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;; See Pentium Pro errata 70, Pentium 2 errata A33 and Pentium 3 errata E17.
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;; Call subroutine returning no value.
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(define_expand "call_pop"
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@ -14592,27 +14596,13 @@
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}
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[(set_attr "type" "call")])
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(define_insn "*call_pop_1_esp"
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[(call (mem:QI (match_operand:SI 0 "call_insn_operand" "rsm"))
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(match_operand:SI 1 "" ""))
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(set (reg:SI SP_REG)
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(plus:SI (reg:SI SP_REG)
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(match_operand:SI 2 "immediate_operand" "i")))]
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"!TARGET_64BIT && TARGET_CALL_ESP && !SIBLING_CALL_P (insn)"
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{
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if (constant_call_address_operand (operands[0], Pmode))
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return "call\t%P0";
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return "call\t%A0";
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}
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[(set_attr "type" "call")])
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(define_insn "*call_pop_1"
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[(call (mem:QI (match_operand:SI 0 "call_insn_operand" "lsm"))
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(match_operand:SI 1 "" ""))
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(set (reg:SI SP_REG)
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(plus:SI (reg:SI SP_REG)
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(match_operand:SI 2 "immediate_operand" "i")))]
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"!TARGET_64BIT && !TARGET_CALL_ESP && !SIBLING_CALL_P (insn)"
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"!TARGET_64BIT && !SIBLING_CALL_P (insn)"
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{
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if (constant_call_address_operand (operands[0], Pmode))
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return "call\t%P0";
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@ -14664,21 +14654,10 @@
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}
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[(set_attr "type" "call")])
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(define_insn "*call_1_esp"
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[(call (mem:QI (match_operand:SI 0 "call_insn_operand" "rsm"))
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(match_operand 1 "" ""))]
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"!TARGET_64BIT && TARGET_CALL_ESP && !SIBLING_CALL_P (insn)"
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{
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if (constant_call_address_operand (operands[0], Pmode))
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return "call\t%P0";
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return "call\t%A0";
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}
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[(set_attr "type" "call")])
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(define_insn "*call_1"
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[(call (mem:QI (match_operand:SI 0 "call_insn_operand" "lsm"))
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(match_operand 1 "" ""))]
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"!TARGET_64BIT && !TARGET_CALL_ESP && !SIBLING_CALL_P (insn)"
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"!TARGET_64BIT && !SIBLING_CALL_P (insn)"
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{
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if (constant_call_address_operand (operands[0], Pmode))
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return "call\t%P0";
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@ -21158,8 +21137,9 @@
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[(set (match_operand 0 "" "")
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(call (mem:QI (match_operand:SI 1 "constant_call_address_operand" ""))
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(match_operand:SI 2 "" "")))
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(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
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(match_operand:SI 3 "immediate_operand" "")))]
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(set (reg:SI SP_REG)
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(plus:SI (reg:SI SP_REG)
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(match_operand:SI 3 "immediate_operand" "")))]
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"!TARGET_64BIT"
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{
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if (SIBLING_CALL_P (insn))
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@ -21169,27 +21149,14 @@
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}
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[(set_attr "type" "callv")])
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(define_insn "*call_value_pop_1_esp"
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[(set (match_operand 0 "" "")
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(call (mem:QI (match_operand:SI 1 "call_insn_operand" "rsm"))
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(match_operand:SI 2 "" "")))
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(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
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(match_operand:SI 3 "immediate_operand" "i")))]
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"!TARGET_64BIT && TARGET_CALL_ESP && !SIBLING_CALL_P (insn)"
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{
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if (constant_call_address_operand (operands[1], Pmode))
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return "call\t%P1";
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return "call\t%A1";
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}
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[(set_attr "type" "callv")])
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(define_insn "*call_value_pop_1"
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[(set (match_operand 0 "" "")
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(call (mem:QI (match_operand:SI 1 "call_insn_operand" "lsm"))
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(match_operand:SI 2 "" "")))
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(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
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(match_operand:SI 3 "immediate_operand" "i")))]
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"!TARGET_64BIT && !TARGET_CALL_ESP && !SIBLING_CALL_P (insn)"
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(set (reg:SI SP_REG)
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(plus:SI (reg:SI SP_REG)
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(match_operand:SI 3 "immediate_operand" "i")))]
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"!TARGET_64BIT && !SIBLING_CALL_P (insn)"
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{
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if (constant_call_address_operand (operands[1], Pmode))
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return "call\t%P1";
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@ -21201,8 +21168,9 @@
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[(set (match_operand 0 "" "")
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(call (mem:QI (match_operand:SI 1 "sibcall_insn_operand" "s,U"))
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(match_operand:SI 2 "" "")))
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(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
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(match_operand:SI 3 "immediate_operand" "i,i")))]
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(set (reg:SI SP_REG)
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(plus:SI (reg:SI SP_REG)
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(match_operand:SI 3 "immediate_operand" "i,i")))]
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"!TARGET_64BIT && SIBLING_CALL_P (insn)"
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"@
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jmp\t%P1
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@ -21261,23 +21229,11 @@
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}
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[(set_attr "type" "callv")])
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(define_insn "*call_value_1_esp"
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[(set (match_operand 0 "" "")
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(call (mem:QI (match_operand:SI 1 "call_insn_operand" "rsm"))
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(match_operand:SI 2 "" "")))]
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"!TARGET_64BIT && TARGET_CALL_ESP && !SIBLING_CALL_P (insn)"
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{
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if (constant_call_address_operand (operands[1], Pmode))
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return "call\t%P1";
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return "call\t%A1";
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}
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[(set_attr "type" "callv")])
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(define_insn "*call_value_1"
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[(set (match_operand 0 "" "")
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(call (mem:QI (match_operand:SI 1 "call_insn_operand" "lsm"))
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(match_operand:SI 2 "" "")))]
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"!TARGET_64BIT && !TARGET_CALL_ESP && !SIBLING_CALL_P (insn)"
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"!TARGET_64BIT && !SIBLING_CALL_P (insn)"
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{
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if (constant_call_address_operand (operands[1], Pmode))
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return "call\t%P1";
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@ -561,9 +561,7 @@
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;; Test for a valid operand for a call instruction.
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(define_predicate "call_insn_operand"
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(ior (match_operand 0 "constant_call_address_operand")
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(ior (and (match_operand 0 "register_no_elim_operand")
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(ior (match_test "TARGET_CALL_ESP")
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(match_operand 0 "index_register_operand")))
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(ior (match_operand 0 "index_register_operand")
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(match_operand 0 "memory_operand"))))
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;; Similarly, but for tail calls, in which we cannot allow memory references.
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