re PR rtl-optimization/60763 (ICE in extract_insn starting with rev 208984)
gcc/ PR target/60763 * config/rs6000/vsx.md (vsx_xscvdpspn_scalar): Change input to DImode. * config/rs6000/rs6000.md (reload_vsx_from_gprsf): Update accordingly. Use gen_rtx_REG rather than simplify_gen_subreg for op0_di. From-SVN: r209223
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@ -1,3 +1,10 @@
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2014-04-08 Richard Sandiford <rdsandiford@googlemail.com>
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PR target/60763
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* config/rs6000/vsx.md (vsx_xscvdpspn_scalar): Change input to DImode.
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* config/rs6000/rs6000.md (reload_vsx_from_gprsf): Update accordingly.
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Use gen_rtx_REG rather than simplify_gen_subreg for op0_di.
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2014-04-08 Richard Biener <rguenther@suse.de>
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2014-04-08 Richard Biener <rguenther@suse.de>
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PR middle-end/60706
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PR middle-end/60706
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@ -10029,13 +10029,16 @@
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rtx op0 = operands[0];
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rtx op0 = operands[0];
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rtx op1 = operands[1];
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rtx op1 = operands[1];
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rtx op2 = operands[2];
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rtx op2 = operands[2];
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rtx op0_di = simplify_gen_subreg (DImode, op0, SFmode, 0);
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/* Also use the destination register to hold the unconverted DImode value.
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This is conceptually a separate value from OP0, so we use gen_rtx_REG
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rather than simplify_gen_subreg. */
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rtx op0_di = gen_rtx_REG (DImode, REGNO (op0));
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rtx op1_di = simplify_gen_subreg (DImode, op1, SFmode, 0);
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rtx op1_di = simplify_gen_subreg (DImode, op1, SFmode, 0);
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/* Move SF value to upper 32-bits for xscvspdpn. */
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/* Move SF value to upper 32-bits for xscvspdpn. */
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emit_insn (gen_ashldi3 (op2, op1_di, GEN_INT (32)));
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emit_insn (gen_ashldi3 (op2, op1_di, GEN_INT (32)));
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emit_move_insn (op0_di, op2);
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emit_move_insn (op0_di, op2);
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emit_insn (gen_vsx_xscvspdpn_directmove (op0, op0));
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emit_insn (gen_vsx_xscvspdpn_directmove (op0, op0_di));
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DONE;
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DONE;
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}
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}
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[(set_attr "length" "8")
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[(set_attr "length" "8")
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@ -1223,7 +1223,7 @@
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;; Used by direct move to move a SFmode value from GPR to VSX register
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;; Used by direct move to move a SFmode value from GPR to VSX register
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(define_insn "vsx_xscvspdpn_directmove"
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(define_insn "vsx_xscvspdpn_directmove"
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[(set (match_operand:SF 0 "vsx_register_operand" "=wa")
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[(set (match_operand:SF 0 "vsx_register_operand" "=wa")
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(unspec:SF [(match_operand:SF 1 "vsx_register_operand" "wa")]
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(unspec:SF [(match_operand:DI 1 "vsx_register_operand" "wa")]
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UNSPEC_VSX_CVSPDPN))]
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UNSPEC_VSX_CVSPDPN))]
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"TARGET_XSCVSPDPN"
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"TARGET_XSCVSPDPN"
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"xscvspdpn %x0,%x1"
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"xscvspdpn %x0,%x1"
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