entered into RCS
From-SVN: r28
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Charles Hannum
parent
acde64ae54
commit
8480102e8b
299
gcc/config/fx80/fx80.c
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299
gcc/config/fx80/fx80.c
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/* Subroutines for insn-output.c for Alliant FX computers.
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Copyright (C) 1989,1991 Free Software Foundation, Inc.
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This file is part of GNU CC.
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GNU CC is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2, or (at your option)
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any later version.
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GNU CC is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with GNU CC; see the file COPYING. If not, write to
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the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
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/* Some output-actions in alliant.md need these. */
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#include <stdio.h>
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#include "config.h"
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#include "rtl.h"
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#include "regs.h"
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#include "hard-reg-set.h"
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#include "real.h"
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#include "insn-config.h"
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#include "conditions.h"
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#include "insn-flags.h"
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#include "output.h"
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#include "insn-attr.h"
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/* Index into this array by (register number >> 3) to find the
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smallest class which contains that register. */
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enum reg_class regno_reg_class[]
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= { DATA_REGS, ADDR_REGS, FP_REGS };
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static rtx find_addr_reg ();
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char *
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output_btst (operands, countop, dataop, insn, signpos)
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rtx *operands;
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rtx countop, dataop;
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rtx insn;
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int signpos;
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{
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operands[0] = countop;
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operands[1] = dataop;
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if (GET_CODE (countop) == CONST_INT)
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{
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register int count = INTVAL (countop);
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/* If COUNT is bigger than size of storage unit in use,
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advance to the containing unit of same size. */
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if (count > signpos)
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{
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int offset = (count & ~signpos) / 8;
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count = count & signpos;
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operands[1] = dataop = adj_offsettable_operand (dataop, offset);
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}
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if (count == signpos)
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cc_status.flags = CC_NOT_POSITIVE | CC_Z_IN_NOT_N;
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else
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cc_status.flags = CC_NOT_NEGATIVE | CC_Z_IN_NOT_N;
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/* These three statements used to use next_insns_test_no...
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but it appears that this should do the same job. */
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if (count == 31
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&& next_insn_tests_no_inequality (insn))
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return "tst%.l %1";
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if (count == 15
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&& next_insn_tests_no_inequality (insn))
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return "tst%.w %1";
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if (count == 7
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&& next_insn_tests_no_inequality (insn))
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return "tst%.b %1";
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cc_status.flags = CC_NOT_NEGATIVE;
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}
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return "btst %0,%1";
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}
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/* Return the best assembler insn template
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for moving operands[1] into operands[0] as a fullword. */
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static char *
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singlemove_string (operands)
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rtx *operands;
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{
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if (operands[1] != const0_rtx)
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return "mov%.l %1,%0";
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if (! ADDRESS_REG_P (operands[0]))
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return "clr%.l %0";
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return "sub%.l %0,%0";
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}
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/* Output assembler code to perform a doubleword move insn
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with operands OPERANDS. */
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char *
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output_move_double (operands)
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rtx *operands;
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{
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enum { REGOP, OFFSOP, MEMOP, PUSHOP, POPOP, CNSTOP, RNDOP } optype0, optype1;
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rtx latehalf[2];
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rtx addreg0 = 0, addreg1 = 0;
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/* First classify both operands. */
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if (REG_P (operands[0]))
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optype0 = REGOP;
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else if (offsettable_memref_p (operands[0]))
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optype0 = OFFSOP;
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else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
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optype0 = POPOP;
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else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
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optype0 = PUSHOP;
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else if (GET_CODE (operands[0]) == MEM)
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optype0 = MEMOP;
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else
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optype0 = RNDOP;
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if (REG_P (operands[1]))
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optype1 = REGOP;
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else if (CONSTANT_P (operands[1]))
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optype1 = CNSTOP;
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else if (offsettable_memref_p (operands[1]))
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optype1 = OFFSOP;
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else if (GET_CODE (XEXP (operands[1], 0)) == POST_INC)
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optype1 = POPOP;
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else if (GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
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optype1 = PUSHOP;
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else if (GET_CODE (operands[1]) == MEM)
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optype1 = MEMOP;
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else
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optype1 = RNDOP;
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/* Check for the cases that the operand constraints are not
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supposed to allow to happen. Abort if we get one,
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because generating code for these cases is painful. */
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if (optype0 == RNDOP || optype1 == RNDOP)
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abort ();
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/* If one operand is decrementing and one is incrementing
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decrement the former register explicitly
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and change that operand into ordinary indexing. */
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if (optype0 == PUSHOP && optype1 == POPOP)
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{
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operands[0] = XEXP (XEXP (operands[0], 0), 0);
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output_asm_insn ("subq%.l %#8,%0", operands);
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operands[0] = gen_rtx (MEM, DImode, operands[0]);
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optype0 = OFFSOP;
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}
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if (optype0 == POPOP && optype1 == PUSHOP)
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{
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operands[1] = XEXP (XEXP (operands[1], 0), 0);
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output_asm_insn ("subq%.l %#8,%1", operands);
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operands[1] = gen_rtx (MEM, DImode, operands[1]);
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optype1 = OFFSOP;
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}
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/* If an operand is an unoffsettable memory ref, find a register
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we can increment temporarily to make it refer to the second word. */
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if (optype0 == MEMOP)
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addreg0 = find_addr_reg (XEXP (operands[0], 0));
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if (optype1 == MEMOP)
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addreg1 = find_addr_reg (XEXP (operands[1], 0));
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/* Ok, we can do one word at a time.
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Normally we do the low-numbered word first,
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but if either operand is autodecrementing then we
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do the high-numbered word first.
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In either case, set up in LATEHALF the operands to use
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for the high-numbered word and in some cases alter the
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operands in OPERANDS to be suitable for the low-numbered word. */
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if (optype0 == REGOP)
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latehalf[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
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else if (optype0 == OFFSOP)
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latehalf[0] = adj_offsettable_operand (operands[0], 4);
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else
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latehalf[0] = operands[0];
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if (optype1 == REGOP)
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latehalf[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
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else if (optype1 == OFFSOP)
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latehalf[1] = adj_offsettable_operand (operands[1], 4);
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else if (optype1 == CNSTOP)
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{
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if (GET_CODE (operands[1]) == CONST_DOUBLE)
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split_double (operands[1], &operands[1], &latehalf[1]);
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else if (CONSTANT_P (operands[1]))
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{
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latehalf[1] = operands[1];
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operands[1] = const0_rtx;
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}
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}
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else
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latehalf[1] = operands[1];
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/* If insn is effectively movd N(sp),-(sp) then we will do the
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high word first. We should use the adjusted operand 1 (which is N+4(sp))
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for the low word as well, to compensate for the first decrement of sp. */
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if (optype0 == PUSHOP
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&& REGNO (XEXP (XEXP (operands[0], 0), 0)) == STACK_POINTER_REGNUM
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&& reg_overlap_mentioned_p (stack_pointer_rtx, operands[1]))
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operands[1] = latehalf[1];
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/* If one or both operands autodecrementing,
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do the two words, high-numbered first. */
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/* Likewise, the first move would clobber the source of the second one,
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do them in the other order. This happens only for registers;
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such overlap can't happen in memory unless the user explicitly
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sets it up, and that is an undefined circumstance. */
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if (optype0 == PUSHOP || optype1 == PUSHOP
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|| (optype0 == REGOP && optype1 == REGOP
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&& REGNO (operands[0]) == REGNO (latehalf[1])))
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{
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/* Make any unoffsettable addresses point at high-numbered word. */
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if (addreg0)
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output_asm_insn ("addql %#4,%0", &addreg0);
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if (addreg1)
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output_asm_insn ("addql %#4,%0", &addreg1);
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/* Do that word. */
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output_asm_insn (singlemove_string (latehalf), latehalf);
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/* Undo the adds we just did. */
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if (addreg0)
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output_asm_insn ("subql %#4,%0", &addreg0);
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if (addreg1)
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output_asm_insn ("subql %#4,%0", &addreg1);
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/* Do low-numbered word. */
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return singlemove_string (operands);
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}
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/* Normal case: do the two words, low-numbered first. */
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output_asm_insn (singlemove_string (operands), operands);
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/* Make any unoffsettable addresses point at high-numbered word. */
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if (addreg0)
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output_asm_insn ("addql %#4,%0", &addreg0);
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if (addreg1)
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output_asm_insn ("addql %#4,%0", &addreg1);
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/* Do that word. */
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output_asm_insn (singlemove_string (latehalf), latehalf);
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/* Undo the adds we just did. */
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if (addreg0)
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output_asm_insn ("subql %#4,%0", &addreg0);
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if (addreg1)
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output_asm_insn ("subql %#4,%0", &addreg1);
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return "";
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}
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/* Return a REG that occurs in ADDR with coefficient 1.
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ADDR can be effectively incremented by incrementing REG. */
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static rtx
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find_addr_reg (addr)
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rtx addr;
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{
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while (GET_CODE (addr) == PLUS)
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{
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if (GET_CODE (XEXP (addr, 0)) == REG)
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addr = XEXP (addr, 0);
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else if (GET_CODE (XEXP (addr, 1)) == REG)
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addr = XEXP (addr, 1);
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else if (CONSTANT_P (XEXP (addr, 0)))
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addr = XEXP (addr, 1);
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else if (CONSTANT_P (XEXP (addr, 1)))
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addr = XEXP (addr, 0);
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else
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abort ();
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}
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if (GET_CODE (addr) == REG)
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return addr;
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abort ();
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}
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int
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standard_SunFPA_constant_p (x)
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rtx x;
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{
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return( 0 );
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}
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