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[AArch64 3/3] Fix XOR_one_cmpl pattern; add SIMD-reg variants for BIC,ORN,EON

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gcc/:

	* config/aarch64/aarch64.c (<LOGICAL:optab>_one_cmpl<mode>3):
	Reparameterize to...
	(<NLOGICAL:optab>_one_cmpl<mode>3): with extra SIMD-register variant.
	(xor_one_cmpl<mode>3): New define_insn_and_split.

	* config/aarch64/iterators.md (NLOGICAL): New define_code_iterator.

gcc/testsuite/:

	* gcc.target/aarch64/eon_1.c: New test.

From-SVN: r218961
This commit is contained in:
Alan Lawrence 2014-12-19 17:59:23 +00:00 committed by Alan Lawrence
parent fe82d1f27e
commit 84be603271
5 changed files with 84 additions and 7 deletions
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9
gcc/ChangeLog
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@ -1,3 +1,12 @@
2014-12-19 Alan Lawrence <alan.lawrence@arm.com>
* config/aarch64/aarch64.c (<LOGICAL:optab>_one_cmpl<mode>3):
Reparameterize to...
(<NLOGICAL:optab>_one_cmpl<mode>3): with extra SIMD-register variant.
(xor_one_cmpl<mode>3): New define_insn_and_split.
* config/aarch64/iterators.md (NLOGICAL): New define_code_iterator.
2014-12-19 Alan Lawrence <alan.lawrence@arm.com>
* config/aarch64/aarch64.md (<optab><mode>3, one_cmpl<mode>2):

36
gcc/config/aarch64/aarch64.md
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@ -3015,14 +3015,36 @@
[(set_attr "type" "logic_shift_imm")]
)
(define_insn "*<LOGICAL:optab>_one_cmpl<mode>3"
[(set (match_operand:GPI 0 "register_operand" "=r")
(LOGICAL:GPI (not:GPI
(match_operand:GPI 1 "register_operand" "r"))
(match_operand:GPI 2 "register_operand" "r")))]
;; Binary logical operators negating one operand, i.e. (a & !b), (a | !b).
(define_insn "*<NLOGICAL:optab>_one_cmpl<mode>3"
[(set (match_operand:GPI 0 "register_operand" "=r,w")
(NLOGICAL:GPI (not:GPI (match_operand:GPI 1 "register_operand" "r,w"))
(match_operand:GPI 2 "register_operand" "r,w")))]
""
"<LOGICAL:nlogical>\\t%<w>0, %<w>2, %<w>1"
[(set_attr "type" "logic_reg")]
"@
<NLOGICAL:nlogical>\\t%<w>0, %<w>2, %<w>1
<NLOGICAL:nlogical>\\t%0.<Vbtype>, %2.<Vbtype>, %1.<Vbtype>"
[(set_attr "type" "logic_reg,neon_logic")
(set_attr "simd" "*,yes")]
)
;; (xor (not a) b) is simplify_rtx-ed down to (not (xor a b)).
;; eon does not operate on SIMD registers so the vector variant must be split.
(define_insn_and_split "*xor_one_cmpl<mode>3"
[(set (match_operand:GPI 0 "register_operand" "=r,w")
(not:GPI (xor:GPI (match_operand:GPI 1 "register_operand" "r,?w")
(match_operand:GPI 2 "register_operand" "r,w"))))]
""
"eon\\t%<w>0, %<w>1, %<w>2" ;; For GPR registers (only).
"reload_completed && (which_alternative == 1)" ;; For SIMD registers.
[(set (match_operand:GPI 0 "register_operand" "=w")
(xor:GPI (match_operand:GPI 1 "register_operand" "w")
(match_operand:GPI 2 "register_operand" "w")))
(set (match_dup 0) (not:GPI (match_dup 0)))]
""
[(set_attr "type" "logic_reg,multiple")
(set_attr "simd" "*,yes")]
)
(define_insn "*and_one_cmpl<mode>3_compare0"

3
gcc/config/aarch64/iterators.md
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@ -665,6 +665,9 @@
;; Code iterator for logical operations
(define_code_iterator LOGICAL [and ior xor])
;; Code iterator for logical operations whose :nlogical works on SIMD registers.
(define_code_iterator NLOGICAL [and ior])
;; Code iterator for sign/zero extension
(define_code_iterator ANY_EXTEND [sign_extend zero_extend])

4
gcc/testsuite/ChangeLog
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@ -1,3 +1,7 @@
2014-12-19 Alan Lawrence <alan.lawrence@arm.com>
* gcc.target/aarch64/eon_1.c: New test.
2014-12-19 Paolo Carlini <paolo.carlini@oracle.com>
PR c++/60493

39
gcc/testsuite/gcc.target/aarch64/eon_1.c Normal file
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@ -0,0 +1,39 @@
/* { dg-do compile } */
/* { dg-options "-O2" } */
/* { dg-final { scan-assembler-not "\tf?mov\t" } } */
typedef long long int64_t;
typedef int64_t int64x1_t __attribute__ ((__vector_size__ (8)));
/* { dg-final { scan-assembler-times "\\teon\\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+" 1 } } */
int64_t
test_eon (int64_t a, int64_t b)
{
return a ^ ~b;
}
/* { dg-final { scan-assembler-times "\\tmvn\\tx\[0-9\]+, x\[0-9\]+" 1 } } */
int64_t
test_not (int64_t a)
{
return ~a;
}
/* There is no eon for SIMD regs; we prefer eor+mvn to mov+mov+eon+mov. */
/* { dg-final { scan-assembler-times "\\teor\\tv\[0-9\]+\.8b, v\[0-9\]+\.8b, v\[0-9\]+\.8b" 1 } } */
/* { dg-final { scan-assembler-times "\\tmvn\\tv\[0-9\]+\.8b, v\[0-9\]+\.8b" 2 } } */
int64x1_t
test_vec_eon (int64x1_t a, int64x1_t b)
{
return a ^ ~b;
}
int64x1_t
test_vec_not (int64x1_t a)
{
return ~a;
}