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re PR target/55673 (Reversed before/after handling in sparc_emit_membar_for_model) 

PR target/55673
	* config/sparc/sparc.c (sparc_emit_membar_for_model): Fix reversed
	handling of before and after cases.
	* config/sparc/sync.md (atomic_store): Fix pasto.

Co-Authored-By: Tomash Brechko <tomash.brechko@gmail.com>

From-SVN: r194532
This commit is contained in:
Eric Botcazou 2012-12-16 10:26:08 +00:00 committed by Eric Botcazou
parent 5543ab362e
commit 84ec8cbc99
3 changed files with 24 additions and 17 deletions
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8
gcc/ChangeLog
View File

@ -1,3 +1,11 @@
2012-12-16 Eric Botcazou <ebotcazou@adacore.com>
Tomash Brechko <tomash.brechko@gmail.com>
PR target/55673
* config/sparc/sparc.c (sparc_emit_membar_for_model): Fix reversed
handling of before and after cases.
* config/sparc/sync.md (atomic_store): Fix pasto.
2012-12-14 Yvan Roux <yvan.roux@linaro.org>
* optabs.c (expand_atomic_store): Elide redundant model test.

24
gcc/config/sparc/sparc.c
View File

@ -10948,18 +10948,6 @@ sparc_emit_membar_for_model (enum memmodel model,
}
if (before_after & 1)
{
if (model == MEMMODEL_ACQUIRE
|| model == MEMMODEL_ACQ_REL
|| model == MEMMODEL_SEQ_CST)
{
if (load_store & 1)
mm |= LoadLoad | LoadStore;
if (load_store & 2)
mm |= StoreLoad | StoreStore;
}
}
if (before_after & 2)
{
if (model == MEMMODEL_RELEASE
|| model == MEMMODEL_ACQ_REL
@ -10971,6 +10959,18 @@ sparc_emit_membar_for_model (enum memmodel model,
mm |= LoadStore | StoreStore;
}
}
if (before_after & 2)
{
if (model == MEMMODEL_ACQUIRE
|| model == MEMMODEL_ACQ_REL
|| model == MEMMODEL_SEQ_CST)
{
if (load_store & 1)
mm |= LoadLoad | LoadStore;
if (load_store & 2)
mm |= StoreLoad | StoreStore;
}
}
/* Remove the bits implied by the system memory model. */
mm &= ~implied;

9
gcc/config/sparc/sync.md
View File

@ -35,8 +35,7 @@
(define_expand "membar"
[(set (match_dup 1)
(unspec:BLK [(match_dup 1)
(match_operand:SI 0 "const_int_operand")]
(unspec:BLK [(match_dup 1) (match_operand:SI 0 "const_int_operand")]
UNSPEC_MEMBAR))]
"TARGET_V8 || TARGET_V9"
{
@ -66,7 +65,7 @@
"stbar"
[(set_attr "type" "multi")])
;; For V8, LDSTUB has the effect of membar #StoreLoad
;; For V8, LDSTUB has the effect of membar #StoreLoad.
(define_insn "*membar_storeload"
[(set (match_operand:BLK 0 "" "")
(unspec:BLK [(match_dup 0) (const_int 2)] UNSPEC_MEMBAR))]
@ -123,8 +122,8 @@
[(set_attr "type" "load,fpload")])
(define_expand "atomic_store<mode>"
[(match_operand:I 0 "register_operand" "")
(match_operand:I 1 "memory_operand" "")
[(match_operand:I 0 "memory_operand" "")
(match_operand:I 1 "register_operand" "")
(match_operand:SI 2 "const_int_operand" "")]
""
{