ia64-protos.h (ia64_expand_prediction): Remove.
* config/ia64/ia64-protos.h (ia64_expand_prediction): Remove. * config/ia64/ia64.c (ia64_expand_prediction): Move code ... (ia64_print_operand) [+]: ... here. Use current_output_insn. * config/ia64/ia64.h (PRINT_OPERAND_PUNCT_VALID_P): New. * config/ia64/ia64.md (all branch/call patterns): Use %+. From-SVN: r34318
This commit is contained in:
parent
18153f6ceb
commit
85548039c4
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@ -1,3 +1,11 @@
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2000-05-31 Richard Henderson <rth@cygnus.com>
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* config/ia64/ia64-protos.h (ia64_expand_prediction): Remove.
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* config/ia64/ia64.c (ia64_expand_prediction): Move code ...
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(ia64_print_operand) [+]: ... here. Use current_output_insn.
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* config/ia64/ia64.h (PRINT_OPERAND_PUNCT_VALID_P): New.
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* config/ia64/ia64.md (all branch/call patterns): Use %+.
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2000-05-31 Richard Henderson <rth@cygnus.com>
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* ifcvt.c (cond_exec_process_insns): Don't ever ignore clobbers.
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@ -61,7 +61,6 @@ extern enum reg_class ia64_secondary_reload_class PARAMS((enum reg_class,
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enum machine_mode,
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rtx));
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extern void ia64_reorg PARAMS((rtx));
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extern const char *ia64_expand_prediction PARAMS((rtx, const char *));
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#endif /* RTX_CODE */
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#ifdef TREE_CODE
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@ -1714,8 +1714,6 @@ ia64_print_operand (file, x, code)
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{
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switch (code)
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{
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/* XXX Add other codes here. */
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case 0:
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/* Handled below. */
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break;
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@ -1840,6 +1838,36 @@ ia64_print_operand (file, x, code)
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output_operand_lossage ("invalid %%r value");
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return;
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case '+':
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{
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const char *which;
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/* For conditional branches, returns or calls, substitute
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sptk, dptk, dpnt, or spnt for %s. */
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x = find_reg_note (current_output_insn, REG_BR_PROB, 0);
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if (x)
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{
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int pred_val = INTVAL (XEXP (x, 0));
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/* Guess top and bottom 10% statically predicted. */
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if (pred_val < REG_BR_PROB_BASE / 10)
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which = ".spnt";
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else if (pred_val < REG_BR_PROB_BASE / 2)
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which = ".dpnt";
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else if (pred_val < REG_BR_PROB_BASE * 9 / 10)
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which = ".dptk";
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else
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which = ".sptk";
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}
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else if (GET_CODE (current_output_insn) == CALL_INSN)
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which = ".sptk";
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else
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which = ".dptk";
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fputs (which, file);
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return;
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}
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default:
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output_operand_lossage ("ia64_print_operand: unknown code");
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return;
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@ -1872,48 +1900,6 @@ ia64_print_operand (file, x, code)
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return;
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}
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/* For conditional branches, returns or calls, substitute
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sptk, dptk, dpnt, or spnt for %s. */
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const char *
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ia64_expand_prediction (insn, template)
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rtx insn;
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const char *template;
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{
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static char const pred_name[4][5] = {
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"spnt", "dpnt", "dptk", "sptk"
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};
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static char new_template[64];
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int pred_val, pred_which;
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rtx note;
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note = find_reg_note (insn, REG_BR_PROB, 0);
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if (note)
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{
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pred_val = INTVAL (XEXP (note, 0));
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/* Guess top and bottom 10% statically predicted. */
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if (pred_val < REG_BR_PROB_BASE / 10)
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pred_which = 0;
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else if (pred_val < REG_BR_PROB_BASE / 2)
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pred_which = 1;
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else if (pred_val < REG_BR_PROB_BASE * 9 / 10)
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pred_which = 2;
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else
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pred_which = 3;
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}
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else
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pred_which = 2;
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if (strlen (template) >= sizeof (new_template) - 3)
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abort ();
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sprintf (new_template, template, pred_name[pred_which]);
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return new_template;
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}
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/* This function returns the register class required for a secondary
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@ -2469,7 +2469,7 @@ do { \
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/* ??? Keep this around for now, as we might need it later. */
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/* #define PRINT_OPERAND_PUNCT_VALID_P(CODE) */
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#define PRINT_OPERAND_PUNCT_VALID_P(CODE) ((CODE) == '+')
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/* A C compound statement to output to stdio stream STREAM the assembler syntax
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for an instruction operand that is a memory reference whose address is X. X
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@ -2162,7 +2162,7 @@
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(label_ref (match_operand 2 "" ""))
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(pc)))]
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""
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"* return ia64_expand_prediction (insn, \"(%%J0) br.cond.%s %%l2\");"
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"(%J0) br.cond%+ %l2"
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[(set_attr "type" "B")
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(set_attr "predicable" "no")])
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@ -2174,7 +2174,7 @@
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(pc)
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(label_ref (match_operand 2 "" ""))))]
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""
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"* return ia64_expand_prediction (insn, \"(%%j0) br.cond.%s %%l2\");"
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"(%j0) br.cond%+ %l2"
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[(set_attr "type" "B")
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(set_attr "predicable" "no")])
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@ -2717,14 +2717,7 @@
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(match_operand 1 "" ""))
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(clobber (match_operand:DI 2 "register_operand" "=b"))]
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""
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"*
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{
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operands[3] = current_insn_predicate;
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if (operands[3] != NULL_RTX)
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return ia64_expand_prediction (insn, \"(%%J3) br.call.%s.many %2 = %0\");
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else
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return \"br.call.sptk.many %2 = %0\";
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}"
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"br.call%+.many %2 = %0"
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[(set_attr "type" "B")])
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(define_insn "*call_internal1"
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(use (reg:DI 1))
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(clobber (match_operand:DI 2 "register_operand" "=b"))]
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""
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"*
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{
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operands[3] = current_insn_predicate;
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if (operands[3] != NULL_RTX)
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return ia64_expand_prediction (insn, \"(%%J3) br.call.%s.many %2 = %0\");
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else
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return \"br.call.sptk.many %2 = %0\";
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}"
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"br.call%+.many %2 = %0"
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[(set_attr "type" "B")])
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;; Subroutine call instruction returning a value. Operand 0 is the hard
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(match_operand 2 "" "")))
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(clobber (match_operand:DI 3 "register_operand" "=b"))]
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""
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"*
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{
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operands[4] = current_insn_predicate;
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if (operands[4] != NULL_RTX)
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return ia64_expand_prediction (insn, \"(%%J4) br.call.%s.many %3 = %1\");
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else
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return \"br.call.sptk.many %3 = %1\";
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}"
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"br.call%+.many %3 = %1"
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[(set_attr "type" "B")])
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(define_insn "*call_value_internal1"
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(use (reg:DI 1))
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(clobber (match_operand:DI 3 "register_operand" "=b"))]
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""
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"*
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{
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operands[4] = current_insn_predicate;
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if (operands[4] != NULL_RTX)
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return ia64_expand_prediction (insn, \"(%%J4) br.call.%s.many %3 = %1\");
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else
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return \"br.call.sptk.many %3 = %1\";
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}"
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"br.call%+.many %3 = %1"
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[(set_attr "type" "B")])
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(define_insn "*call_multiple_values_internal1"
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(use (reg:DI 1))
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(clobber (match_operand:DI 4 "register_operand" "=b"))])]
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""
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"*
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{
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operands[5] = current_insn_predicate;
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if (operands[5] != NULL_RTX)
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return ia64_expand_prediction (insn, \"(%%J5) br.call.%s.many %4 = %2\");
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else
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return \"br.call.sptk.many %4 = %2\";
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}"
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"br.call%+.many %4 = %2"
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[(set_attr "type" "B")])
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;; Call subroutine returning any type.
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(return)
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(pc)))]
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"ia64_direct_return ()"
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"* return ia64_expand_prediction (insn, \"(%%J0) br.ret.%s.many rp\");"
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"(%%J0) br.ret%+.many rp"
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[(set_attr "type" "B")
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(set_attr "predicable" "no")])
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(pc)
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(return)))]
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"ia64_direct_return ()"
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"* return ia64_expand_prediction (insn, \"(%%j0) br.ret.%s.many rp\");"
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"(%%j0) br.ret%+.many rp"
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[(set_attr "type" "B")
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(set_attr "predicable" "no")])
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