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A15 neon description.

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2012-10-18  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
	    Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
            Sameera Deshpande  <sameera.deshpande@arm.com>

           * config/arm/cortex-a15-neon.md: New file.
           * config/arm/cortex-a15.md (cortex_a15_call): Adjust reservation.
           (cortex_a15_load1): Likewise.
           (cortex_a15_load3): Likewise.
           (cortex_a15_store1): Likewise.
           (cortex_a15_store3): Likewise.
           (cortex-a15-neon.md): Include.




Co-Authored-By: Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
Co-Authored-By: Sameera Deshpande <sameera.deshpande@arm.com>

From-SVN: r192569
This commit is contained in:
Matthew Gretton-Dann 2012-10-18 16:43:15 +00:00 committed by Ramana Radhakrishnan
parent 1ba24090f6
commit 855828f1b1
3 changed files with 1245 additions and 16 deletions
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12
gcc/ChangeLog
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@ -1,3 +1,15 @@
2012-10-18 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
Sameera Deshpande <sameera.deshpande@arm.com>
* config/arm/cortex-a15-neon.md: New file.
* config/arm/cortex-a15.md (cortex_a15_call): Adjust reservation.
(cortex_a15_load1): Likewise.
(cortex_a15_load3): Likewise.
(cortex_a15_store1): Likewise.
(cortex_a15_store3): Likewise.
(cortex-a15-neon.md): Include.
2012-10-18 Segher Boessenkool <segher@kernel.crashing.org> 2012-10-18 Segher Boessenkool <segher@kernel.crashing.org>
* config/rs6000/altivec.md (altivec_lvsl, altivec_lvsr): Add mode. * config/rs6000/altivec.md (altivec_lvsl, altivec_lvsr): Add mode.

1215
gcc/config/arm/cortex-a15-neon.md Normal file
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34
gcc/config/arm/cortex-a15.md
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@ -24,7 +24,7 @@
;; The Cortex-A15 core is modelled as a triple issue pipeline that has ;; The Cortex-A15 core is modelled as a triple issue pipeline that has
;; the following dispatch units. ;; the following dispatch units.
;; 1. Two pipelines for simple integer operations: SX1, SX2 ;; 1. Two pipelines for simple integer operations: SX1, SX2
;; 2. Two pipelines for Neon and FP data-processing operations: CX1, CX2 ;; 2. Individual units for Neon and FP operations as in cortex-a15-neon.md
;; 3. One pipeline for branch operations: BX ;; 3. One pipeline for branch operations: BX
;; 4. One pipeline for integer multiply and divide operations: MX ;; 4. One pipeline for integer multiply and divide operations: MX
;; 5. Two pipelines for load and store operations: LS1, LS2 ;; 5. Two pipelines for load and store operations: LS1, LS2
@ -44,7 +44,6 @@
;; The main dispatch units ;; The main dispatch units
(define_cpu_unit "ca15_sx1, ca15_sx2" "cortex_a15") (define_cpu_unit "ca15_sx1, ca15_sx2" "cortex_a15")
(define_cpu_unit "ca15_cx1, ca15_cx2" "cortex_a15")
(define_cpu_unit "ca15_ls1, ca15_ls2" "cortex_a15") (define_cpu_unit "ca15_ls1, ca15_ls2" "cortex_a15")
(define_cpu_unit "ca15_bx, ca15_mx" "cortex_a15") (define_cpu_unit "ca15_bx, ca15_mx" "cortex_a15")
@ -129,20 +128,6 @@
(eq_attr "neon_type" "none"))) (eq_attr "neon_type" "none")))
"ca15_issue1,ca15_bx") "ca15_issue1,ca15_bx")
;; We lie with calls. They take up all issue slots, and form a block in the
;; pipeline. The result however is available the next cycle.
;;
;; Addition of new units requires this to be updated.
(define_insn_reservation "cortex_a15_call" 1
(and (eq_attr "tune" "cortexa15")
(and (eq_attr "type" "call")
(eq_attr "neon_type" "none")))
"ca15_issue3,\
ca15_sx1+ca15_sx2+ca15_bx+ca15_mx+ca15_cx1+ca15_cx2+ca15_ls1+ca15_ls2,\
ca15_sx1_alu+ca15_sx1_shf+ca15_sx1_sat+ca15_sx2_alu+ca15_sx2_shf\
+ca15_sx2_sat+ca15_ldr+ca15_str")
;; Load-store execution Unit ;; Load-store execution Unit
;; ;;
;; Loads of up to two words. ;; Loads of up to two words.
@ -173,6 +158,23 @@
(eq_attr "neon_type" "none"))) (eq_attr "neon_type" "none")))
"ca15_issue2,ca15_ls1+ca15_ls2,ca15_str,ca15_str") "ca15_issue2,ca15_ls1+ca15_ls2,ca15_str,ca15_str")
;; We include Neon.md here to ensure that the branch can block the Neon units.
(include "cortex-a15-neon.md")
;; We lie with calls. They take up all issue slots, and form a block in the
;; pipeline. The result however is available the next cycle.
(define_insn_reservation "cortex_a15_call" 1
(and (eq_attr "tune" "cortexa15")
(and (eq_attr "type" "call")
(eq_attr "neon_type" "none")))
"ca15_issue3,\
ca15_sx1+ca15_sx2+ca15_bx+ca15_mx+ca15_cx_ij+ca15_cx_ik+ca15_ls1+ca15_ls2+\
ca15_cx_imac1+ca15_cx_ialu1+ca15_cx_ialu2+ca15_cx_ishf+\
ca15_cx_acc+ca15_cx_fmul1+ca15_cx_fmul2+ca15_cx_fmul3+ca15_cx_fmul4+\
ca15_cx_falu1+ca15_cx_falu2+ca15_cx_falu3+ca15_cx_falu4+ca15_cx_vfp_i,\
ca15_sx1_alu+ca15_sx1_shf+ca15_sx1_sat+ca15_sx2_alu+\
ca15_sx2_shf+ca15_sx2_sat+ca15_ldr+ca15_str")
;; Simple execution unit bypasses ;; Simple execution unit bypasses
(define_bypass 1 "cortex_a15_alu" (define_bypass 1 "cortex_a15_alu"
"cortex_a15_alu,cortex_a15_alu_shift,cortex_a15_alu_shift_reg") "cortex_a15_alu,cortex_a15_alu_shift,cortex_a15_alu_shift_reg")