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re PR target/71663 (aarch64 Vector initialization can be improved slightly)

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PR target/71663
gcc
	* config/aarch64/aarch64.c (aarch64_expand_vector_init):
	Improve vector initialization code gen for only variable case.

gcc/testsuite
	* gcc.target/aarch64/vect-init-1.c: Newtestcase.
	* gcc.target/aarch64/vect-init-2.c: Likewise.
	* gcc.target/aarch64/vect-init-3.c: Likewise.
	* gcc.target/aarch64/vect-init-4.c: Likewise.
	* gcc.target/aarch64/vect-init-5.c: Likewise.


Co-Authored-By: Naveen H.S <Naveen.Hurugalawadi@cavium.com>

From-SVN: r249187
This commit is contained in:
Andrew Pinski 2017-06-14 10:20:07 +00:00 committed by Naveen H.S
parent bee9e49f6c
commit 85c1b6d7c8
8 changed files with 128 additions and 4 deletions
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7
gcc/ChangeLog
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@ -1,3 +1,10 @@
2017-06-14 Andrew Pinski <apinski@cavium.com>
Naveen H.S <Naveen.Hurugalawadi@cavium.com>
PR target/71663
* config/aarch64/aarch64.c (aarch64_expand_vector_init):
Improve vector initialization code gen for only variable case.
2017-06-14 Eric Botcazou <ebotcazou@adacore.com>
* config/sparc/driver-sparc.c (cpu_names): Add SPARC-T5 entry.

55
gcc/config/aarch64/aarch64.c
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@ -11707,6 +11707,57 @@ aarch64_expand_vector_init (rtx target, rtx vals)
return;
}
enum insn_code icode = optab_handler (vec_set_optab, mode);
gcc_assert (icode != CODE_FOR_nothing);
/* If there are only variable elements, try to optimize
the insertion using dup for the most common element
followed by insertions. */
/* The algorithm will fill matches[*][0] with the earliest matching element,
and matches[X][1] with the count of duplicate elements (if X is the
earliest element which has duplicates). */
if (n_var == n_elts && n_elts <= 16)
{
int matches[16][2] = {0};
for (int i = 0; i < n_elts; i++)
{
for (int j = 0; j <= i; j++)
{
if (rtx_equal_p (XVECEXP (vals, 0, i), XVECEXP (vals, 0, j)))
{
matches[i][0] = j;
matches[j][1]++;
break;
}
}
}
int maxelement = 0;
int maxv = 0;
for (int i = 0; i < n_elts; i++)
if (matches[i][1] > maxv)
{
maxelement = i;
maxv = matches[i][1];
}
/* Create a duplicate of the most common element. */
rtx x = copy_to_mode_reg (inner_mode, XVECEXP (vals, 0, maxelement));
aarch64_emit_move (target, gen_rtx_VEC_DUPLICATE (mode, x));
/* Insert the rest. */
for (int i = 0; i < n_elts; i++)
{
rtx x = XVECEXP (vals, 0, i);
if (matches[i][0] == maxelement)
continue;
x = copy_to_mode_reg (inner_mode, x);
emit_insn (GEN_FCN (icode) (target, x, GEN_INT (i)));
}
return;
}
/* Initialise a vector which is part-variable. We want to first try
to build those lanes which are constant in the most efficient way we
can. */
@ -11740,10 +11791,6 @@ aarch64_expand_vector_init (rtx target, rtx vals)
}
/* Insert the variable lanes directly. */
enum insn_code icode = optab_handler (vec_set_optab, mode);
gcc_assert (icode != CODE_FOR_nothing);
for (int i = 0; i < n_elts; i++)
{
rtx x = XVECEXP (vals, 0, i);

10
gcc/testsuite/ChangeLog
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@ -1,3 +1,13 @@
2017-06-14 Andrew Pinski <apinski@cavium.com>
Naveen H.S <Naveen.Hurugalawadi@cavium.com>
PR target/71663
* gcc.target/aarch64/vect-init-1.c: Newtestcase.
* gcc.target/aarch64/vect-init-2.c: Likewise.
* gcc.target/aarch64/vect-init-3.c: Likewise.
* gcc.target/aarch64/vect-init-4.c: Likewise.
* gcc.target/aarch64/vect-init-5.c: Likewise.
2017-06-14 Paolo Carlini <paolo.carlini@oracle.com>
PR c++/58541

12
gcc/testsuite/gcc.target/aarch64/vect-init-1.c Normal file
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@ -0,0 +1,12 @@
/* { dg-do compile } */
/* { dg-options "-O2" } */
#define vector __attribute__((vector_size(16)))
vector float combine (float a, float b, float c, float d)
{
return (vector float) { a, b, c, d };
}
/* { dg-final { scan-assembler-not "movi\t" } } */
/* { dg-final { scan-assembler-not "orr\t" } } */

12
gcc/testsuite/gcc.target/aarch64/vect-init-2.c Normal file
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@ -0,0 +1,12 @@
/* { dg-do compile } */
/* { dg-options "-O2" } */
#define vector __attribute__((vector_size(16)))
vector float combine (float a, float b, float d)
{
return (vector float) { a, b, a, d };
}
/* { dg-final { scan-assembler-not "movi\t" } } */
/* { dg-final { scan-assembler-not "orr\t" } } */

12
gcc/testsuite/gcc.target/aarch64/vect-init-3.c Normal file
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@ -0,0 +1,12 @@
/* { dg-do compile } */
/* { dg-options "-O2" } */
#define vector __attribute__((vector_size(16)))
vector float combine (float a, float b)
{
return (vector float) { a, b, a, b };
}
/* { dg-final { scan-assembler-not "movi\t" } } */
/* { dg-final { scan-assembler-not "orr\t" } } */

12
gcc/testsuite/gcc.target/aarch64/vect-init-4.c Normal file
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@ -0,0 +1,12 @@
/* { dg-do compile } */
/* { dg-options "-O2" } */
#define vector __attribute__((vector_size(16)))
vector float combine (float a, float b)
{
return (vector float) { a, b, b, a };
}
/* { dg-final { scan-assembler-not "movi\t" } } */
/* { dg-final { scan-assembler-not "orr\t" } } */

12
gcc/testsuite/gcc.target/aarch64/vect-init-5.c Normal file
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@ -0,0 +1,12 @@
/* { dg-do compile } */
/* { dg-options "-O2" } */
#define vector __attribute__((vector_size(16)))
vector float combine (float a, float b)
{
return (vector float) { a, b, a, a };
}
/* { dg-final { scan-assembler-not "movi\t" } } */
/* { dg-final { scan-assembler-not "orr\t" } } */