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nvptx: Support 16-bit shifts and extendqihi2 

Add support for 16-bits shifts and for sign extension from 8 bits to
16 bits.

This patch has been tested on nvptx-none with no new regressions.

2020-07-28  Roger Sayle  <roger@nextmovesoftware.com>
	    Tom de Vries  <tdevries@suse.de>

gcc/ChangeLog:

	* config/nvptx/nvptx.md (extendqihi2): New instruction.
	(ashl<mode>3, ashr<mode>3, lshr<mode>3): Support HImode.

gcc/testsuite/ChangeLog:

	* gcc.target/nvptx/cvt.c: New test.
	* gcc.target/nvptx/shift16.c: New test.
This commit is contained in:
Tom de Vries 2020-07-28 15:13:54 +02:00
parent 134051f16b
commit 862a58ed83
3 changed files with 59 additions and 9 deletions
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25
gcc/config/nvptx/nvptx.md
View File

@ -319,6 +319,13 @@
%.\\tld%A1%u1\\t%0, %1;"
[(set_attr "subregs_ok" "true")])
(define_insn "extendqihi2"
[(set (match_operand:HI 0 "nvptx_register_operand" "=R")
(sign_extend:HI (match_operand:QI 1 "nvptx_register_operand" "R")))]
""
"%.\\tcvt.s16.s8\\t%0, %1;"
[(set_attr "subregs_ok" "true")])
(define_insn "extend<mode>si2"
[(set (match_operand:SI 0 "nvptx_register_operand" "=R,R")
(sign_extend:SI (match_operand:QHIM 1 "nvptx_nonimmediate_operand" "R,m")))]
@ -556,23 +563,23 @@
;; Shifts
(define_insn "ashl<mode>3"
[(set (match_operand:SDIM 0 "nvptx_register_operand" "=R")
(ashift:SDIM (match_operand:SDIM 1 "nvptx_register_operand" "R")
(match_operand:SI 2 "nvptx_nonmemory_operand" "Ri")))]
[(set (match_operand:HSDIM 0 "nvptx_register_operand" "=R")
(ashift:HSDIM (match_operand:HSDIM 1 "nvptx_register_operand" "R")
(match_operand:SI 2 "nvptx_nonmemory_operand" "Ri")))]
""
"%.\\tshl.b%T0\\t%0, %1, %2;")
(define_insn "ashr<mode>3"
[(set (match_operand:SDIM 0 "nvptx_register_operand" "=R")
(ashiftrt:SDIM (match_operand:SDIM 1 "nvptx_register_operand" "R")
(match_operand:SI 2 "nvptx_nonmemory_operand" "Ri")))]
[(set (match_operand:HSDIM 0 "nvptx_register_operand" "=R")
(ashiftrt:HSDIM (match_operand:HSDIM 1 "nvptx_register_operand" "R")
(match_operand:SI 2 "nvptx_nonmemory_operand" "Ri")))]
""
"%.\\tshr.s%T0\\t%0, %1, %2;")
(define_insn "lshr<mode>3"
[(set (match_operand:SDIM 0 "nvptx_register_operand" "=R")
(lshiftrt:SDIM (match_operand:SDIM 1 "nvptx_register_operand" "R")
(match_operand:SI 2 "nvptx_nonmemory_operand" "Ri")))]
[(set (match_operand:HSDIM 0 "nvptx_register_operand" "=R")
(lshiftrt:HSDIM (match_operand:HSDIM 1 "nvptx_register_operand" "R")
(match_operand:SI 2 "nvptx_nonmemory_operand" "Ri")))]
""
"%.\\tshr.u%T0\\t%0, %1, %2;")

13
gcc/testsuite/gcc.target/nvptx/cvt.c Normal file
View File

@ -0,0 +1,13 @@
/* { dg-do assemble } */
/* { dg-options "-O2 -save-temps" } */
signed short s;
signed char c;
void
foo (void)
{
s = c;
}
/* { dg-final { scan-assembler "(?n)cvt\\.s16\\.s8.*%r" } } */

30
gcc/testsuite/gcc.target/nvptx/shift16.c Normal file
View File

@ -0,0 +1,30 @@
/* { dg-do assemble } */
/* { dg-options "-O2 -save-temps" } */
void
foo (unsigned short u)
{
volatile unsigned short u2 = u << 5;
}
void
foo2 (short s)
{
volatile unsigned short s2 = s << 5;
}
void
foo3 (unsigned short u)
{
volatile unsigned short u2 = u >> 5;
}
void
foo4 (signed short s)
{
volatile signed short s2 = s >> 5;
}
/* { dg-final { scan-assembler-times "(?n)shl\\.b16.*%r" 2 } } */
/* { dg-final { scan-assembler "(?n)shr\\.u16.*%r" } } */
/* { dg-final { scan-assembler "(?n)shr\\.s16.*%r" } } */