nvptx: Support 16-bit shifts and extendqihi2
Add support for 16-bits shifts and for sign extension from 8 bits to 16 bits. This patch has been tested on nvptx-none with no new regressions. 2020-07-28 Roger Sayle <roger@nextmovesoftware.com> Tom de Vries <tdevries@suse.de> gcc/ChangeLog: * config/nvptx/nvptx.md (extendqihi2): New instruction. (ashl<mode>3, ashr<mode>3, lshr<mode>3): Support HImode. gcc/testsuite/ChangeLog: * gcc.target/nvptx/cvt.c: New test. * gcc.target/nvptx/shift16.c: New test.
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@ -319,6 +319,13 @@
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%.\\tld%A1%u1\\t%0, %1;"
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[(set_attr "subregs_ok" "true")])
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(define_insn "extendqihi2"
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[(set (match_operand:HI 0 "nvptx_register_operand" "=R")
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(sign_extend:HI (match_operand:QI 1 "nvptx_register_operand" "R")))]
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""
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"%.\\tcvt.s16.s8\\t%0, %1;"
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[(set_attr "subregs_ok" "true")])
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(define_insn "extend<mode>si2"
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[(set (match_operand:SI 0 "nvptx_register_operand" "=R,R")
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(sign_extend:SI (match_operand:QHIM 1 "nvptx_nonimmediate_operand" "R,m")))]
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@ -556,22 +563,22 @@
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;; Shifts
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(define_insn "ashl<mode>3"
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[(set (match_operand:SDIM 0 "nvptx_register_operand" "=R")
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(ashift:SDIM (match_operand:SDIM 1 "nvptx_register_operand" "R")
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[(set (match_operand:HSDIM 0 "nvptx_register_operand" "=R")
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(ashift:HSDIM (match_operand:HSDIM 1 "nvptx_register_operand" "R")
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(match_operand:SI 2 "nvptx_nonmemory_operand" "Ri")))]
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""
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"%.\\tshl.b%T0\\t%0, %1, %2;")
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(define_insn "ashr<mode>3"
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[(set (match_operand:SDIM 0 "nvptx_register_operand" "=R")
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(ashiftrt:SDIM (match_operand:SDIM 1 "nvptx_register_operand" "R")
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[(set (match_operand:HSDIM 0 "nvptx_register_operand" "=R")
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(ashiftrt:HSDIM (match_operand:HSDIM 1 "nvptx_register_operand" "R")
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(match_operand:SI 2 "nvptx_nonmemory_operand" "Ri")))]
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""
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"%.\\tshr.s%T0\\t%0, %1, %2;")
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(define_insn "lshr<mode>3"
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[(set (match_operand:SDIM 0 "nvptx_register_operand" "=R")
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(lshiftrt:SDIM (match_operand:SDIM 1 "nvptx_register_operand" "R")
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[(set (match_operand:HSDIM 0 "nvptx_register_operand" "=R")
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(lshiftrt:HSDIM (match_operand:HSDIM 1 "nvptx_register_operand" "R")
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(match_operand:SI 2 "nvptx_nonmemory_operand" "Ri")))]
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""
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"%.\\tshr.u%T0\\t%0, %1, %2;")
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@ -0,0 +1,13 @@
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/* { dg-do assemble } */
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/* { dg-options "-O2 -save-temps" } */
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signed short s;
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signed char c;
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void
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foo (void)
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{
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s = c;
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}
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/* { dg-final { scan-assembler "(?n)cvt\\.s16\\.s8.*%r" } } */
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@ -0,0 +1,30 @@
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/* { dg-do assemble } */
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/* { dg-options "-O2 -save-temps" } */
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void
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foo (unsigned short u)
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{
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volatile unsigned short u2 = u << 5;
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}
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void
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foo2 (short s)
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{
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volatile unsigned short s2 = s << 5;
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}
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void
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foo3 (unsigned short u)
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{
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volatile unsigned short u2 = u >> 5;
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}
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void
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foo4 (signed short s)
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{
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volatile signed short s2 = s >> 5;
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}
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/* { dg-final { scan-assembler-times "(?n)shl\\.b16.*%r" 2 } } */
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/* { dg-final { scan-assembler "(?n)shr\\.u16.*%r" } } */
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/* { dg-final { scan-assembler "(?n)shr\\.s16.*%r" } } */
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