re PR target/31019 (Microoptimization of the i386 and x86_64 compilers)
PR target/31019 * config/i386/i386.h (TUNEMASK): Redefine to use ix86_tune_mask. (ARCHMASK): Define. (TARGET_CMOVE): Use ARCHMASK. (TARGET_CMPXCHG): Ditto. (TARGET_CMPXCHG8B): Ditto. (TARGET_XADD): Ditto. (TARGET_BSWAP): Ditto. * config/i386/i386.c (ix86_tune_mask): New global variable. (ix86_arch_mask): Ditto. (override_options): Initialize ix86_tune_mask and ix86_arch_mask. Use ARCHMASK to clear MASK_NO_FANCY_MATH_387 in target_flags. Co-Authored-By: Michael Meissner <michael.meissner@amd.com> From-SVN: r122473
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@ -1,3 +1,20 @@
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2007-03-02 Uros Bizjak <ubizjak@gmail.com>
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Michael Meissner <michael.meissner@amd.com>
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PR target/31019
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* config/i386/i386.h (TUNEMASK): Redefine to use ix86_tune_mask.
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(ARCHMASK): Define.
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(TARGET_CMOVE): Use ARCHMASK.
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(TARGET_CMPXCHG): Ditto.
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(TARGET_CMPXCHG8B): Ditto.
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(TARGET_XADD): Ditto.
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(TARGET_BSWAP): Ditto.
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* config/i386/i386.c (ix86_tune_mask): New global variable.
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(ix86_arch_mask): Ditto.
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(override_options): Initialize ix86_tune_mask and
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ix86_arch_mask. Use ARCHMASK to clear MASK_NO_FANCY_MATH_387 in
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target_flags.
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2007-03-02 Ben Elliston <bje@au.ibm.com>
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PR 30992
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@ -984,23 +984,25 @@ const struct processor_costs *ix86_cost = &pentium_cost;
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#define m_486 (1<<PROCESSOR_I486)
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#define m_PENT (1<<PROCESSOR_PENTIUM)
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#define m_PPRO (1<<PROCESSOR_PENTIUMPRO)
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#define m_GEODE (1<<PROCESSOR_GEODE)
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#define m_K6_GEODE (m_K6 | m_GEODE)
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#define m_K6 (1<<PROCESSOR_K6)
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#define m_ATHLON (1<<PROCESSOR_ATHLON)
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#define m_PENT4 (1<<PROCESSOR_PENTIUM4)
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#define m_K8 (1<<PROCESSOR_K8)
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#define m_ATHLON_K8 (m_K8 | m_ATHLON)
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#define m_AMDFAM10 (1<<PROCESSOR_AMDFAM10)
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#define m_NOCONA (1<<PROCESSOR_NOCONA)
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#define m_CORE2 (1<<PROCESSOR_CORE2)
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#define m_GEODE (1<<PROCESSOR_GEODE)
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#define m_K6 (1<<PROCESSOR_K6)
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#define m_K6_GEODE (m_K6 | m_GEODE)
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#define m_K8 (1<<PROCESSOR_K8)
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#define m_ATHLON (1<<PROCESSOR_ATHLON)
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#define m_ATHLON_K8 (m_K8 | m_ATHLON)
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#define m_AMDFAM10 (1<<PROCESSOR_AMDFAM10)
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#define m_ATHLON_K8_AMDFAM10 (m_K8 | m_ATHLON | m_AMDFAM10)
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#define m_GENERIC32 (1<<PROCESSOR_GENERIC32)
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#define m_GENERIC64 (1<<PROCESSOR_GENERIC64)
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#define m_GENERIC (m_GENERIC32 | m_GENERIC64)
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#define m_ATHLON_K8_AMDFAM10 (m_K8 | m_ATHLON | m_AMDFAM10)
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/* Generic instruction choice should be common subset of supported CPUs
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(PPro/PENT4/NOCONA/CORE2/Athlon/K8). */
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#define m_GENERIC (m_GENERIC32 | m_GENERIC64)
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/* Leave is not affecting Nocona SPEC2000 results negatively, so enabling for
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Generic64 seems like good code size tradeoff. We can't enable it for 32bit
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@ -1395,8 +1397,11 @@ enum fpmath_unit ix86_fpmath;
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/* Which cpu are we scheduling for. */
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enum processor_type ix86_tune;
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int ix86_tune_mask;
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/* Which instruction set architecture to use. */
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enum processor_type ix86_arch;
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int ix86_arch_mask;
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/* true if sse prefetch instruction is not NOOP. */
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int x86_prefetch_sse;
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@ -2074,8 +2079,10 @@ override_options (void)
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if (! strcmp (ix86_arch_string, processor_alias_table[i].name))
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{
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ix86_arch = processor_alias_table[i].processor;
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ix86_arch_mask = 1 << ix86_arch;
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/* Default cpu tuning to the architecture. */
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ix86_tune = ix86_arch;
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ix86_tune_mask = 1 << ix86_tune;
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if (processor_alias_table[i].flags & PTA_MMX
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&& !(target_flags_explicit & MASK_MMX))
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target_flags |= MASK_MMX;
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@ -2276,7 +2283,7 @@ override_options (void)
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/* If the architecture always has an FPU, turn off NO_FANCY_MATH_387,
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since the insns won't need emulation. */
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if (x86_arch_always_fancy_math_387 & (1 << ix86_arch))
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if (x86_arch_always_fancy_math_387 & ARCHMASK)
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target_flags &= ~MASK_NO_FANCY_MATH_387;
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/* Likewise, if the target doesn't have a 387, or we've specified
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@ -179,7 +179,6 @@ extern const struct processor_costs *ix86_cost;
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#define TARGET_GENERIC (TARGET_GENERIC32 || TARGET_GENERIC64)
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#define TARGET_AMDFAM10 (ix86_tune == PROCESSOR_AMDFAM10)
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#define TUNEMASK (1 << ix86_tune)
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extern const int x86_use_leave, x86_push_memory, x86_zero_extend_with_and;
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extern const int x86_use_bit_test, x86_cmove, x86_deep_branch;
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extern const int x86_branch_hints, x86_unroll_strlen;
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@ -208,6 +207,9 @@ extern const int x86_bswap;
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extern const int x86_partial_flag_reg_stall;
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extern int x86_prefetch_sse, x86_cmpxchg16b;
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#define TUNEMASK ix86_tune_mask
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#define ARCHMASK ix86_arch_mask
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#define TARGET_USE_LEAVE (x86_use_leave & TUNEMASK)
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#define TARGET_PUSH_MEMORY (x86_push_memory & TUNEMASK)
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#define TARGET_ZERO_EXTEND_WITH_AND (x86_zero_extend_with_and & TUNEMASK)
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@ -215,7 +217,7 @@ extern int x86_prefetch_sse, x86_cmpxchg16b;
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#define TARGET_UNROLL_STRLEN (x86_unroll_strlen & TUNEMASK)
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/* For sane SSE instruction set generation we need fcomi instruction. It is
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safe to enable all CMOVE instructions. */
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#define TARGET_CMOVE ((x86_cmove & (1 << ix86_arch)) || TARGET_SSE)
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#define TARGET_CMOVE ((x86_cmove & ARCHMASK) || TARGET_SSE)
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#define TARGET_FISTTP (TARGET_SSE3 && TARGET_80387)
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#define TARGET_DEEP_BRANCH_PREDICTION (x86_deep_branch & TUNEMASK)
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#define TARGET_BRANCH_PREDICTION_HINTS (x86_branch_hints & TUNEMASK)
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@ -276,11 +278,11 @@ extern int x86_prefetch_sse, x86_cmpxchg16b;
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#define TARGET_ANY_GNU_TLS (TARGET_GNU_TLS || TARGET_GNU2_TLS)
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#define TARGET_SUN_TLS (ix86_tls_dialect == TLS_DIALECT_SUN)
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#define TARGET_CMPXCHG (x86_cmpxchg & (1 << ix86_arch))
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#define TARGET_CMPXCHG8B (x86_cmpxchg8b & (1 << ix86_arch))
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#define TARGET_CMPXCHG (x86_cmpxchg & ARCHMASK)
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#define TARGET_CMPXCHG8B (x86_cmpxchg8b & ARCHMASK)
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#define TARGET_CMPXCHG16B (x86_cmpxchg16b)
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#define TARGET_XADD (x86_xadd & (1 << ix86_arch))
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#define TARGET_BSWAP (x86_bswap & (1 << ix86_arch))
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#define TARGET_XADD (x86_xadd & ARCHMASK)
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#define TARGET_BSWAP (x86_bswap & ARCHMASK)
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#ifndef TARGET_64BIT_DEFAULT
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#define TARGET_64BIT_DEFAULT 0
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@ -2130,7 +2132,10 @@ enum processor_type
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};
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extern enum processor_type ix86_tune;
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extern int ix86_tune_mask;
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extern enum processor_type ix86_arch;
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extern int ix86_arch_mask;
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enum fpmath_unit
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{
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