diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 3e087775050..c5900668f45 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,16 @@ +2003-04-28 Richard Henderson + + * config/sparc/sparc.c (print_operand): Add 's' to sign-extend. + * config/sparc/sparc.md (const_mulsidi3_v8plus): Fix mode of + integral constant mult operand. + (const_mulsidi3_sp32, const_mulsidi3_sp64): Likewise. + (const_smulsi3_highpart_v8plus): Likewise. + (const_smulsi3_highpart): Likewise. + (const_umulsidi3_sp32): Likewise; sign-extend it in the output. + (const_umulsidi3_sp64, const_umulsidi3_v8plus): Likewise. + (const_umulsi3_highpart_v8plus): Likewise. + (const_umulsi3_highpart): Likewise. + 2003-04-28 David O'Brien * config/i386/x86-64.h (NO_PROFILE_COUNTERS, HAVE_AS_DWARF2_DEBUG_LINE): diff --git a/gcc/config/sparc/sparc.c b/gcc/config/sparc/sparc.c index 2ac680629fa..857fe3f321b 100644 --- a/gcc/config/sparc/sparc.c +++ b/gcc/config/sparc/sparc.c @@ -6472,6 +6472,21 @@ print_operand (file, x, code) output_address (XEXP (x, 0)); return; + case 's': + { + /* Print a sign-extended 32-bit value. */ + HOST_WIDE_INT i; + if (GET_CODE(x) == CONST_INT) + i = INTVAL (x); + else if (GET_CODE(x) == CONST_DOUBLE) + i = CONST_DOUBLE_LOW (x); + else + output_operand_lossage ("invalid %%s operand"); + i = trunc_int_for_mode (i, SImode); + fprintf (file, HOST_WIDE_INT_PRINT_DEC, i); + return; + } + case 0: /* Do nothing special. */ break; diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md index 36b213d63d9..4c66a7867fa 100644 --- a/gcc/config/sparc/sparc.md +++ b/gcc/config/sparc/sparc.md @@ -5323,7 +5323,7 @@ (define_insn "const_mulsidi3_v8plus" [(set (match_operand:DI 0 "register_operand" "=h,r") (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r,r")) - (match_operand:SI 2 "small_int" "I,I"))) + (match_operand:DI 2 "small_int" "I,I"))) (clobber (match_scratch:SI 3 "=X,&h"))] "TARGET_V8PLUS" "@ @@ -5364,7 +5364,7 @@ (define_insn "const_mulsidi3_sp32" [(set (match_operand:DI 0 "register_operand" "=r") (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r")) - (match_operand:SI 2 "small_int" "I")))] + (match_operand:DI 2 "small_int" "I")))] "TARGET_HARD_MUL32" { return TARGET_SPARCLET @@ -5381,7 +5381,7 @@ (define_insn "const_mulsidi3_sp64" [(set (match_operand:DI 0 "register_operand" "=r") (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r")) - (match_operand:SI 2 "small_int" "I")))] + (match_operand:DI 2 "small_int" "I")))] "TARGET_DEPRECATED_V8_INSNS && TARGET_ARCH64" "smul\t%1, %2, %0" [(set_attr "type" "imul")]) @@ -5453,7 +5453,7 @@ [(set (match_operand:SI 0 "register_operand" "=h,r") (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r,r")) - (match_operand 2 "small_int" "i,i")) + (match_operand:DI 2 "small_int" "i,i")) (match_operand:SI 3 "const_int_operand" "i,i")))) (clobber (match_scratch:SI 4 "=X,&h"))] "TARGET_V8PLUS" @@ -5480,7 +5480,7 @@ [(set (match_operand:SI 0 "register_operand" "=r") (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r")) - (match_operand:SI 2 "register_operand" "r")) + (match_operand:DI 2 "small_int" "i")) (const_int 32))))] "TARGET_HARD_MUL32" "smul\t%1, %2, %%g0\n\trd\t%%y, %0" @@ -5558,12 +5558,12 @@ (define_insn "const_umulsidi3_sp32" [(set (match_operand:DI 0 "register_operand" "=r") (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r")) - (match_operand:SI 2 "uns_small_int" "")))] + (match_operand:DI 2 "uns_small_int" "")))] "TARGET_HARD_MUL32" { return TARGET_SPARCLET - ? "umuld\t%1, %2, %L0" - : "umul\t%1, %2, %L0\n\trd\t%%y, %H0"; + ? "umuld\t%1, %s2, %L0" + : "umul\t%1, %s2, %L0\n\trd\t%%y, %H0"; } [(set (attr "type") (if_then_else (eq_attr "isa" "sparclet") @@ -5575,21 +5575,21 @@ (define_insn "const_umulsidi3_sp64" [(set (match_operand:DI 0 "register_operand" "=r") (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r")) - (match_operand:SI 2 "uns_small_int" "")))] + (match_operand:DI 2 "uns_small_int" "")))] "TARGET_DEPRECATED_V8_INSNS && TARGET_ARCH64" - "umul\t%1, %2, %0" + "umul\t%1, %s2, %0" [(set_attr "type" "imul")]) ;; XXX (define_insn "const_umulsidi3_v8plus" [(set (match_operand:DI 0 "register_operand" "=h,r") (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r,r")) - (match_operand:SI 2 "uns_small_int" ""))) + (match_operand:DI 2 "uns_small_int" ""))) (clobber (match_scratch:SI 3 "=X,h"))] "TARGET_V8PLUS" "@ - umul\t%1, %2, %L0\n\tsrlx\t%L0, 32, %H0 - umul\t%1, %2, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0" + umul\t%1, %s2, %L0\n\tsrlx\t%L0, 32, %H0 + umul\t%1, %s2, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0" [(set_attr "type" "multi") (set_attr "length" "2,3")]) @@ -5642,13 +5642,13 @@ [(set (match_operand:SI 0 "register_operand" "=h,r") (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r,r")) - (match_operand:SI 2 "uns_small_int" "")) + (match_operand:DI 2 "uns_small_int" "")) (match_operand:SI 3 "const_int_operand" "i,i")))) (clobber (match_scratch:SI 4 "=X,h"))] "TARGET_V8PLUS" "@ - umul\t%1, %2, %0\n\tsrlx\t%0, %3, %0 - umul\t%1, %2, %4\n\tsrlx\t%4, %3, %0" + umul\t%1, %s2, %0\n\tsrlx\t%0, %3, %0 + umul\t%1, %s2, %4\n\tsrlx\t%4, %3, %0" [(set_attr "type" "multi") (set_attr "length" "2")]) @@ -5669,10 +5669,10 @@ [(set (match_operand:SI 0 "register_operand" "=r") (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r")) - (match_operand:SI 2 "uns_small_int" "")) + (match_operand:DI 2 "uns_small_int" "")) (const_int 32))))] "TARGET_HARD_MUL32" - "umul\t%1, %2, %%g0\n\trd\t%%y, %0" + "umul\t%1, %s2, %%g0\n\trd\t%%y, %0" [(set_attr "type" "multi") (set_attr "length" "2")])