diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 49fce320d08..c2ebbbcf436 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -13,6 +13,19 @@ * doc/invoke.texi (pdp11 -mfloat32): Remove: (pdp11 -mfloat64): Remove. +2018-10-05 Uros Bizjak + + * config/i386/i386.md (*cmpxf_cc_i387): Remove pattern. + (*cmp_cc_i387): Ditto. + (*cmpu_cc_i387): Ditto. + (*cmp__cc_i387): Ditto. + * config/i386/i386.c (ix86_expand_fp_compare): Remove + "scratch" argument. + : Do not generate pattern with HImode clobber. + Emit x86_sahf_1 pattern. + (ix86_expand_compare): Update call to ix86_expand_fp_compare. + (ix86_expand_carry_flag_compare): Ditto. + 2018-10-05 Uros Bizjak * config/i386/i386.md (*cmpxf_i387): Change operand 2 predicate diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index fafdcd4115e..0cf4152acb2 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -22258,45 +22258,38 @@ ix86_fp_compare_code_to_integer (enum rtx_code code) /* Generate insn patterns to do a floating point compare of OPERANDS. */ static rtx -ix86_expand_fp_compare (enum rtx_code code, rtx op0, rtx op1, rtx scratch) +ix86_expand_fp_compare (enum rtx_code code, rtx op0, rtx op1) { bool unordered_compare = ix86_unordered_fp_compare (code); - machine_mode intcmp_mode; - rtx tmp, tmp2; + machine_mode cmp_mode; + rtx tmp, scratch; code = ix86_prepare_fp_compare_args (code, &op0, &op1); + tmp = gen_rtx_COMPARE (CCFPmode, op0, op1); + if (unordered_compare) + tmp = gen_rtx_UNSPEC (CCFPmode, gen_rtvec (1, tmp), UNSPEC_NOTRAP); + /* Do fcomi/sahf based test when profitable. */ switch (ix86_fp_comparison_strategy (code)) { case IX86_FPCMP_COMI: - intcmp_mode = CCFPmode; - tmp = gen_rtx_COMPARE (CCFPmode, op0, op1); - if (unordered_compare) - tmp = gen_rtx_UNSPEC (CCFPmode, gen_rtvec (1, tmp), UNSPEC_NOTRAP); + cmp_mode = CCFPmode; emit_insn (gen_rtx_SET (gen_rtx_REG (CCFPmode, FLAGS_REG), tmp)); break; case IX86_FPCMP_SAHF: - intcmp_mode = CCFPmode; - tmp = gen_rtx_COMPARE (CCFPmode, op0, op1); - if (unordered_compare) - tmp = gen_rtx_UNSPEC (CCFPmode, gen_rtvec (1, tmp), UNSPEC_NOTRAP); - tmp = gen_rtx_SET (gen_rtx_REG (CCFPmode, FLAGS_REG), tmp); - if (!scratch) - scratch = gen_reg_rtx (HImode); - tmp2 = gen_rtx_CLOBBER (VOIDmode, scratch); - emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, tmp, tmp2))); + cmp_mode = CCFPmode; + tmp = gen_rtx_UNSPEC (HImode, gen_rtvec (1, tmp), UNSPEC_FNSTSW); + scratch = gen_reg_rtx (HImode); + emit_insn (gen_rtx_SET (scratch, tmp)); + emit_insn (gen_x86_sahf_1 (scratch)); break; case IX86_FPCMP_ARITH: - /* Sadness wrt reg-stack pops killing fpsr -- gotta get fnstsw first. */ - tmp = gen_rtx_COMPARE (CCFPmode, op0, op1); - if (unordered_compare) - tmp = gen_rtx_UNSPEC (CCFPmode, gen_rtvec (1, tmp), UNSPEC_NOTRAP); + cmp_mode = CCNOmode; tmp = gen_rtx_UNSPEC (HImode, gen_rtvec (1, tmp), UNSPEC_FNSTSW); - if (!scratch) - scratch = gen_reg_rtx (HImode); + scratch = gen_reg_rtx (HImode); emit_insn (gen_rtx_SET (scratch, tmp)); /* In the unordered case, we have to check C2 for NaN's, which @@ -22304,7 +22297,6 @@ ix86_expand_fp_compare (enum rtx_code code, rtx op0, rtx op1, rtx scratch) So do some bit twiddling on the value we've got in AH to come up with an appropriate set of condition codes. */ - intcmp_mode = CCNOmode; switch (code) { case GT: @@ -22319,7 +22311,7 @@ ix86_expand_fp_compare (enum rtx_code code, rtx op0, rtx op1, rtx scratch) emit_insn (gen_andqi_ext_1 (scratch, scratch, GEN_INT (0x45))); emit_insn (gen_addqi_ext_1 (scratch, scratch, constm1_rtx)); emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x44))); - intcmp_mode = CCmode; + cmp_mode = CCmode; code = GEU; } break; @@ -22329,7 +22321,7 @@ ix86_expand_fp_compare (enum rtx_code code, rtx op0, rtx op1, rtx scratch) { emit_insn (gen_andqi_ext_1 (scratch, scratch, GEN_INT (0x45))); emit_insn (gen_cmpqi_ext_3 (scratch, const1_rtx)); - intcmp_mode = CCmode; + cmp_mode = CCmode; code = EQ; } else @@ -22359,7 +22351,7 @@ ix86_expand_fp_compare (enum rtx_code code, rtx op0, rtx op1, rtx scratch) emit_insn (gen_andqi_ext_1 (scratch, scratch, GEN_INT (0x45))); emit_insn (gen_addqi_ext_1 (scratch, scratch, constm1_rtx)); emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x40))); - intcmp_mode = CCmode; + cmp_mode = CCmode; code = LTU; } else @@ -22374,7 +22366,7 @@ ix86_expand_fp_compare (enum rtx_code code, rtx op0, rtx op1, rtx scratch) { emit_insn (gen_andqi_ext_1 (scratch, scratch, GEN_INT (0x45))); emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x40))); - intcmp_mode = CCmode; + cmp_mode = CCmode; code = EQ; } else @@ -22420,7 +22412,7 @@ ix86_expand_fp_compare (enum rtx_code code, rtx op0, rtx op1, rtx scratch) /* Return the test that should be put into the flags user, i.e. the bcc, scc, or cmov instruction. */ return gen_rtx_fmt_ee (code, VOIDmode, - gen_rtx_REG (intcmp_mode, FLAGS_REG), + gen_rtx_REG (cmp_mode, FLAGS_REG), const0_rtx); } @@ -22435,7 +22427,7 @@ ix86_expand_compare (enum rtx_code code, rtx op0, rtx op1) else if (SCALAR_FLOAT_MODE_P (GET_MODE (op0))) { gcc_assert (!DECIMAL_FLOAT_MODE_P (GET_MODE (op0))); - ret = ix86_expand_fp_compare (code, op0, op1, NULL_RTX); + ret = ix86_expand_fp_compare (code, op0, op1); } else ret = ix86_expand_int_compare (code, op0, op1); @@ -22735,7 +22727,7 @@ ix86_expand_carry_flag_compare (enum rtx_code code, rtx op0, rtx op1, rtx *pop) we decide to expand comparison using arithmetic that is not too common scenario. */ start_sequence (); - compare_op = ix86_expand_fp_compare (code, op0, op1, NULL_RTX); + compare_op = ix86_expand_fp_compare (code, op0, op1); compare_seq = get_insns (); end_sequence (); diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index d7afb6a0bda..7c440a4ed50 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -1480,26 +1480,6 @@ (set_attr "unit" "i387") (set_attr "mode" "XF")]) -(define_insn_and_split "*cmpxf_cc_i387" - [(set (reg:CCFP FLAGS_REG) - (compare:CCFP - (match_operand:XF 1 "register_operand" "f") - (match_operand:XF 2 "reg_or_0_operand" "fC"))) - (clobber (match_operand:HI 0 "register_operand" "=a"))] - "TARGET_80387 && TARGET_SAHF && !TARGET_CMOVE" - "#" - "&& reload_completed" - [(set (match_dup 0) - (unspec:HI - [(compare:CCFP (match_dup 1)(match_dup 2))] - UNSPEC_FNSTSW)) - (set (reg:CC FLAGS_REG) - (unspec:CC [(match_dup 0)] UNSPEC_SAHF))] - "" - [(set_attr "type" "multi") - (set_attr "unit" "i387") - (set_attr "mode" "XF")]) - (define_insn "*cmp_i387" [(set (match_operand:HI 0 "register_operand" "=a") (unspec:HI @@ -1513,65 +1493,6 @@ (set_attr "unit" "i387") (set_attr "mode" "")]) -(define_insn_and_split "*cmp_cc_i387" - [(set (reg:CCFP FLAGS_REG) - (compare:CCFP - (match_operand:MODEF 1 "register_operand" "f") - (match_operand:MODEF 2 "nonimm_or_0_operand" "fmC"))) - (clobber (match_operand:HI 0 "register_operand" "=a"))] - "TARGET_80387 && TARGET_SAHF && !TARGET_CMOVE" - "#" - "&& reload_completed" - [(set (match_dup 0) - (unspec:HI - [(compare:CCFP (match_dup 1)(match_dup 2))] - UNSPEC_FNSTSW)) - (set (reg:CC FLAGS_REG) - (unspec:CC [(match_dup 0)] UNSPEC_SAHF))] - "" - [(set_attr "type" "multi") - (set_attr "unit" "i387") - (set_attr "mode" "")]) - -(define_insn "*cmpu_i387" - [(set (match_operand:HI 0 "register_operand" "=a") - (unspec:HI - [(unspec:CCFP - [(compare:CCFP - (match_operand:X87MODEF 1 "register_operand" "f") - (match_operand:X87MODEF 2 "register_operand" "f"))] - UNSPEC_NOTRAP)] - UNSPEC_FNSTSW))] - "TARGET_80387" - "* return output_fp_compare (insn, operands, false, true);" - [(set_attr "type" "multi") - (set_attr "unit" "i387") - (set_attr "mode" "")]) - -(define_insn_and_split "*cmpu_cc_i387" - [(set (reg:CCFP FLAGS_REG) - (unspec:CCFP - [(compare:CCFP - (match_operand:X87MODEF 1 "register_operand" "f") - (match_operand:X87MODEF 2 "register_operand" "f"))] - UNSPEC_NOTRAP)) - (clobber (match_operand:HI 0 "register_operand" "=a"))] - "TARGET_80387 && TARGET_SAHF && !TARGET_CMOVE" - "#" - "&& reload_completed" - [(set (match_dup 0) - (unspec:HI - [(unspec:CCFP - [(compare:CCFP (match_dup 1)(match_dup 2))] - UNSPEC_NOTRAP)] - UNSPEC_FNSTSW)) - (set (reg:CC FLAGS_REG) - (unspec:CC [(match_dup 0)] UNSPEC_SAHF))] - "" - [(set_attr "type" "multi") - (set_attr "unit" "i387") - (set_attr "mode" "")]) - (define_insn "*cmp__i387" [(set (match_operand:HI 0 "register_operand" "=a") (unspec:HI @@ -1589,31 +1510,20 @@ (set_attr "fp_int_src" "true") (set_attr "mode" "")]) -(define_insn_and_split "*cmp__cc_i387" - [(set (reg:CCFP FLAGS_REG) - (compare:CCFP - (match_operand:X87MODEF 1 "register_operand" "f") - (float:X87MODEF - (match_operand:SWI24 2 "nonimmediate_operand" "m")))) - (clobber (match_operand:HI 0 "register_operand" "=a"))] - "TARGET_80387 && TARGET_SAHF && !TARGET_CMOVE - && (TARGET_USE_MODE_FIOP - || optimize_function_for_size_p (cfun))" - "#" - "&& reload_completed" - [(set (match_dup 0) +(define_insn "*cmpu_i387" + [(set (match_operand:HI 0 "register_operand" "=a") (unspec:HI - [(compare:CCFP - (match_dup 1) - (float:X87MODEF (match_dup 2)))] - UNSPEC_FNSTSW)) - (set (reg:CC FLAGS_REG) - (unspec:CC [(match_dup 0)] UNSPEC_SAHF))] - "" + [(unspec:CCFP + [(compare:CCFP + (match_operand:X87MODEF 1 "register_operand" "f") + (match_operand:X87MODEF 2 "register_operand" "f"))] + UNSPEC_NOTRAP)] + UNSPEC_FNSTSW))] + "TARGET_80387" + "* return output_fp_compare (insn, operands, false, true);" [(set_attr "type" "multi") (set_attr "unit" "i387") - (set_attr "fp_int_src" "true") - (set_attr "mode" "")]) + (set_attr "mode" "")]) ;; FP compares, step 2: ;; Get ax into flags, general case.