i386: Implement widen_smul_*_v4si for plain sse2
If we don't implement this pattern, the vectorizer is happy to
unpack the v4si and use the full mulv2di3. This results in
more element shuffling than is required.
* config/i386/i386.c (bdesc_args): Update. Change
IX86_BUILTIN_VEC_WIDEN_SMUL_ODD_V4SI to OPTION_MASK_ISA_SSE2.
(IX86_BUILTIN_VEC_WIDEN_SMUL_EVEN_V4SI): New.
(ix86_builtin_mul_widen_even): Use it.
(ix86_builtin_mul_widen_odd): Relax SMUL_ODD from sse4 to sse2.
(ix86_expand_mul_widen_evenodd): Handle signed for sse2.
* config/i386/sse.md (vec_widen_<s>mult_hi_<V124_AVX2>): Allow
for all SSE2.
(vec_widen_<s>mult_lo_<V124_AVX2>): Likewise.
(vec_widen_<s>mult_odd_<VI4_AVX2>): Likewise. Relax from V124_AVX2.
(vec_widen_smult_even_v4si): New.
From-SVN: r189006
This commit is contained in:
Richard Henderson
Richard Henderson
parent
298301d9e7
commit
87b7851620
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@ -1,3 +1,17 @@
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2012-06-26 Richard Henderson <rth@redhat.com>
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* config/i386/i386.c (bdesc_args): Update. Change
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IX86_BUILTIN_VEC_WIDEN_SMUL_ODD_V4SI to OPTION_MASK_ISA_SSE2.
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(IX86_BUILTIN_VEC_WIDEN_SMUL_EVEN_V4SI): New.
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(ix86_builtin_mul_widen_even): Use it.
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(ix86_builtin_mul_widen_odd): Relax SMUL_ODD from sse4 to sse2.
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(ix86_expand_mul_widen_evenodd): Handle signed for sse2.
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* config/i386/sse.md (vec_widen_<s>mult_hi_<V124_AVX2>): Allow
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for all SSE2.
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(vec_widen_<s>mult_lo_<V124_AVX2>): Likewise.
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(vec_widen_<s>mult_odd_<VI4_AVX2>): Likewise. Relax from V124_AVX2.
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(vec_widen_smult_even_v4si): New.
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2012-06-26 Richard Henderson <rth@redhat.com>
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* config/i386/sse.md (mul<VI8_AVX2>3): Change from insn_and_split
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@ -25758,6 +25758,7 @@ enum ix86_builtins
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IX86_BUILTIN_VEC_WIDEN_SMUL_ODD_V8SI,
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IX86_BUILTIN_VEC_WIDEN_UMUL_ODD_V4SI,
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IX86_BUILTIN_VEC_WIDEN_UMUL_ODD_V8SI,
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IX86_BUILTIN_VEC_WIDEN_SMUL_EVEN_V4SI,
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IX86_BUILTIN_VEC_WIDEN_UMUL_EVEN_V4SI,
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IX86_BUILTIN_VEC_WIDEN_UMUL_EVEN_V8SI,
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@ -26620,7 +26621,9 @@ static const struct builtin_description bdesc_args[] =
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{ OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulv1siv1di3, "__builtin_ia32_pmuludq", IX86_BUILTIN_PMULUDQ, UNKNOWN, (int) V1DI_FTYPE_V2SI_V2SI },
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{ OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulv2siv2di3, "__builtin_ia32_pmuludq128", IX86_BUILTIN_PMULUDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
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{ OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulv2siv2di3, "__builtin_vw_umul_even_v4si", IX86_BUILTIN_VEC_WIDEN_UMUL_EVEN_V4SI, UNKNOWN, (int) V2UDI_FTYPE_V4USI_V4USI },
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{ OPTION_MASK_ISA_SSE2, CODE_FOR_vec_widen_smult_even_v4si, "__builtin_ia32_vw_smul_even_v4si", IX86_BUILTIN_VEC_WIDEN_SMUL_EVEN_V4SI, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
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{ OPTION_MASK_ISA_SSE2, CODE_FOR_vec_widen_umult_odd_v4si, "__builtin_ia32_vw_umul_odd_v4si", IX86_BUILTIN_VEC_WIDEN_UMUL_ODD_V4SI, UNKNOWN, (int) V2UDI_FTYPE_V4USI_V4USI },
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{ OPTION_MASK_ISA_SSE2, CODE_FOR_vec_widen_smult_odd_v4si, "__builtin_ia32_vw_smul_odd_v4si", IX86_BUILTIN_VEC_WIDEN_SMUL_ODD_V4SI, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
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{ OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmaddwd, "__builtin_ia32_pmaddwd128", IX86_BUILTIN_PMADDWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI_V8HI },
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@ -26747,7 +26750,6 @@ static const struct builtin_description bdesc_args[] =
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{ OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv4si3, "__builtin_ia32_pminud128", IX86_BUILTIN_PMINUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
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{ OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv8hi3, "__builtin_ia32_pminuw128", IX86_BUILTIN_PMINUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
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{ OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mulv2siv2di3, "__builtin_ia32_pmuldq128", IX86_BUILTIN_PMULDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
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{ OPTION_MASK_ISA_SSE4_1, CODE_FOR_vec_widen_smult_odd_v4si, "__builtin_ia32_vw_smul_odd_v4si", IX86_BUILTIN_VEC_WIDEN_SMUL_ODD_V4SI, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
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{ OPTION_MASK_ISA_SSE4_1, CODE_FOR_mulv4si3, "__builtin_ia32_pmulld128", IX86_BUILTIN_PMULLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
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/* SSE4.1 */
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@ -31067,18 +31069,10 @@ ix86_builtin_mul_widen_even (tree type)
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switch (TYPE_MODE (type))
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{
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case V4SImode:
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if (uns_p)
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{
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if (!TARGET_SSE2)
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return NULL;
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code = IX86_BUILTIN_VEC_WIDEN_UMUL_EVEN_V4SI;
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}
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else
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{
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if (!TARGET_SSE4_1)
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return NULL;
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code = IX86_BUILTIN_PMULDQ128;
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}
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if (!TARGET_SSE2)
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return NULL;
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code = (uns_p ? IX86_BUILTIN_VEC_WIDEN_UMUL_EVEN_V4SI
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: IX86_BUILTIN_VEC_WIDEN_SMUL_EVEN_V4SI);
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break;
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case V8SImode:
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@ -31103,18 +31097,10 @@ ix86_builtin_mul_widen_odd (tree type)
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switch (TYPE_MODE (type))
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{
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case V4SImode:
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if (uns_p)
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{
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if (!TARGET_SSE2)
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return NULL;
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code = IX86_BUILTIN_VEC_WIDEN_UMUL_ODD_V4SI;
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}
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else
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{
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if (!TARGET_SSE4_1)
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return NULL;
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code = IX86_BUILTIN_VEC_WIDEN_SMUL_ODD_V4SI;
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}
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if (!TARGET_SSE2)
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return NULL;
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code = (uns_p ? IX86_BUILTIN_VEC_WIDEN_UMUL_ODD_V4SI
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: IX86_BUILTIN_VEC_WIDEN_SMUL_ODD_V4SI);
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break;
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case V8SImode:
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@ -38774,12 +38760,12 @@ ix86_expand_mul_widen_evenodd (rtx dest, rtx op1, rtx op2,
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emit_insn (gen_xop_pmacsdqh (dest, op1, op2, x));
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return;
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}
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x = GEN_INT (GET_MODE_UNIT_BITSIZE (mode));
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op1 = expand_binop (wmode, lshr_optab, gen_lowpart (wmode, op1),
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GEN_INT (GET_MODE_UNIT_BITSIZE (mode)), NULL,
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1, OPTAB_DIRECT);
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x, NULL, 1, OPTAB_DIRECT);
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op2 = expand_binop (wmode, lshr_optab, gen_lowpart (wmode, op2),
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GEN_INT (GET_MODE_UNIT_BITSIZE (mode)), NULL,
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1, OPTAB_DIRECT);
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x, NULL, 1, OPTAB_DIRECT);
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op1 = gen_lowpart (mode, op1);
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op2 = gen_lowpart (mode, op2);
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}
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@ -38801,7 +38787,38 @@ ix86_expand_mul_widen_evenodd (rtx dest, rtx op1, rtx op2,
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x = gen_xop_pmacsdql (dest, op1, op2, x);
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}
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else
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gcc_unreachable ();
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{
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rtx s1, s2, t0, t1, t2;
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/* The easiest way to implement this without PMULDQ is to go through
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the motions as if we are performing a full 64-bit multiply. With
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the exception that we need to do less shuffling of the elements. */
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/* Compute the sign-extension, aka highparts, of the two operands. */
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s1 = ix86_expand_sse_cmp (gen_reg_rtx (mode), GT, CONST0_RTX (mode),
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op1, pc_rtx, pc_rtx);
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s2 = ix86_expand_sse_cmp (gen_reg_rtx (mode), GT, CONST0_RTX (mode),
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op2, pc_rtx, pc_rtx);
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/* Multiply LO(A) * HI(B), and vice-versa. */
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t1 = gen_reg_rtx (wmode);
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t2 = gen_reg_rtx (wmode);
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emit_insn (gen_sse2_umulv2siv2di3 (t1, s1, op2));
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emit_insn (gen_sse2_umulv2siv2di3 (t2, s2, op1));
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/* Multiply LO(A) * LO(B). */
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t0 = gen_reg_rtx (wmode);
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emit_insn (gen_sse2_umulv2siv2di3 (t0, op1, op2));
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/* Combine and shift the highparts into place. */
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t1 = expand_binop (wmode, add_optab, t1, t2, t1, 1, OPTAB_DIRECT);
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t1 = expand_binop (wmode, ashl_optab, t1, GEN_INT (32), t1,
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1, OPTAB_DIRECT);
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/* Combine high and low parts. */
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force_expand_binop (wmode, add_optab, t0, t1, dest, 1, OPTAB_DIRECT);
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return;
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}
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emit_insn (x);
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}
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@ -5607,9 +5607,7 @@
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(any_extend:<sseunpackmode>
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(match_operand:VI124_AVX2 1 "register_operand"))
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(match_operand:VI124_AVX2 2 "register_operand")]
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; Note that SSE2 does not have signed SI multiply
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"TARGET_XOP || TARGET_SSE4_1
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|| (TARGET_SSE2 && (<u_bool> || <MODE>mode != V4SImode))"
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"TARGET_SSE2"
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{
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ix86_expand_mul_widen_hilo (operands[0], operands[1], operands[2],
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<u_bool>, true);
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@ -5621,23 +5619,32 @@
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(any_extend:<sseunpackmode>
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(match_operand:VI124_AVX2 1 "register_operand"))
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(match_operand:VI124_AVX2 2 "register_operand")]
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; Note that SSE2 does not have signed SI multiply
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"TARGET_XOP || TARGET_SSE4_1
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|| (TARGET_SSE2 && (<u_bool> || <MODE>mode != V4SImode))"
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"TARGET_SSE2"
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{
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ix86_expand_mul_widen_hilo (operands[0], operands[1], operands[2],
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<u_bool>, false);
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DONE;
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})
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;; Most widen_<s>mult_even_<mode> can be handled directly from other
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;; named patterns, but signed V4SI needs special help for plain SSE2.
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(define_expand "vec_widen_smult_even_v4si"
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[(match_operand:V2DI 0 "register_operand")
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(match_operand:V4SI 1 "register_operand")
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(match_operand:V4SI 2 "register_operand")]
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"TARGET_SSE2"
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{
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ix86_expand_mul_widen_evenodd (operands[0], operands[1], operands[2],
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false, false);
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DONE;
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})
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(define_expand "vec_widen_<s>mult_odd_<mode>"
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[(match_operand:<sseunpackmode> 0 "register_operand")
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(any_extend:<sseunpackmode>
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(match_operand:VI124_AVX2 1 "register_operand"))
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(match_operand:VI124_AVX2 2 "register_operand")]
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; Note that SSE2 does not have signed SI multiply
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"TARGET_AVX || TARGET_XOP || TARGET_SSE4_1
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|| (TARGET_SSE2 && (<u_bool> || <MODE>mode != V4SImode))"
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(match_operand:VI4_AVX2 1 "register_operand"))
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(match_operand:VI4_AVX2 2 "register_operand")]
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"TARGET_SSE2"
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{
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ix86_expand_mul_widen_evenodd (operands[0], operands[1], operands[2],
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<u_bool>, true);
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