i960.md (*): Use TFmode, not XFmode.
* config/i960/i960.md (*): Use TFmode, not XFmode. * config/i960/i960.c (*): Likewise. (i960_arg_size_and_align): Remove XFmode alignment hack. (i960_round_align): Merge code from ROUND_TYPE_ALIGN. * config/i960/i960.h (LONG_DOUBLE_TYPE_SIZE): Use 128, not 96. (MAX_LONG_DOUBLE_TYPE_SIZE): Likewise. (DATA_ALIGNMENT, ROUND_TYPE_SIZE): Remove. From-SVN: r57889
This commit is contained in:
parent
5ef38d2ac1
commit
87cb2a87f8
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@ -1,3 +1,13 @@
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2002-10-07 Richard Henderson <rth@redhat.com>
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* config/i960/i960.md (*): Use TFmode, not XFmode.
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* config/i960/i960.c (*): Likewise.
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(i960_arg_size_and_align): Remove XFmode alignment hack.
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(i960_round_align): Merge code from ROUND_TYPE_ALIGN.
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* config/i960/i960.h (LONG_DOUBLE_TYPE_SIZE): Use 128, not 96.
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(MAX_LONG_DOUBLE_TYPE_SIZE): Likewise.
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(DATA_ALIGNMENT, ROUND_TYPE_SIZE): Remove.
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2002-10-07 Richard Henderson <rth@redhat.com>
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* config/fp-bit.c (EXTENDED_FLOAT_STUBS): Flush out all XF/TFmode
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@ -152,8 +152,8 @@ i960_initialize ()
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i960_last_maxbitalignment = 8;
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}
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/* Tell the compiler which flavor of XFmode we're using. */
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real_format_for_mode[XFmode - QFmode] = &ieee_extended_intel_96_format;
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/* Tell the compiler which flavor of TFmode we're using. */
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real_format_for_mode[TFmode - QFmode] = &ieee_extended_intel_128_format;
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}
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/* Return true if OP can be used as the source of an fp move insn. */
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@ -803,13 +803,13 @@ i960_output_ldconst (dst, src)
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output_asm_insn ("ldconst %1,%0", operands);
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return "";
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}
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else if (mode == XFmode)
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else if (mode == TFmode)
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{
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REAL_VALUE_TYPE d;
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long value_long[3];
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int i;
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if (fp_literal_zero (src, XFmode))
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if (fp_literal_zero (src, TFmode))
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return "movt 0,%0";
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REAL_VALUE_FROM_CONST_DOUBLE (d, src);
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@ -2208,7 +2208,7 @@ hard_regno_mode_ok (regno, mode)
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case DImode: case DFmode:
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return (regno & 1) == 0;
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case TImode: case XFmode:
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case TImode: case TFmode:
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return (regno & 3) == 0;
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default:
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@ -2219,7 +2219,7 @@ hard_regno_mode_ok (regno, mode)
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{
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switch (mode)
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{
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case SFmode: case DFmode: case XFmode:
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case SFmode: case DFmode: case TFmode:
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case SCmode: case DCmode:
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return 1;
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@ -2397,14 +2397,7 @@ i960_arg_size_and_align (mode, type, size_out, align_out)
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size = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
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if (type == 0)
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{
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/* ??? This is a hack to properly correct the alignment of XFmode
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values without affecting anything else. */
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if (size == 3)
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align = 4;
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else
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align = size;
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}
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align = size;
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else if (TYPE_ALIGN (type) >= BITS_PER_WORD)
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align = TYPE_ALIGN (type) / BITS_PER_WORD;
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else
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@ -2503,11 +2496,18 @@ i960_object_bytes_bitalign (n)
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MIN (pragma align, structure size alignment)). */
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int
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i960_round_align (align, tsize)
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i960_round_align (align, type)
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int align;
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tree tsize;
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tree type;
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{
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int new_align;
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tree tsize;
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if (TARGET_OLD_ALIGN || TYPE_PACKED (type))
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return align;
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if (TREE_CODE (type) != RECORD_TYPE)
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return align;
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tsize = TYPE_SIZE (type);
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if (! tsize || TREE_CODE (tsize) != INTEGER_CST)
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return align;
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@ -362,17 +362,16 @@ extern int target_flags;
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/* Width of a word, in units (bytes). */
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#define UNITS_PER_WORD 4
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/* Width in bits of a long double. Define to 96, and let
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ROUND_TYPE_ALIGN adjust the alignment for speed. */
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#define LONG_DOUBLE_TYPE_SIZE (TARGET_LONG_DOUBLE_64 ? 64 : 96)
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#define MAX_LONG_DOUBLE_TYPE_SIZE 96
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/* Width in bits of a long double. */
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#define LONG_DOUBLE_TYPE_SIZE (TARGET_LONG_DOUBLE_64 ? 64 : 128)
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#define MAX_LONG_DOUBLE_TYPE_SIZE 128
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/* Define this to set long double type size to use in libgcc2.c, which can
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not depend on target_flags. */
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#if defined(__LONG_DOUBLE_64__)
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#define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
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#else
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#define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 96
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#define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
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#endif
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/* Allocation boundary (in *bits*) for storing pointers in memory. */
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@ -417,33 +416,14 @@ extern int target_flags;
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? i960_object_bytes_bitalign (int_size_in_bytes (TREE_TYPE (EXP))) \
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: (ALIGN))
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/* Make XFmode floating point quantities be 128 bit aligned. */
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#define DATA_ALIGNMENT(TYPE, ALIGN) \
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(TREE_CODE (TYPE) == ARRAY_TYPE \
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&& TYPE_MODE (TREE_TYPE (TYPE)) == XFmode \
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&& (ALIGN) < 128 ? 128 : (ALIGN))
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/* Macros to determine size of aggregates (structures and unions
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in C). Normally, these may be defined to simply return the maximum
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alignment and simple rounded-up size, but on some machines (like
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the i960), the total size of a structure is based on a non-trivial
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rounding method. */
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#define ROUND_TYPE_ALIGN(TYPE, COMPUTED, SPECIFIED) \
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((TREE_CODE (TYPE) == REAL_TYPE && TYPE_MODE (TYPE) == XFmode) \
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? 128 /* Put 80 bit floating point elements on 128 bit boundaries. */ \
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: ((!TARGET_OLD_ALIGN && !TYPE_PACKED (TYPE) \
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&& TREE_CODE (TYPE) == RECORD_TYPE) \
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? i960_round_align (MAX ((COMPUTED), (SPECIFIED)), TYPE_SIZE (TYPE)) \
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: MAX ((COMPUTED), (SPECIFIED))))
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#define ROUND_TYPE_SIZE(TYPE, COMPUTED, SPECIFIED) \
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((TREE_CODE (TYPE) == REAL_TYPE && TYPE_MODE (TYPE) == XFmode) \
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? bitsize_int (128) : round_up (COMPUTED, SPECIFIED))
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#define ROUND_TYPE_SIZE_UNIT(TYPE, COMPUTED, SPECIFIED) \
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((TREE_CODE (TYPE) == REAL_TYPE && TYPE_MODE (TYPE) == XFmode) \
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? size_int (16) : round_up (COMPUTED, SPECIFIED))
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#define ROUND_TYPE_ALIGN(TYPE, COMPUTED, SPECIFIED) \
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i960_round_align (MAX ((COMPUTED), (SPECIFIED)), TYPE)
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/* Standard register usage. */
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@ -526,7 +506,7 @@ extern int target_flags;
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/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
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On 80960, the cpu registers can hold any mode but the float registers
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can only hold SFmode, DFmode, or XFmode. */
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can only hold SFmode, DFmode, or TFmode. */
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#define HARD_REGNO_MODE_OK(REGNO, MODE) hard_regno_mode_ok ((REGNO), (MODE))
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/* Value is 1 if it is a good idea to tie two pseudo registers
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@ -2061,10 +2061,10 @@
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;; Tetra (16 byte) float support.
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(define_expand "cmpxf"
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(define_expand "cmptf"
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[(set (reg:CC 36)
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(compare:CC (match_operand:XF 0 "register_operand" "")
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(match_operand:XF 1 "nonmemory_operand" "")))]
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(compare:CC (match_operand:TF 0 "register_operand" "")
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(match_operand:TF 1 "nonmemory_operand" "")))]
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"TARGET_NUMERICS"
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"
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{
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@ -2075,27 +2075,27 @@
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(define_insn ""
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[(set (reg:CC 36)
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(compare:CC (match_operand:XF 0 "register_operand" "f")
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(match_operand:XF 1 "nonmemory_operand" "fGH")))]
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(compare:CC (match_operand:TF 0 "register_operand" "f")
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(match_operand:TF 1 "nonmemory_operand" "fGH")))]
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"TARGET_NUMERICS"
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"cmpr %0,%1"
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[(set_attr "type" "fpcc")])
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(define_expand "movxf"
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[(set (match_operand:XF 0 "general_operand" "")
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(match_operand:XF 1 "fpmove_src_operand" ""))]
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(define_expand "movtf"
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[(set (match_operand:TF 0 "general_operand" "")
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(match_operand:TF 1 "fpmove_src_operand" ""))]
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""
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"
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{
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if (emit_move_sequence (operands, XFmode))
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if (emit_move_sequence (operands, TFmode))
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DONE;
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}")
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(define_insn ""
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[(set (match_operand:XF 0 "general_operand" "=r,f,d,d,m")
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(match_operand:XF 1 "fpmove_src_operand" "r,GH,F,m,d"))]
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"register_operand (operands[0], XFmode)
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|| register_operand (operands[1], XFmode)"
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[(set (match_operand:TF 0 "general_operand" "=r,f,d,d,m")
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(match_operand:TF 1 "fpmove_src_operand" "r,GH,F,m,d"))]
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"register_operand (operands[0], TFmode)
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|| register_operand (operands[1], TFmode)"
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"*
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{
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switch (which_alternative)
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@ -2119,9 +2119,9 @@
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}"
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[(set_attr "type" "move,move,load,fpload,fpstore")])
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(define_insn "extendsfxf2"
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[(set (match_operand:XF 0 "register_operand" "=f,d")
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(float_extend:XF
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(define_insn "extendsftf2"
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[(set (match_operand:TF 0 "register_operand" "=f,d")
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(float_extend:TF
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(match_operand:SF 1 "register_operand" "d,f")))]
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"TARGET_NUMERICS"
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"@
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movre %1,%0"
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[(set_attr "type" "fpmove")])
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(define_insn "extenddfxf2"
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[(set (match_operand:XF 0 "register_operand" "=f,d")
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(float_extend:XF
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(define_insn "extenddftf2"
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[(set (match_operand:TF 0 "register_operand" "=f,d")
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(float_extend:TF
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(match_operand:DF 1 "register_operand" "d,f")))]
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"TARGET_NUMERICS"
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"@
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@ -2139,85 +2139,85 @@
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movre %1,%0"
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[(set_attr "type" "fpmove")])
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(define_insn "truncxfdf2"
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(define_insn "trunctfdf2"
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[(set (match_operand:DF 0 "register_operand" "=d")
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(float_truncate:DF
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(match_operand:XF 1 "register_operand" "f")))]
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(match_operand:TF 1 "register_operand" "f")))]
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"TARGET_NUMERICS"
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"movrl %1,%0"
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[(set_attr "type" "fpmove")])
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(define_insn "truncxfsf2"
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(define_insn "trunctfsf2"
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[(set (match_operand:SF 0 "register_operand" "=d")
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(float_truncate:SF
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(match_operand:XF 1 "register_operand" "f")))]
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(match_operand:TF 1 "register_operand" "f")))]
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"TARGET_NUMERICS"
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"movr %1,%0"
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[(set_attr "type" "fpmove")])
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(define_insn "floatsixf2"
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[(set (match_operand:XF 0 "register_operand" "=f")
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(float:XF (match_operand:SI 1 "register_operand" "d")))]
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(define_insn "floatsitf2"
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[(set (match_operand:TF 0 "register_operand" "=f")
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(float:TF (match_operand:SI 1 "register_operand" "d")))]
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"TARGET_NUMERICS"
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"cvtir %1,%0"
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[(set_attr "type" "fpcvt")])
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(define_insn "fix_truncxfsi2"
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(define_insn "fix_trunctfsi2"
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[(set (match_operand:SI 0 "register_operand" "=d")
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(fix:SI (fix:XF (match_operand:XF 1 "register_operand" "f"))))]
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(fix:SI (fix:TF (match_operand:TF 1 "register_operand" "f"))))]
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"TARGET_NUMERICS"
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"cvtzri %1,%0"
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[(set_attr "type" "fpcvt")])
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(define_insn "fixuns_truncxfsi2"
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(define_insn "fixuns_trunctfsi2"
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[(set (match_operand:SI 0 "register_operand" "=d")
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(unsigned_fix:SI (fix:XF (match_operand:XF 1 "register_operand" "f"))))]
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(unsigned_fix:SI (fix:TF (match_operand:TF 1 "register_operand" "f"))))]
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"TARGET_NUMERICS"
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"cvtzri %1,%0"
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[(set_attr "type" "fpcvt")])
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(define_insn "addxf3"
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[(set (match_operand:XF 0 "register_operand" "=f")
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(plus:XF (match_operand:XF 1 "nonmemory_operand" "%fGH")
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(match_operand:XF 2 "nonmemory_operand" "fGH")))]
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(define_insn "addtf3"
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[(set (match_operand:TF 0 "register_operand" "=f")
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(plus:TF (match_operand:TF 1 "nonmemory_operand" "%fGH")
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(match_operand:TF 2 "nonmemory_operand" "fGH")))]
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"TARGET_NUMERICS"
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"addr %1,%2,%0"
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[(set_attr "type" "fpadd")])
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(define_insn "subxf3"
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[(set (match_operand:XF 0 "register_operand" "=f")
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(minus:XF (match_operand:XF 1 "nonmemory_operand" "fGH")
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(match_operand:XF 2 "nonmemory_operand" "fGH")))]
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(define_insn "subtf3"
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[(set (match_operand:TF 0 "register_operand" "=f")
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(minus:TF (match_operand:TF 1 "nonmemory_operand" "fGH")
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(match_operand:TF 2 "nonmemory_operand" "fGH")))]
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"TARGET_NUMERICS"
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"subr %2,%1,%0"
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[(set_attr "type" "fpadd")])
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(define_insn "mulxf3"
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[(set (match_operand:XF 0 "register_operand" "=f")
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(mult:XF (match_operand:XF 1 "nonmemory_operand" "%fGH")
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(match_operand:XF 2 "nonmemory_operand" "fGH")))]
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(define_insn "multf3"
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[(set (match_operand:TF 0 "register_operand" "=f")
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(mult:TF (match_operand:TF 1 "nonmemory_operand" "%fGH")
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(match_operand:TF 2 "nonmemory_operand" "fGH")))]
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"TARGET_NUMERICS"
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"mulr %1,%2,%0"
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[(set_attr "type" "fpmul")])
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(define_insn "divxf3"
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[(set (match_operand:XF 0 "register_operand" "=f")
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(div:XF (match_operand:XF 1 "nonmemory_operand" "fGH")
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(match_operand:XF 2 "nonmemory_operand" "fGH")))]
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(define_insn "divtf3"
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[(set (match_operand:TF 0 "register_operand" "=f")
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(div:TF (match_operand:TF 1 "nonmemory_operand" "fGH")
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(match_operand:TF 2 "nonmemory_operand" "fGH")))]
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"TARGET_NUMERICS"
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"divr %2,%1,%0"
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[(set_attr "type" "fpdiv")])
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(define_insn "negxf2"
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[(set (match_operand:XF 0 "register_operand" "=f")
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(neg:XF (match_operand:XF 1 "register_operand" "f")))]
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(define_insn "negtf2"
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[(set (match_operand:TF 0 "register_operand" "=f")
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(neg:TF (match_operand:TF 1 "register_operand" "f")))]
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"TARGET_NUMERICS"
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"subr %1,0f0.0,%0"
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[(set_attr "type" "fpadd")])
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(define_insn "absxf2"
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[(set (match_operand:XF 0 "register_operand" "=f")
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(abs:XF (match_operand:XF 1 "register_operand" "f")))]
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(define_insn "abstf2"
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[(set (match_operand:TF 0 "register_operand" "=f")
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(abs:TF (match_operand:TF 1 "register_operand" "f")))]
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"(TARGET_NUMERICS)"
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"cpysre %1,0f0.0,%0"
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[(set_attr "type" "fpmove")])
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