i386.c (ix86_expand_setcc): Support 64bit.
* i386.c (ix86_expand_setcc): Support 64bit. (ix86_expand_int_movcc): Likewise. * i386.md (movdicc_rex64, x86_movsicc_0_m1_rex64, movdicc_c_rex64): New patterns. * i386.md (allocate_stack_worker): Turn to expander. (allocate_stack_worker_1, allocate_stack_worker_rex64): New insns. * i386.c (print_reg): Do not print x86_64 style regs on IA-32 From-SVN: r40958
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@ -1,3 +1,15 @@
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Fri Mar 30 00:21:41 CEST 2001 Jan Hubicka <jh@suse.cz>
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* i386.c (ix86_expand_setcc): Support 64bit.
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(ix86_expand_int_movcc): Likewise.
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* i386.md (movdicc_rex64, x86_movsicc_0_m1_rex64, movdicc_c_rex64):
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New patterns.
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* i386.md (allocate_stack_worker): Turn to expander.
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(allocate_stack_worker_1, allocate_stack_worker_rex64): New insns.
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* i386.c (print_reg): Do not print x86_64 style regs on IA-32
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2001-03-29 Richard Henderson <rth@redhat.com>
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* libgcc2.c [L__main]: Include unwind-dw2-fde.h instead of frame.h.
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@ -3798,6 +3798,8 @@ print_reg (x, code, file)
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from the normal registers. */
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if (REX_INT_REG_P (x))
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{
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if (!TARGET_64BIT)
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abort ();
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switch (code)
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{
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case 5:
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@ -3837,7 +3839,7 @@ print_reg (x, code, file)
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case 4:
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case 12:
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if (! ANY_FP_REG_P (x))
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putc (code == 8 ? 'r' : 'e', file);
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putc (code == 8 && TARGET_64BIT ? 'r' : 'e', file);
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/* FALLTHRU */
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case 16:
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case 2:
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@ -6112,7 +6114,8 @@ ix86_expand_setcc (code, dest)
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rtx second_test, bypass_test;
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int type;
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if (GET_MODE (ix86_compare_op0) == DImode)
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if (GET_MODE (ix86_compare_op0) == DImode
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&& !TARGET_64BIT)
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return 0; /* FAIL */
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/* Three modes of generation:
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@ -6229,6 +6232,7 @@ ix86_expand_int_movcc (operands)
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HImode insns, we'd be swallowed in word prefix ops. */
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if (GET_MODE (operands[0]) != HImode
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&& GET_MODE (operands[0]) != DImode
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&& GET_CODE (operands[2]) == CONST_INT
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&& GET_CODE (operands[3]) == CONST_INT)
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{
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@ -6362,28 +6366,46 @@ ix86_expand_int_movcc (operands)
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ix86_compare_op1, VOIDmode, 0, 1);
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nops = 0;
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/* On x86_64 the lea instruction operates on Pmode, so we need to get arithmetics
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done in proper mode to match. */
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if (diff == 1)
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tmp = out;
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{
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if (Pmode != SImode)
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tmp = gen_lowpart (Pmode, out);
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else
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tmp = out;
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}
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else
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{
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tmp = gen_rtx_MULT (SImode, out, GEN_INT (diff & ~1));
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rtx out1;
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if (Pmode != SImode)
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out1 = gen_lowpart (Pmode, out);
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else
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out1 = out;
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tmp = gen_rtx_MULT (Pmode, out1, GEN_INT (diff & ~1));
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nops++;
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if (diff & 1)
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{
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tmp = gen_rtx_PLUS (SImode, tmp, out);
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tmp = gen_rtx_PLUS (Pmode, tmp, out1);
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nops++;
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}
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}
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if (cf != 0)
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{
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tmp = gen_rtx_PLUS (SImode, tmp, GEN_INT (cf));
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tmp = gen_rtx_PLUS (Pmode, tmp, GEN_INT (cf));
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nops++;
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}
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if (tmp != out)
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if (tmp != out
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&& (GET_CODE (tmp) != SUBREG || SUBREG_REG (tmp) != out))
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{
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if (nops == 0)
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emit_move_insn (out, tmp);
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else if (nops == 1)
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if (Pmode != SImode)
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tmp = gen_rtx_SUBREG (SImode, tmp, 0);
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/* ??? We should to take care for outputing non-lea arithmetics
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for Pmode != SImode case too, but it is quite tricky and not
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too important, since all TARGET_64BIT machines support real
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conditional moves. */
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if (nops == 1 && Pmode == SImode)
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{
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rtx clob;
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@ -14919,6 +14919,45 @@
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;; Conditional move instructions.
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(define_expand "movdicc_rex64"
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[(set (match_operand:DI 0 "register_operand" "")
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(if_then_else:DI (match_operand 1 "comparison_operator" "")
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(match_operand:DI 2 "x86_64_general_operand" "")
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(match_operand:DI 3 "x86_64_general_operand" "")))]
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"TARGET_64BIT"
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"if (!ix86_expand_int_movcc (operands)) FAIL; DONE;")
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(define_insn "x86_movsicc_0_m1_rex64"
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[(set (match_operand:DI 0 "register_operand" "=r")
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(if_then_else:DI (ltu (reg:CC 17) (const_int 0))
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(const_int -1)
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(const_int 0)))
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(clobber (reg:CC 17))]
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"TARGET_64BIT"
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"sbb{l}\\t%0, %0"
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; Since we don't have the proper number of operands for an alu insn,
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; fill in all the blanks.
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[(set_attr "type" "alu")
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(set_attr "memory" "none")
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(set_attr "imm_disp" "false")
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(set_attr "mode" "DI")
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(set_attr "length_immediate" "0")])
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(define_insn "*movdicc_c_rex64"
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[(set (match_operand:DI 0 "register_operand" "=r,r")
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(if_then_else:DI (match_operator 1 "ix86_comparison_operator"
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[(reg 17) (const_int 0)])
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(match_operand:DI 2 "nonimmediate_operand" "rm,0")
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(match_operand:DI 3 "nonimmediate_operand" "0,rm")))]
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"TARGET_64BIT && TARGET_CMOVE
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&& (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
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"@
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cmov%C1\\t{%2, %0|%0, %2}
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cmov%c1\\t{%3, %0|%0, %3}"
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[(set_attr "type" "icmov")
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(set_attr "mode" "DI")])
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(define_expand "movsicc"
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[(set (match_operand:SI 0 "register_operand" "")
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(if_then_else:SI (match_operand 1 "comparison_operator" "")
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@ -15749,12 +15788,34 @@
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}
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}")
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(define_insn "allocate_stack_worker"
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(define_expand "allocate_stack_worker"
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[(match_operand:SI 0 "register_operand" "")]
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"TARGET_STACK_PROBE"
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"
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{
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if (TARGET_64BIT)
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emit_insn (gen_allocate_stack_worker_rex64 (operands[0]));
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else
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emit_insn (gen_allocate_stack_worker_1 (operands[0]));
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DONE;
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}")
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(define_insn "allocate_stack_worker_1"
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[(unspec:SI [(match_operand:SI 0 "register_operand" "a")] 3)
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(set (reg:SI 7) (minus:SI (reg:SI 7) (match_dup 0)))
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(clobber (match_dup 0))
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(clobber (reg:CC 17))]
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"TARGET_STACK_PROBE"
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"TARGET_STACK_PROBE && !TARGET_64BIT"
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"call\\t__alloca"
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[(set_attr "type" "multi")
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(set_attr "length" "5")])
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(define_insn "allocate_stack_worker_rex64"
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[(unspec:DI [(match_operand:DI 0 "register_operand" "a")] 3)
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(set (reg:DI 7) (minus:DI (reg:DI 7) (match_dup 0)))
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(clobber (match_dup 0))
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(clobber (reg:CC 17))]
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"TARGET_STACK_PROBE && TARGET_64BIT"
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"call\\t__alloca"
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[(set_attr "type" "multi")
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(set_attr "length" "5")])
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