* defaults.h (REGNO_MODE_OK_FOR_BASE_P, REG_MODE_OK_FOR_BASE_P)
(MODE_BASE_REG_REG_CLASS, REGNO_MODE_OK_FOR_REG_BASE_P) (REG_MODE_OK_FOR_REG_BASE_P): Provide default definitions. * regclass.c (record_address_regs): Remove ifdef. Use REG_MODE_OK_FOR_REG_BASE_P and MODE_BASE_REG_REG_CLASS. * regrename.c (REG_MODE_OK_FOR_BASE_P): Remove unnecessary definition. (scan_rtx_address, replace_oldest_value_addr): Use REG_MODE_OK_FOR_REG_BASE_P and MODE_BASE_REG_REG_CLASS. * reload.c (REGNO_MODE_OK_FOR_BASE_P, REG_MODE_OK_FOR_BASE_P): Remove unnecessary definitions. (find_reloads_address_1): Support REG_MODE_OK_FOR_REG_BASE_P and MODE_BASE_REG_REG_CLASS. * config/arm/arm.h (MODE_BASE_REG_CLASS): Don't check reload_completed. (MODE_BASE_REG_REG_CLASS): Define. (REGNO_MODE_OK_FOR_REG_BASE_P): Define. (REG_MODE_OK_FOR_REG_BASE_P): Define. * doc/tm.texi (Register Classes): Document MODE_BASE_REG_REG_CLASS, REG_MODE_OK_FOR_REG_BASE_P, and REGNO_MODE_OK_FOR_REG_BASE_P. From-SVN: r88948
This commit is contained in:
parent
3d4818fd4d
commit
888d2cd6b5
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@ -1,3 +1,25 @@
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2004-10-12 Daniel Jacobowitz <dan@debian.org>
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* defaults.h (REGNO_MODE_OK_FOR_BASE_P, REG_MODE_OK_FOR_BASE_P)
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(MODE_BASE_REG_REG_CLASS, REGNO_MODE_OK_FOR_REG_BASE_P)
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(REG_MODE_OK_FOR_REG_BASE_P): Provide default definitions.
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* regclass.c (record_address_regs): Remove ifdef. Use
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REG_MODE_OK_FOR_REG_BASE_P and MODE_BASE_REG_REG_CLASS.
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* regrename.c (REG_MODE_OK_FOR_BASE_P): Remove unnecessary
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definition.
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(scan_rtx_address, replace_oldest_value_addr): Use
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REG_MODE_OK_FOR_REG_BASE_P and MODE_BASE_REG_REG_CLASS.
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* reload.c (REGNO_MODE_OK_FOR_BASE_P, REG_MODE_OK_FOR_BASE_P): Remove
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unnecessary definitions.
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(find_reloads_address_1): Support REG_MODE_OK_FOR_REG_BASE_P
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and MODE_BASE_REG_REG_CLASS.
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* config/arm/arm.h (MODE_BASE_REG_CLASS): Don't check reload_completed.
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(MODE_BASE_REG_REG_CLASS): Define.
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(REGNO_MODE_OK_FOR_REG_BASE_P): Define.
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(REG_MODE_OK_FOR_REG_BASE_P): Define.
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* doc/tm.texi (Register Classes): Document MODE_BASE_REG_REG_CLASS,
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REG_MODE_OK_FOR_REG_BASE_P, and REGNO_MODE_OK_FOR_REG_BASE_P.
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2004-10-12 Daniel Berlin <dberlin@dberlin.org>
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* tree-ssa-alias.c (verify_name_tags): New function.
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@ -1218,12 +1218,14 @@ enum reg_class
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/* For the Thumb the high registers cannot be used as base registers
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when addressing quantities in QI or HI mode; if we don't know the
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mode, then we must be conservative. After reload we must also be
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conservative, since we can't support SP+reg addressing, and we
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can't fix up any bad substitutions. */
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mode, then we must be conservative. */
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#define MODE_BASE_REG_CLASS(MODE) \
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(TARGET_ARM ? GENERAL_REGS : \
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(((MODE) == SImode && !reload_completed) ? BASE_REGS : LO_REGS))
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(((MODE) == SImode) ? BASE_REGS : LO_REGS))
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/* For Thumb we can not support SP+reg addressing, so we return LO_REGS
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instead of BASE_REGS. */
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#define MODE_BASE_REG_REG_CLASS(MODE) BASE_REG_CLASS
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/* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
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registers explicitly used in the rtl to be used as spill registers
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@ -1980,6 +1982,11 @@ typedef struct
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? THUMB_REGNO_MODE_OK_FOR_BASE_P (REGNO, MODE) \
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: ARM_REGNO_OK_FOR_BASE_P (REGNO))
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/* Nonzero if X can be the base register in a reg+reg addressing mode.
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For Thumb, we can not use SP + reg, so reject SP. */
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#define REGNO_MODE_OK_FOR_REG_BASE_P(X, MODE) \
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REGNO_OK_FOR_INDEX_P (X)
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/* For ARM code, we don't care about the mode, but for Thumb, the index
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must be suitable for use in a QImode load. */
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#define REGNO_OK_FOR_INDEX_P(REGNO) \
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@ -2123,6 +2130,10 @@ typedef struct
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? THUMB_REG_OK_FOR_INDEX_P (X) \
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: ARM_REG_OK_FOR_INDEX_P (X))
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/* Nonzero if X can be the base register in a reg+reg addressing mode.
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For Thumb, we can not use SP + reg, so reject SP. */
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#define REG_MODE_OK_FOR_REG_BASE_P(X, MODE) \
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REG_OK_FOR_INDEX_P (X)
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/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
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that is a valid memory address for an instruction.
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@ -577,6 +577,19 @@ do { fputs (integer_asm_op (POINTER_SIZE / BITS_PER_UNIT, TRUE), FILE); \
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#define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT
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#endif
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/* Some macros can be defined by the backend in either a mode-dependent
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or mode-independent form. The compiler proper should only use the
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mode-dependent form, providing VOIDmode when the mode is unknown.
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We can't poison the macros because the backend may reference them. */
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#ifndef REGNO_MODE_OK_FOR_BASE_P
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#define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) REGNO_OK_FOR_BASE_P (REGNO)
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#endif
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#ifndef REG_MODE_OK_FOR_BASE_P
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#define REG_MODE_OK_FOR_BASE_P(REG, MODE) REG_OK_FOR_BASE_P (REG)
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#endif
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/* Determine the register class for registers suitable to be the base
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address register in a MEM. Allow the choice to be dependent upon
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the mode of the memory access. */
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#define MODE_BASE_REG_CLASS(MODE) BASE_REG_CLASS
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#endif
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/* Some machines require a different base register class if the index
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is a register. By default, assume that a base register is acceptable. */
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#ifndef MODE_BASE_REG_REG_CLASS
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#define MODE_BASE_REG_REG_CLASS(MODE) MODE_BASE_REG_CLASS(MODE)
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#endif
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#ifndef REGNO_MODE_OK_FOR_REG_BASE_P
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#define REGNO_MODE_OK_FOR_REG_BASE_P(REGNO, MODE) REGNO_MODE_OK_FOR_BASE_P (REGNO, MODE)
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#endif
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#ifndef REG_MODE_OK_FOR_REG_BASE_P
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#define REG_MODE_OK_FOR_REG_BASE_P(REGNO, MODE) REG_MODE_OK_FOR_BASE_P (REGNO, MODE)
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#endif
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#ifndef LARGEST_EXPONENT_IS_NORMAL
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#define LARGEST_EXPONENT_IS_NORMAL(SIZE) 0
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#endif
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@ -2402,6 +2402,13 @@ the selection of a base register in a mode dependent manner. If
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@code{BASE_REG_CLASS}.
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@end defmac
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@defmac MODE_BASE_REG_REG_CLASS (@var{mode})
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A C expression whose value is the register class to which a valid
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base register must belong in order to be used in a base plus index
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register address. You should define this macro if base plus index
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addresses have different requirements than other base register uses.
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@end defmac
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@defmac INDEX_REG_CLASS
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A macro whose definition is the name of the class to which a valid
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index register must belong. An index register is one used in an
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@code{REGNO_OK_FOR_BASE_P}.
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@end defmac
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@defmac REGNO_MODE_OK_FOR_REG_BASE_P (@var{num}, @var{mode})
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A C expression which is nonzero if register number @var{num} is suitable for
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use as a base register in base plus index operand addresses, accessing
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memory in mode @var{mode}. It may be either a suitable hard register or a
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pseudo register that has been allocated such a hard register. You should
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define this macro if base plus index addresses have different requirements
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than other base register uses.
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@end defmac
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@defmac REGNO_OK_FOR_INDEX_P (@var{num})
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A C expression which is nonzero if register number @var{num} is
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suitable for use as an index register in operand addresses. It may be
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@code{REG_OK_FOR_BASE_P}.
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@end defmac
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@defmac REG_MODE_OK_FOR_REG_BASE_P (@var{x}, @var{mode})
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A C expression which is nonzero if @var{x} (assumed to be a @code{reg} RTX)
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is suitable for use as a base register in base plus index operand addresses,
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accessing memory in mode @var{mode}. It may be either a suitable hard
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register or a pseudo register that has been allocated such a hard register.
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You should define this macro if base plus index addresses have different
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requirements than other base register uses.
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@end defmac
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@defmac REG_OK_FOR_INDEX_P (@var{x})
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A C expression that is nonzero if @var{x} (assumed to be a @code{reg}
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RTX) is valid for use as an index register.
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@ -2011,25 +2011,27 @@ record_address_regs (rtx x, enum reg_class class, int scale)
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record_address_regs (arg0, INDEX_REG_CLASS, scale);
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/* If both operands are registers but one is already a hard register
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of index or base class, give the other the class that the hard
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register is not. */
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of index or reg-base class, give the other the class that the
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hard register is not. */
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#ifdef REG_OK_FOR_BASE_P
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else if (code0 == REG && code1 == REG
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&& REGNO (arg0) < FIRST_PSEUDO_REGISTER
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&& (REG_OK_FOR_BASE_P (arg0) || REG_OK_FOR_INDEX_P (arg0)))
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&& (REG_MODE_OK_FOR_REG_BASE_P (arg0, VOIDmode)
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|| REG_OK_FOR_INDEX_P (arg0)))
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record_address_regs (arg1,
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REG_OK_FOR_BASE_P (arg0)
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? INDEX_REG_CLASS : MODE_BASE_REG_CLASS (VOIDmode),
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REG_MODE_OK_FOR_REG_BASE_P (arg0, VOIDmode)
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? INDEX_REG_CLASS
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: MODE_BASE_REG_REG_CLASS (VOIDmode),
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scale);
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else if (code0 == REG && code1 == REG
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&& REGNO (arg1) < FIRST_PSEUDO_REGISTER
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&& (REG_OK_FOR_BASE_P (arg1) || REG_OK_FOR_INDEX_P (arg1)))
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&& (REG_MODE_OK_FOR_REG_BASE_P (arg1, VOIDmode)
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|| REG_OK_FOR_INDEX_P (arg1)))
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record_address_regs (arg0,
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REG_OK_FOR_BASE_P (arg1)
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? INDEX_REG_CLASS : MODE_BASE_REG_CLASS (VOIDmode),
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REG_MODE_OK_FOR_REG_BASE_P (arg1, VOIDmode)
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? INDEX_REG_CLASS
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: MODE_BASE_REG_REG_CLASS (VOIDmode),
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scale);
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#endif
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/* If one operand is known to be a pointer, it must be the base
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with the other operand the index. Likewise if the other operand
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@ -2038,14 +2040,16 @@ record_address_regs (rtx x, enum reg_class class, int scale)
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else if ((code0 == REG && REG_POINTER (arg0))
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|| code1 == MULT)
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{
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record_address_regs (arg0, MODE_BASE_REG_CLASS (VOIDmode), scale);
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record_address_regs (arg0, MODE_BASE_REG_REG_CLASS (VOIDmode),
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scale);
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record_address_regs (arg1, INDEX_REG_CLASS, scale);
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}
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else if ((code1 == REG && REG_POINTER (arg1))
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|| code0 == MULT)
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{
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record_address_regs (arg0, INDEX_REG_CLASS, scale);
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record_address_regs (arg1, MODE_BASE_REG_CLASS (VOIDmode), scale);
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record_address_regs (arg1, MODE_BASE_REG_REG_CLASS (VOIDmode),
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scale);
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}
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/* Otherwise, count equal chances that each might be a base
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@ -2053,10 +2057,10 @@ record_address_regs (rtx x, enum reg_class class, int scale)
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else
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{
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record_address_regs (arg0, MODE_BASE_REG_CLASS (VOIDmode),
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record_address_regs (arg0, MODE_BASE_REG_REG_CLASS (VOIDmode),
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scale / 2);
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record_address_regs (arg0, INDEX_REG_CLASS, scale / 2);
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record_address_regs (arg1, MODE_BASE_REG_CLASS (VOIDmode),
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record_address_regs (arg1, MODE_BASE_REG_REG_CLASS (VOIDmode),
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scale / 2);
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record_address_regs (arg1, INDEX_REG_CLASS, scale / 2);
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}
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@ -36,10 +36,6 @@
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#include "toplev.h"
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#include "obstack.h"
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#ifndef REG_MODE_OK_FOR_BASE_P
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#define REG_MODE_OK_FOR_BASE_P(REGNO, MODE) REG_OK_FOR_BASE_P (REGNO)
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#endif
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static const char *const reg_class_names[] = REG_CLASS_NAMES;
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struct du_chain
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@ -524,6 +520,7 @@ scan_rtx_address (rtx insn, rtx *loc, enum reg_class cl,
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rtx op1 = orig_op1;
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rtx *locI = NULL;
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rtx *locB = NULL;
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rtx *locB_reg = NULL;
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if (GET_CODE (op0) == SUBREG)
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{
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@ -560,14 +557,14 @@ scan_rtx_address (rtx insn, rtx *loc, enum reg_class cl,
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int index_op;
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if (REG_OK_FOR_INDEX_P (op0)
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&& REG_MODE_OK_FOR_BASE_P (op1, mode))
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&& REG_MODE_OK_FOR_REG_BASE_P (op1, mode))
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index_op = 0;
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else if (REG_OK_FOR_INDEX_P (op1)
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&& REG_MODE_OK_FOR_BASE_P (op0, mode))
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&& REG_MODE_OK_FOR_REG_BASE_P (op0, mode))
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index_op = 1;
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else if (REG_MODE_OK_FOR_BASE_P (op1, mode))
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else if (REG_MODE_OK_FOR_REG_BASE_P (op1, mode))
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index_op = 0;
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else if (REG_MODE_OK_FOR_BASE_P (op0, mode))
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else if (REG_MODE_OK_FOR_REG_BASE_P (op0, mode))
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index_op = 1;
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else if (REG_OK_FOR_INDEX_P (op1))
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index_op = 1;
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|
@ -575,7 +572,7 @@ scan_rtx_address (rtx insn, rtx *loc, enum reg_class cl,
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index_op = 0;
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locI = &XEXP (x, index_op);
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locB = &XEXP (x, !index_op);
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locB_reg = &XEXP (x, !index_op);
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}
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else if (code0 == REG)
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{
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|
@ -592,6 +589,9 @@ scan_rtx_address (rtx insn, rtx *loc, enum reg_class cl,
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scan_rtx_address (insn, locI, INDEX_REG_CLASS, action, mode);
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if (locB)
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scan_rtx_address (insn, locB, MODE_BASE_REG_CLASS (mode), action, mode);
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if (locB_reg)
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scan_rtx_address (insn, locB_reg, MODE_BASE_REG_REG_CLASS (mode),
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action, mode);
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return;
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}
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@ -1415,6 +1415,7 @@ replace_oldest_value_addr (rtx *loc, enum reg_class cl,
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rtx op1 = orig_op1;
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rtx *locI = NULL;
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rtx *locB = NULL;
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rtx *locB_reg = NULL;
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if (GET_CODE (op0) == SUBREG)
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{
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|
@ -1451,14 +1452,14 @@ replace_oldest_value_addr (rtx *loc, enum reg_class cl,
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int index_op;
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if (REG_OK_FOR_INDEX_P (op0)
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&& REG_MODE_OK_FOR_BASE_P (op1, mode))
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&& REG_MODE_OK_FOR_REG_BASE_P (op1, mode))
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index_op = 0;
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else if (REG_OK_FOR_INDEX_P (op1)
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&& REG_MODE_OK_FOR_BASE_P (op0, mode))
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&& REG_MODE_OK_FOR_REG_BASE_P (op0, mode))
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index_op = 1;
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else if (REG_MODE_OK_FOR_BASE_P (op1, mode))
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else if (REG_MODE_OK_FOR_REG_BASE_P (op1, mode))
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index_op = 0;
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else if (REG_MODE_OK_FOR_BASE_P (op0, mode))
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else if (REG_MODE_OK_FOR_REG_BASE_P (op0, mode))
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index_op = 1;
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else if (REG_OK_FOR_INDEX_P (op1))
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index_op = 1;
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|
@ -1466,7 +1467,7 @@ replace_oldest_value_addr (rtx *loc, enum reg_class cl,
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index_op = 0;
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locI = &XEXP (x, index_op);
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locB = &XEXP (x, !index_op);
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locB_reg = &XEXP (x, !index_op);
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}
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else if (code0 == REG)
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{
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|
@ -1486,6 +1487,10 @@ replace_oldest_value_addr (rtx *loc, enum reg_class cl,
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changed |= replace_oldest_value_addr (locB,
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MODE_BASE_REG_CLASS (mode),
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mode, insn, vd);
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if (locB_reg)
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changed |= replace_oldest_value_addr (locB_reg,
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MODE_BASE_REG_REG_CLASS (mode),
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mode, insn, vd);
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return changed;
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}
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|
|
83
gcc/reload.c
83
gcc/reload.c
|
@ -108,14 +108,6 @@ a register with any other reload. */
|
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#include "params.h"
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#include "target.h"
|
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#ifndef REGNO_MODE_OK_FOR_BASE_P
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#define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) REGNO_OK_FOR_BASE_P (REGNO)
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#endif
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|
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#ifndef REG_MODE_OK_FOR_BASE_P
|
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#define REG_MODE_OK_FOR_BASE_P(REGNO, MODE) REG_OK_FOR_BASE_P (REGNO)
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#endif
|
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|
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/* True if X is a constant that can be forced into the constant pool. */
|
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#define CONST_POOL_OK_P(X) \
|
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(CONSTANT_P (X) \
|
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|
@ -5227,7 +5219,8 @@ update_auto_inc_notes (rtx insn ATTRIBUTE_UNUSED, int regno ATTRIBUTE_UNUSED,
|
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is strictly valid.)
|
||||
|
||||
CONTEXT = 1 means we are considering regs as index regs,
|
||||
= 0 means we are considering them as base regs.
|
||||
= 0 means we are considering them as base regs, = 2 means we
|
||||
are considering them as base regs for REG + REG.
|
||||
|
||||
OPNUM and TYPE specify the purpose of any reloads made.
|
||||
|
||||
|
@ -5250,8 +5243,23 @@ find_reloads_address_1 (enum machine_mode mode, rtx x, int context,
|
|||
rtx *loc, int opnum, enum reload_type type,
|
||||
int ind_levels, rtx insn)
|
||||
{
|
||||
#define REG_OK_FOR_CONTEXT(CONTEXT, REGNO, MODE) \
|
||||
((CONTEXT) == 2 \
|
||||
? REGNO_MODE_OK_FOR_REG_BASE_P (REGNO, MODE) \
|
||||
: (CONTEXT) == 1 \
|
||||
? REGNO_OK_FOR_INDEX_P (REGNO) \
|
||||
: REGNO_MODE_OK_FOR_BASE_P (REGNO, MODE))
|
||||
|
||||
enum reg_class context_reg_class;
|
||||
RTX_CODE code = GET_CODE (x);
|
||||
|
||||
if (context == 2)
|
||||
context_reg_class = MODE_BASE_REG_REG_CLASS (mode);
|
||||
else if (context == 1)
|
||||
context_reg_class = INDEX_REG_CLASS;
|
||||
else
|
||||
context_reg_class = MODE_BASE_REG_CLASS (mode);
|
||||
|
||||
switch (code)
|
||||
{
|
||||
case PLUS:
|
||||
|
@ -5294,12 +5302,12 @@ find_reloads_address_1 (enum machine_mode mode, rtx x, int context,
|
|||
register remateralization for expression like &localvar*4. Reload it.
|
||||
It may be possible to combine the displacement on the outer level,
|
||||
but it is probably not worthwhile to do so. */
|
||||
if (context)
|
||||
if (context == 1)
|
||||
{
|
||||
find_reloads_address (GET_MODE (x), loc, XEXP (x, 0), &XEXP (x, 0),
|
||||
opnum, ADDR_TYPE (type), ind_levels, insn);
|
||||
push_reload (*loc, NULL_RTX, loc, (rtx*) 0,
|
||||
(context ? INDEX_REG_CLASS : MODE_BASE_REG_CLASS (mode)),
|
||||
context_reg_class,
|
||||
GET_MODE (x), VOIDmode, 0, 0, opnum, type);
|
||||
return 1;
|
||||
}
|
||||
|
@ -5335,22 +5343,22 @@ find_reloads_address_1 (enum machine_mode mode, rtx x, int context,
|
|||
else if (code0 == REG && code1 == REG)
|
||||
{
|
||||
if (REG_OK_FOR_INDEX_P (op0)
|
||||
&& REG_MODE_OK_FOR_BASE_P (op1, mode))
|
||||
&& REG_MODE_OK_FOR_REG_BASE_P (op1, mode))
|
||||
return 0;
|
||||
else if (REG_OK_FOR_INDEX_P (op1)
|
||||
&& REG_MODE_OK_FOR_BASE_P (op0, mode))
|
||||
&& REG_MODE_OK_FOR_REG_BASE_P (op0, mode))
|
||||
return 0;
|
||||
else if (REG_MODE_OK_FOR_BASE_P (op1, mode))
|
||||
else if (REG_MODE_OK_FOR_REG_BASE_P (op1, mode))
|
||||
find_reloads_address_1 (mode, orig_op0, 1, &XEXP (x, 0), opnum,
|
||||
type, ind_levels, insn);
|
||||
else if (REG_MODE_OK_FOR_BASE_P (op0, mode))
|
||||
else if (REG_MODE_OK_FOR_REG_BASE_P (op0, mode))
|
||||
find_reloads_address_1 (mode, orig_op1, 1, &XEXP (x, 1), opnum,
|
||||
type, ind_levels, insn);
|
||||
else if (REG_OK_FOR_INDEX_P (op1))
|
||||
find_reloads_address_1 (mode, orig_op0, 0, &XEXP (x, 0), opnum,
|
||||
find_reloads_address_1 (mode, orig_op0, 2, &XEXP (x, 0), opnum,
|
||||
type, ind_levels, insn);
|
||||
else if (REG_OK_FOR_INDEX_P (op0))
|
||||
find_reloads_address_1 (mode, orig_op1, 0, &XEXP (x, 1), opnum,
|
||||
find_reloads_address_1 (mode, orig_op1, 2, &XEXP (x, 1), opnum,
|
||||
type, ind_levels, insn);
|
||||
else
|
||||
{
|
||||
|
@ -5514,9 +5522,8 @@ find_reloads_address_1 (enum machine_mode mode, rtx x, int context,
|
|||
|
||||
if (reg_renumber[regno] >= 0)
|
||||
regno = reg_renumber[regno];
|
||||
if ((regno >= FIRST_PSEUDO_REGISTER
|
||||
|| !(context ? REGNO_OK_FOR_INDEX_P (regno)
|
||||
: REGNO_MODE_OK_FOR_BASE_P (regno, mode))))
|
||||
if (regno >= FIRST_PSEUDO_REGISTER
|
||||
|| !REG_OK_FOR_CONTEXT (context, regno, mode))
|
||||
{
|
||||
int reloadnum;
|
||||
|
||||
|
@ -5552,8 +5559,7 @@ find_reloads_address_1 (enum machine_mode mode, rtx x, int context,
|
|||
x = XEXP (x, 0);
|
||||
reloadnum
|
||||
= push_reload (x, x, loc, loc,
|
||||
(context ? INDEX_REG_CLASS :
|
||||
MODE_BASE_REG_CLASS (mode)),
|
||||
context_reg_class,
|
||||
GET_MODE (x), GET_MODE (x), 0, 0,
|
||||
opnum, RELOAD_OTHER);
|
||||
}
|
||||
|
@ -5561,8 +5567,7 @@ find_reloads_address_1 (enum machine_mode mode, rtx x, int context,
|
|||
{
|
||||
reloadnum
|
||||
= push_reload (x, NULL_RTX, loc, (rtx*) 0,
|
||||
(context ? INDEX_REG_CLASS :
|
||||
MODE_BASE_REG_CLASS (mode)),
|
||||
context_reg_class,
|
||||
GET_MODE (x), GET_MODE (x), 0, 0,
|
||||
opnum, type);
|
||||
rld[reloadnum].inc
|
||||
|
@ -5602,8 +5607,7 @@ find_reloads_address_1 (enum machine_mode mode, rtx x, int context,
|
|||
opnum, type, ind_levels, insn);
|
||||
|
||||
reloadnum = push_reload (x, NULL_RTX, loc, (rtx*) 0,
|
||||
(context ? INDEX_REG_CLASS :
|
||||
MODE_BASE_REG_CLASS (mode)),
|
||||
context_reg_class,
|
||||
GET_MODE (x), VOIDmode, 0, 0, opnum, type);
|
||||
rld[reloadnum].inc
|
||||
= find_inc_amount (PATTERN (this_insn), XEXP (x, 0));
|
||||
|
@ -5632,7 +5636,7 @@ find_reloads_address_1 (enum machine_mode mode, rtx x, int context,
|
|||
find_reloads_address (GET_MODE (x), loc, XEXP (x, 0), &XEXP (x, 0),
|
||||
opnum, ADDR_TYPE (type), ind_levels, insn);
|
||||
push_reload (*loc, NULL_RTX, loc, (rtx*) 0,
|
||||
(context ? INDEX_REG_CLASS : MODE_BASE_REG_CLASS (mode)),
|
||||
context_reg_class,
|
||||
GET_MODE (x), VOIDmode, 0, 0, opnum, type);
|
||||
return 1;
|
||||
|
||||
|
@ -5643,8 +5647,7 @@ find_reloads_address_1 (enum machine_mode mode, rtx x, int context,
|
|||
if (reg_equiv_constant[regno] != 0)
|
||||
{
|
||||
find_reloads_address_part (reg_equiv_constant[regno], loc,
|
||||
(context ? INDEX_REG_CLASS :
|
||||
MODE_BASE_REG_CLASS (mode)),
|
||||
context_reg_class,
|
||||
GET_MODE (x), opnum, type, ind_levels);
|
||||
return 1;
|
||||
}
|
||||
|
@ -5654,8 +5657,7 @@ find_reloads_address_1 (enum machine_mode mode, rtx x, int context,
|
|||
if (reg_equiv_mem[regno] != 0)
|
||||
{
|
||||
push_reload (reg_equiv_mem[regno], NULL_RTX, loc, (rtx*) 0,
|
||||
(context ? INDEX_REG_CLASS :
|
||||
MODE_BASE_REG_CLASS (mode)),
|
||||
context_reg_class,
|
||||
GET_MODE (x), VOIDmode, 0, 0, opnum, type);
|
||||
return 1;
|
||||
}
|
||||
|
@ -5678,12 +5680,11 @@ find_reloads_address_1 (enum machine_mode mode, rtx x, int context,
|
|||
if (reg_renumber[regno] >= 0)
|
||||
regno = reg_renumber[regno];
|
||||
|
||||
if ((regno >= FIRST_PSEUDO_REGISTER
|
||||
|| !(context ? REGNO_OK_FOR_INDEX_P (regno)
|
||||
: REGNO_MODE_OK_FOR_BASE_P (regno, mode))))
|
||||
if (regno >= FIRST_PSEUDO_REGISTER
|
||||
|| !REG_OK_FOR_CONTEXT (context, regno, mode))
|
||||
{
|
||||
push_reload (x, NULL_RTX, loc, (rtx*) 0,
|
||||
(context ? INDEX_REG_CLASS : MODE_BASE_REG_CLASS (mode)),
|
||||
context_reg_class,
|
||||
GET_MODE (x), VOIDmode, 0, 0, opnum, type);
|
||||
return 1;
|
||||
}
|
||||
|
@ -5695,7 +5696,7 @@ find_reloads_address_1 (enum machine_mode mode, rtx x, int context,
|
|||
if (regno_clobbered_p (regno, this_insn, GET_MODE (x), 0))
|
||||
{
|
||||
push_reload (x, NULL_RTX, loc, (rtx*) 0,
|
||||
(context ? INDEX_REG_CLASS : MODE_BASE_REG_CLASS (mode)),
|
||||
context_reg_class,
|
||||
GET_MODE (x), VOIDmode, 0, 0, opnum, type);
|
||||
return 1;
|
||||
}
|
||||
|
@ -5712,12 +5713,10 @@ find_reloads_address_1 (enum machine_mode mode, rtx x, int context,
|
|||
{
|
||||
int regno ATTRIBUTE_UNUSED = subreg_regno (x);
|
||||
|
||||
if (! (context ? REGNO_OK_FOR_INDEX_P (regno)
|
||||
: REGNO_MODE_OK_FOR_BASE_P (regno, mode)))
|
||||
if (! REG_OK_FOR_CONTEXT (context, regno, mode))
|
||||
{
|
||||
push_reload (x, NULL_RTX, loc, (rtx*) 0,
|
||||
(context ? INDEX_REG_CLASS :
|
||||
MODE_BASE_REG_CLASS (mode)),
|
||||
context_reg_class,
|
||||
GET_MODE (x), VOIDmode, 0, 0, opnum, type);
|
||||
return 1;
|
||||
}
|
||||
|
@ -5726,8 +5725,7 @@ find_reloads_address_1 (enum machine_mode mode, rtx x, int context,
|
|||
is larger than the class size, then reload the whole SUBREG. */
|
||||
else
|
||||
{
|
||||
enum reg_class class = (context ? INDEX_REG_CLASS
|
||||
: MODE_BASE_REG_CLASS (mode));
|
||||
enum reg_class class = context_reg_class;
|
||||
if ((unsigned) CLASS_MAX_NREGS (class, GET_MODE (SUBREG_REG (x)))
|
||||
> reg_class_size[class])
|
||||
{
|
||||
|
@ -5757,6 +5755,7 @@ find_reloads_address_1 (enum machine_mode mode, rtx x, int context,
|
|||
}
|
||||
}
|
||||
|
||||
#undef REG_OK_FOR_CONTEXT
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
Loading…
Reference in New Issue