[AArch64] Improve description of <F>CM instructions in RTL
gcc/ * config/aarch64/aarch64-simd-builtins.def (cmhs): Rename to... (cmgeu): ...This. (cmhi): Rename to... (cmgtu): ...This. * config/aarch64/aarch64-simd.md (simd_mode): Add SF. (aarch64_vcond_internal): Use new names for unsigned comparison insns. (aarch64_cm<optab><mode>): Rewrite to not use UNSPECs. * config/aarch64/aarch64.md (*cstore<mode>_neg): Rename to... (cstore<mode>_neg): ...This. * config/aarch64/iterators.md (VALLF): new. (unspec): Remove UNSPEC_CM<EQ, LE, LT, GE, GT, HS, HI, TST>. (COMPARISONS): New. (UCOMPARISONS): Likewise. (optab): Add missing comparisons. (n_optab): New. (cmp_1): Likewise. (cmp_2): Likewise. (CMP): Likewise. (cmp): Remove. (VCMP_S): Likewise. (VCMP_U): Likewise. (V_cmp_result): Add DF, SF modes. (v_cmp_result): Likewise. (v): Likewise. (vmtype): Likewise. * config/aarch64/predicates.md (aarch64_reg_or_fp_zero): New. From-SVN: r198490
This commit is contained in:
James Greenhalgh
James Greenhalgh
parent
0a7dbb7661
commit
889b941239
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@ -1,3 +1,34 @@
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2013-05-01 James Greenhalgh <james.greenhalgh@arm.com>
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* config/aarch64/aarch64-simd-builtins.def (cmhs): Rename to...
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(cmgeu): ...This.
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(cmhi): Rename to...
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(cmgtu): ...This.
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* config/aarch64/aarch64-simd.md
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(simd_mode): Add SF.
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(aarch64_vcond_internal): Use new names for unsigned comparison insns.
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(aarch64_cm<optab><mode>): Rewrite to not use UNSPECs.
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* config/aarch64/aarch64.md (*cstore<mode>_neg): Rename to...
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(cstore<mode>_neg): ...This.
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* config/aarch64/iterators.md
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(VALLF): new.
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(unspec): Remove UNSPEC_CM<EQ, LE, LT, GE, GT, HS, HI, TST>.
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(COMPARISONS): New.
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(UCOMPARISONS): Likewise.
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(optab): Add missing comparisons.
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(n_optab): New.
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(cmp_1): Likewise.
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(cmp_2): Likewise.
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(CMP): Likewise.
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(cmp): Remove.
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(VCMP_S): Likewise.
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(VCMP_U): Likewise.
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(V_cmp_result): Add DF, SF modes.
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(v_cmp_result): Likewise.
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(v): Likewise.
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(vmtype): Likewise.
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* config/aarch64/predicates.md (aarch64_reg_or_fp_zero): New.
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2013-05-01 Greta Yorsh <Greta.Yorsh@arm.com>
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* config/arm/thumb2.md (thumb2_smaxsi3,thumb2_sminsi3): Convert
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@ -230,8 +230,8 @@
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BUILTIN_VSDQ_I_DI (BINOP, cmle, 0)
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BUILTIN_VSDQ_I_DI (BINOP, cmlt, 0)
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/* Implemented by aarch64_cm<cmp><mode>. */
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BUILTIN_VSDQ_I_DI (BINOP, cmhs, 0)
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BUILTIN_VSDQ_I_DI (BINOP, cmhi, 0)
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BUILTIN_VSDQ_I_DI (BINOP, cmgeu, 0)
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BUILTIN_VSDQ_I_DI (BINOP, cmgtu, 0)
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BUILTIN_VSDQ_I_DI (BINOP, cmtst, 0)
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/* Implemented by aarch64_<fmaxmin><mode>. */
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@ -21,7 +21,7 @@
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; Main data types used by the insntructions
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(define_attr "simd_mode" "unknown,none,V8QI,V16QI,V4HI,V8HI,V2SI,V4SI,V2DI,V2SF,V4SF,V2DF,OI,CI,XI,DI,DF,SI,HI,QI"
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(define_attr "simd_mode" "unknown,none,V8QI,V16QI,V4HI,V8HI,V2SI,V4SI,V2DI,V2SF,V4SF,V2DF,OI,CI,XI,DI,DF,SI,SF,HI,QI"
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(const_string "unknown"))
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@ -1728,12 +1728,12 @@
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case LTU:
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case GEU:
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emit_insn (gen_aarch64_cmhs<mode> (mask, operands[4], operands[5]));
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emit_insn (gen_aarch64_cmgeu<mode> (mask, operands[4], operands[5]));
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break;
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case LEU:
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case GTU:
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emit_insn (gen_aarch64_cmhi<mode> (mask, operands[4], operands[5]));
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emit_insn (gen_aarch64_cmgtu<mode> (mask, operands[4], operands[5]));
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break;
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case NE:
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@ -3170,48 +3170,181 @@
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)
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;; cm(eq|ge|le|lt|gt)
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;; cm(eq|ge|gt|lt|le)
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;; Note, we have constraints for Dz and Z as different expanders
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;; have different ideas of what should be passed to this pattern.
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(define_insn "aarch64_cm<cmp><mode>"
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(define_insn "aarch64_cm<optab><mode>"
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[(set (match_operand:<V_cmp_result> 0 "register_operand" "=w,w")
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(unspec:<V_cmp_result>
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[(match_operand:VSDQ_I_DI 1 "register_operand" "w,w")
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(match_operand:VSDQ_I_DI 2 "aarch64_simd_reg_or_zero" "w,Z")]
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VCMP_S))]
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(neg:<V_cmp_result>
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(COMPARISONS:<V_cmp_result>
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(match_operand:VDQ 1 "register_operand" "w,w")
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(match_operand:VDQ 2 "aarch64_simd_reg_or_zero" "w,ZDz")
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)))]
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"TARGET_SIMD"
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"@
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cm<cmp>\t%<v>0<Vmtype>, %<v>1<Vmtype>, %<v>2<Vmtype>
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cm<cmp>\t%<v>0<Vmtype>, %<v>1<Vmtype>, #0"
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cm<n_optab>\t%<v>0<Vmtype>, %<v><cmp_1><Vmtype>, %<v><cmp_2><Vmtype>
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cm<optab>\t%<v>0<Vmtype>, %<v>1<Vmtype>, #0"
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[(set_attr "simd_type" "simd_cmp")
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(set_attr "simd_mode" "<MODE>")]
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)
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;; cm(hs|hi|tst)
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(define_insn_and_split "aarch64_cm<optab>di"
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[(set (match_operand:DI 0 "register_operand" "=w,w,r")
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(neg:DI
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(COMPARISONS:DI
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(match_operand:DI 1 "register_operand" "w,w,r")
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(match_operand:DI 2 "aarch64_simd_reg_or_zero" "w,ZDz,r")
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)))]
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"TARGET_SIMD"
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"@
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cm<n_optab>\t%d0, %d<cmp_1>, %d<cmp_2>
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cm<optab>\t%d0, %d1, #0
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#"
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"reload_completed
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/* We need to prevent the split from
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happening in the 'w' constraint cases. */
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&& GP_REGNUM_P (REGNO (operands[0]))
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&& GP_REGNUM_P (REGNO (operands[1]))"
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[(set (reg:CC CC_REGNUM)
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(compare:CC
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(match_dup 1)
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(match_dup 2)))
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(set (match_dup 0)
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(neg:DI
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(COMPARISONS:DI
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(match_operand 3 "cc_register" "")
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(const_int 0))))]
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{
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enum machine_mode mode = SELECT_CC_MODE (<CMP>, operands[1], operands[2]);
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rtx cc_reg = aarch64_gen_compare_reg (<CMP>, operands[1], operands[2]);
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rtx comparison = gen_rtx_<CMP> (mode, operands[1], operands[2]);
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emit_insn (gen_cstoredi_neg (operands[0], comparison, cc_reg));
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DONE;
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}
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[(set_attr "simd_type" "simd_cmp")
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(set_attr "simd_mode" "DI")]
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)
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(define_insn "aarch64_cm<cmp><mode>"
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;; cm(hs|hi)
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(define_insn "aarch64_cm<optab><mode>"
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[(set (match_operand:<V_cmp_result> 0 "register_operand" "=w")
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(unspec:<V_cmp_result>
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[(match_operand:VSDQ_I_DI 1 "register_operand" "w")
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(match_operand:VSDQ_I_DI 2 "register_operand" "w")]
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VCMP_U))]
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(neg:<V_cmp_result>
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(UCOMPARISONS:<V_cmp_result>
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(match_operand:VDQ 1 "register_operand" "w")
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(match_operand:VDQ 2 "register_operand" "w")
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)))]
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"TARGET_SIMD"
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"cm<cmp>\t%<v>0<Vmtype>, %<v>1<Vmtype>, %<v>2<Vmtype>"
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"cm<n_optab>\t%<v>0<Vmtype>, %<v><cmp_1><Vmtype>, %<v><cmp_2><Vmtype>"
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[(set_attr "simd_type" "simd_cmp")
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(set_attr "simd_mode" "<MODE>")]
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)
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;; fcm(eq|ge|le|lt|gt)
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(define_insn "aarch64_cm<cmp><mode>"
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[(set (match_operand:<V_cmp_result> 0 "register_operand" "=w,w")
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(unspec:<V_cmp_result>
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[(match_operand:VDQF 1 "register_operand" "w,w")
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(match_operand:VDQF 2 "aarch64_simd_reg_or_zero" "w,Dz")]
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VCMP_S))]
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(define_insn_and_split "aarch64_cm<optab>di"
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[(set (match_operand:DI 0 "register_operand" "=w,r")
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(neg:DI
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(UCOMPARISONS:DI
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(match_operand:DI 1 "register_operand" "w,r")
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(match_operand:DI 2 "aarch64_simd_reg_or_zero" "w,r")
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)))]
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"TARGET_SIMD"
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"@
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fcm<cmp>\t%<v>0<Vmtype>, %<v>1<Vmtype>, %<v>2<Vmtype>
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fcm<cmp>\t%<v>0<Vmtype>, %<v>1<Vmtype>, 0"
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cm<n_optab>\t%d0, %d<cmp_1>, %d<cmp_2>
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#"
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"reload_completed
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/* We need to prevent the split from
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happening in the 'w' constraint cases. */
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&& GP_REGNUM_P (REGNO (operands[0]))
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&& GP_REGNUM_P (REGNO (operands[1]))"
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[(set (reg:CC CC_REGNUM)
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(compare:CC
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(match_dup 1)
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(match_dup 2)))
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(set (match_dup 0)
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(neg:DI
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(UCOMPARISONS:DI
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(match_operand 3 "cc_register" "")
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(const_int 0))))]
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{
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enum machine_mode mode = SELECT_CC_MODE (<CMP>, operands[1], operands[2]);
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rtx cc_reg = aarch64_gen_compare_reg (<CMP>, operands[1], operands[2]);
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rtx comparison = gen_rtx_<CMP> (mode, operands[1], operands[2]);
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emit_insn (gen_cstoredi_neg (operands[0], comparison, cc_reg));
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DONE;
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}
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[(set_attr "simd_type" "simd_cmp")
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(set_attr "simd_mode" "DI")]
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)
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;; cmtst
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(define_insn "aarch64_cmtst<mode>"
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[(set (match_operand:<V_cmp_result> 0 "register_operand" "=w")
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(neg:<V_cmp_result>
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(ne:<V_cmp_result>
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(and:VDQ
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(match_operand:VDQ 1 "register_operand" "w")
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(match_operand:VDQ 2 "register_operand" "w"))
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(vec_duplicate:<V_cmp_result> (const_int 0)))))]
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"TARGET_SIMD"
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"cmtst\t%<v>0<Vmtype>, %<v>1<Vmtype>, %<v>2<Vmtype>"
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[(set_attr "simd_type" "simd_cmp")
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(set_attr "simd_mode" "<MODE>")]
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)
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(define_insn_and_split "aarch64_cmtstdi"
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[(set (match_operand:DI 0 "register_operand" "=w,r")
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(neg:DI
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(ne:DI
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(and:DI
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(match_operand:DI 1 "register_operand" "w,r")
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(match_operand:DI 2 "register_operand" "w,r"))
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(const_int 0))))]
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"TARGET_SIMD"
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"@
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cmtst\t%d0, %d1, %d2
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#"
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"reload_completed
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/* We need to prevent the split from
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happening in the 'w' constraint cases. */
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&& GP_REGNUM_P (REGNO (operands[0]))
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&& GP_REGNUM_P (REGNO (operands[1]))"
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[(set (reg:CC_NZ CC_REGNUM)
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(compare:CC_NZ
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(and:DI (match_dup 1)
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(match_dup 2))
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(const_int 0)))
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(set (match_dup 0)
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(neg:DI
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(ne:DI
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(match_operand 3 "cc_register" "")
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(const_int 0))))]
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{
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rtx and_tree = gen_rtx_AND (DImode, operands[1], operands[2]);
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enum machine_mode mode = SELECT_CC_MODE (NE, and_tree, const0_rtx);
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rtx cc_reg = aarch64_gen_compare_reg (NE, and_tree, const0_rtx);
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rtx comparison = gen_rtx_NE (mode, and_tree, const0_rtx);
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emit_insn (gen_cstoredi_neg (operands[0], comparison, cc_reg));
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DONE;
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}
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[(set_attr "simd_type" "simd_cmp")
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(set_attr "simd_mode" "DI")]
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)
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;; fcm(eq|ge|gt|le|lt)
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(define_insn "aarch64_cm<optab><mode>"
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[(set (match_operand:<V_cmp_result> 0 "register_operand" "=w,w")
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(neg:<V_cmp_result>
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(COMPARISONS:<V_cmp_result>
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(match_operand:VALLF 1 "register_operand" "w,w")
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(match_operand:VALLF 2 "aarch64_simd_reg_or_zero" "w,YDz")
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)))]
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"TARGET_SIMD"
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"@
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fcm<n_optab>\t%<v>0<Vmtype>, %<v><cmp_1><Vmtype>, %<v><cmp_2><Vmtype>
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fcm<optab>\t%<v>0<Vmtype>, %<v>1<Vmtype>, 0"
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[(set_attr "simd_type" "simd_fcmp")
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(set_attr "simd_mode" "<MODE>")]
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)
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@ -2409,7 +2409,7 @@
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(set_attr "mode" "SI")]
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)
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(define_insn "*cstore<mode>_neg"
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(define_insn "cstore<mode>_neg"
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[(set (match_operand:ALLI 0 "register_operand" "=r")
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(neg:ALLI (match_operator:ALLI 1 "aarch64_comparison_operator"
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[(match_operand 2 "cc_register" "") (const_int 0)])))]
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@ -83,6 +83,9 @@
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;; Vector Float modes.
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(define_mode_iterator VDQF [V2SF V4SF V2DF])
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;; All Float modes.
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(define_mode_iterator VALLF [V2SF V4SF V2DF SF DF])
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;; Vector Float modes with 2 elements.
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(define_mode_iterator V2F [V2SF V2DF])
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@ -213,13 +216,6 @@
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UNSPEC_URSHL ; Used in aarch64-simd.md.
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UNSPEC_SQRSHL ; Used in aarch64-simd.md.
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UNSPEC_UQRSHL ; Used in aarch64-simd.md.
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UNSPEC_CMEQ ; Used in aarch64-simd.md.
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UNSPEC_CMLE ; Used in aarch64-simd.md.
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UNSPEC_CMLT ; Used in aarch64-simd.md.
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UNSPEC_CMGE ; Used in aarch64-simd.md.
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UNSPEC_CMGT ; Used in aarch64-simd.md.
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UNSPEC_CMHS ; Used in aarch64-simd.md.
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UNSPEC_CMHI ; Used in aarch64-simd.md.
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UNSPEC_SSLI ; Used in aarch64-simd.md.
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UNSPEC_USLI ; Used in aarch64-simd.md.
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UNSPEC_SSRI ; Used in aarch64-simd.md.
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@ -227,7 +223,6 @@
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UNSPEC_SSHLL ; Used in aarch64-simd.md.
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UNSPEC_USHLL ; Used in aarch64-simd.md.
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UNSPEC_ADDP ; Used in aarch64-simd.md.
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UNSPEC_CMTST ; Used in aarch64-simd.md.
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UNSPEC_FMAX ; Used in aarch64-simd.md.
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UNSPEC_FMIN ; Used in aarch64-simd.md.
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UNSPEC_TBL ; Used in vector permute patterns.
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@ -253,6 +248,7 @@
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;; For scalar usage of vector/FP registers
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(define_mode_attr v [(QI "b") (HI "h") (SI "s") (DI "d")
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(SF "s") (DF "d")
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(V8QI "") (V16QI "")
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(V4HI "") (V8HI "")
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(V2SI "") (V4SI "")
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@ -307,7 +303,8 @@
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(V4SF ".4s") (V2DF ".2d")
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(DI "") (SI "")
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(HI "") (QI "")
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(TI "")])
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(TI "") (SF "")
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(DF "")])
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;; Register suffix narrowed modes for VQN.
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(define_mode_attr Vmntype [(V8HI ".8b") (V4SI ".4h")
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@ -446,7 +443,8 @@
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(V2SI "V2SI") (V4SI "V4SI")
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(DI "DI") (V2DI "V2DI")
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(V2SF "V2SI") (V4SF "V4SI")
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(V2DF "V2DI")])
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(V2DF "V2DI") (DF "DI")
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(SF "SI")])
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;; Lower case mode of results of comparison operations.
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(define_mode_attr v_cmp_result [(V8QI "v8qi") (V16QI "v16qi")
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@ -454,7 +452,8 @@
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(V2SI "v2si") (V4SI "v4si")
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(DI "di") (V2DI "v2di")
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(V2SF "v2si") (V4SF "v4si")
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(V2DF "v2di")])
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(V2DF "v2di") (DF "di")
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(SF "si")])
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||||
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||||
;; Vm for lane instructions is restricted to FP_LO_REGS.
|
||||
(define_mode_attr vwx [(V4HI "x") (V8HI "x") (HI "x")
|
||||
|
|
@ -548,6 +547,12 @@
|
|||
;; Code iterator for signed variants of vector saturating binary ops.
|
||||
(define_code_iterator SBINQOPS [ss_plus ss_minus])
|
||||
|
||||
;; Comparison operators for <F>CM.
|
||||
(define_code_iterator COMPARISONS [lt le eq ge gt])
|
||||
|
||||
;; Unsigned comparison operators.
|
||||
(define_code_iterator UCOMPARISONS [ltu leu geu gtu])
|
||||
|
||||
;; -------------------------------------------------------------------
|
||||
;; Code Attributes
|
||||
;; -------------------------------------------------------------------
|
||||
|
|
@ -580,7 +585,28 @@
|
|||
(eq "eq")
|
||||
(ne "ne")
|
||||
(lt "lt")
|
||||
(ge "ge")])
|
||||
(ge "ge")
|
||||
(le "le")
|
||||
(gt "gt")
|
||||
(ltu "ltu")
|
||||
(leu "leu")
|
||||
(geu "geu")
|
||||
(gtu "gtu")])
|
||||
|
||||
;; For comparison operators we use the FCM* and CM* instructions.
|
||||
;; As there are no CMLE or CMLT instructions which act on 3 vector
|
||||
;; operands, we must use CMGE or CMGT and swap the order of the
|
||||
;; source operands.
|
||||
|
||||
(define_code_attr n_optab [(lt "gt") (le "ge") (eq "eq") (ge "ge") (gt "gt")
|
||||
(ltu "hi") (leu "hs") (geu "hs") (gtu "hi")])
|
||||
(define_code_attr cmp_1 [(lt "2") (le "2") (eq "1") (ge "1") (gt "1")
|
||||
(ltu "2") (leu "2") (geu "1") (gtu "1")])
|
||||
(define_code_attr cmp_2 [(lt "1") (le "1") (eq "2") (ge "2") (gt "2")
|
||||
(ltu "1") (leu "1") (geu "2") (gtu "2")])
|
||||
|
||||
(define_code_attr CMP [(lt "LT") (le "LE") (eq "EQ") (ge "GE") (gt "GT")
|
||||
(ltu "LTU") (leu "LEU") (geu "GEU") (gtu "GTU")])
|
||||
|
||||
(define_code_attr fix_trunc_optab [(fix "fix_trunc")
|
||||
(unsigned_fix "fixuns_trunc")])
|
||||
|
|
@ -693,11 +719,6 @@
|
|||
UNSPEC_SQSHRN UNSPEC_UQSHRN
|
||||
UNSPEC_SQRSHRN UNSPEC_UQRSHRN])
|
||||
|
||||
(define_int_iterator VCMP_S [UNSPEC_CMEQ UNSPEC_CMGE UNSPEC_CMGT
|
||||
UNSPEC_CMLE UNSPEC_CMLT])
|
||||
|
||||
(define_int_iterator VCMP_U [UNSPEC_CMHS UNSPEC_CMHI UNSPEC_CMTST])
|
||||
|
||||
(define_int_iterator PERMUTE [UNSPEC_ZIP1 UNSPEC_ZIP2
|
||||
UNSPEC_TRN1 UNSPEC_TRN2
|
||||
UNSPEC_UZP1 UNSPEC_UZP2])
|
||||
|
|
@ -784,12 +805,6 @@
|
|||
(UNSPEC_RADDHN2 "add")
|
||||
(UNSPEC_RSUBHN2 "sub")])
|
||||
|
||||
(define_int_attr cmp [(UNSPEC_CMGE "ge") (UNSPEC_CMGT "gt")
|
||||
(UNSPEC_CMLE "le") (UNSPEC_CMLT "lt")
|
||||
(UNSPEC_CMEQ "eq")
|
||||
(UNSPEC_CMHS "hs") (UNSPEC_CMHI "hi")
|
||||
(UNSPEC_CMTST "tst")])
|
||||
|
||||
(define_int_attr offsetlr [(UNSPEC_SSLI "1") (UNSPEC_USLI "1")
|
||||
(UNSPEC_SSRI "0") (UNSPEC_USRI "0")])
|
||||
|
||||
|
|
|
|||
|
|
@ -31,6 +31,11 @@
|
|||
(ior (match_operand 0 "register_operand")
|
||||
(match_test "op == const0_rtx"))))
|
||||
|
||||
(define_predicate "aarch64_reg_or_fp_zero"
|
||||
(and (match_code "reg,subreg,const_double")
|
||||
(ior (match_operand 0 "register_operand")
|
||||
(match_test "aarch64_float_const_zero_rtx_p (op)"))))
|
||||
|
||||
(define_predicate "aarch64_reg_zero_or_m1_or_1"
|
||||
(and (match_code "reg,subreg,const_int")
|
||||
(ior (match_operand 0 "register_operand")
|
||||
|
|
|
|||
Loading…
Reference in New Issue