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sparc.c (const64_operand, [...]): New predicates.

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* config/sparc/sparc.c (const64_operand, const64_high_operand):
	New predicates.
	* config/sparc/sparc.h: Declare them.
	(PREDICATE_CODES): Add them.
	* config/sparc/sparc.md (movdi_lo_sum_sp64_dbl,
	movdi_high_sp64_dbl, xordi3_sp64_dbl): Use them.

From-SVN: r21663
This commit is contained in:
David S. Miller 1998-08-11 07:13:17 +00:00 committed by David S. Miller
parent 2a01c93937
commit 89e65674fa
4 changed files with 51 additions and 25 deletions
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7
gcc/ChangeLog
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@ -18,6 +18,13 @@ Tue Aug 11 04:46:01 1998 David S. Miller <davem@pierdol.cobaltmicro.com>
(define_insn zero_extendsidi2_insn_sp32): New pattern and
assosciated forced split for it.
* config/sparc/sparc.c (const64_operand, const64_high_operand):
New predicates.
* config/sparc/sparc.h: Declare them.
(PREDICATE_CODES): Add them.
* config/sparc/sparc.md (movdi_lo_sum_sp64_dbl,
movdi_high_sp64_dbl, xordi3_sp64_dbl): Use them.
Mon Aug 10 22:57:24 1998 John Carr <jfc@mit.edu>
* config/sparc/sparc.md (define_insn jump): Output ba,pt not b,pt

30
gcc/config/sparc/sparc.c
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@ -781,6 +781,36 @@ arith_operand (op, mode)
return SPARC_SIMM13_P (val);
}
/* Return true if OP is a CONST_INT or a CONST_DOUBLE which can fit in the
immediate field of OR and XOR instructions. Used for 64-bit
constant formation patterns. */
int
const64_operand (op, mode)
rtx op;
enum machine_mode mode;
{
return ((GET_CODE (op) == CONST_INT
&& SPARC_SIMM13_P (INTVAL (op)))
|| (GET_CODE (op) == CONST_DOUBLE
&& CONST_DOUBLE_HIGH (op) == 0
&& SPARC_SIMM13_P (CONST_DOUBLE_LOW (op)))
|| GET_CODE (op) == CONSTANT_P_RTX);
}
/* The same, but considering what can fit for a sethi instruction. */
int
const64_high_operand (op, mode)
rtx op;
enum machine_mode mode;
{
return ((GET_CODE (op) == CONST_INT
&& SPARC_SETHI_P (INTVAL (op)))
|| (GET_CODE (op) == CONST_DOUBLE
&& CONST_DOUBLE_HIGH (op) == 0
&& SPARC_SETHI_P (CONST_DOUBLE_LOW (op)))
|| GET_CODE (op) == CONSTANT_P_RTX);
}
/* Return true if OP is a register, or is a CONST_INT that can fit in a
signed 11 bit immediate field. This is an acceptable SImode operand for
the movcc instructions. */

6
gcc/config/sparc/sparc.h
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@ -3201,7 +3201,9 @@ do { \
{"uns_arith_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}}, \
{"clobbered_register", {REG}}, \
{"input_operand", {SUBREG, REG, CONSTANT_P_RTX, CONST_INT, MEM}}, \
{"zero_operand", {CONST_INT, CONSTANT_P_RTX}},
{"zero_operand", {CONST_INT, CONSTANT_P_RTX}}, \
{"const64_operand", {CONST_INT, CONST_DOUBLE, CONSTANT_P_RTX}}, \
{"const64_high_operand", {CONST_INT, CONST_DOUBLE, CONSTANT_P_RTX}},
/* The number of Pmode words for the setjmp buffer. */
@ -3240,6 +3242,8 @@ extern int arith_operand ();
extern int call_operand_address ();
extern int input_operand ();
extern int zero_operand ();
extern int const64_operand ();
extern int const64_high_operand ();
extern int cc_arithop ();
extern int cc_arithopn ();
extern int check_pic ();

33
gcc/config/sparc/sparc.md
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@ -2355,14 +2355,9 @@
(define_insn "*movdi_lo_sum_sp64_dbl"
[(set (match_operand:DI 0 "register_operand" "=r")
(lo_sum:DI (match_operand:DI 1 "register_operand" "r")
(match_operand:DI 2 "const_double_operand" "")))]
"TARGET_ARCH64
&& CONST_DOUBLE_HIGH (operands[2]) == 0"
"*
{
operands[2] = GEN_INT (CONST_DOUBLE_LOW (operands[2]));
return \"or\\t%1, %%lo(%a2), %0\";
}"
(match_operand:DI 2 "const64_operand" "")))]
"TARGET_ARCH64"
"or\\t%1, %%lo(%a2), %0"
[(set_attr "type" "ialu")
(set_attr "length" "1")])
@ -2376,14 +2371,9 @@
(define_insn "*movdi_high_sp64_dbl"
[(set (match_operand:DI 0 "register_operand" "=r")
(high:DI (match_operand:DI 1 "const_double_operand" "")))]
"TARGET_ARCH64
&& CONST_DOUBLE_HIGH (operands[1]) == 0"
"*
{
operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
return \"sethi\\t%%hi(%a1), %0\";
}"
(high:DI (match_operand:DI 1 "const64_high_operand" "")))]
"TARGET_ARCH64"
"sethi\\t%%hi(%a1), %0"
[(set_attr "type" "move")
(set_attr "length" "1")])
@ -5604,14 +5594,9 @@ movtf_is_ok:
(define_insn "*xordi3_sp64_dbl"
[(set (match_operand:DI 0 "register_operand" "=r")
(xor:DI (match_operand:DI 1 "register_operand" "%r")
(match_operand:DI 2 "const_double_operand" "")))]
"TARGET_ARCH64
&& CONST_DOUBLE_HIGH (operands[2]) == 0"
"*
{
operands[2] = GEN_INT (CONST_DOUBLE_LOW (operands[2]));
return \"xor\\t%1, %2, %0\";
}"
(match_operand:DI 2 "const64_operand" "")))]
"TARGET_ARCH64"
"xor\\t%1, %2, %0"
[(set_attr "type" "ialu")
(set_attr "length" "1")])