sparc.c (const64_operand, [...]): New predicates.
* config/sparc/sparc.c (const64_operand, const64_high_operand): New predicates. * config/sparc/sparc.h: Declare them. (PREDICATE_CODES): Add them. * config/sparc/sparc.md (movdi_lo_sum_sp64_dbl, movdi_high_sp64_dbl, xordi3_sp64_dbl): Use them. From-SVN: r21663
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@ -18,6 +18,13 @@ Tue Aug 11 04:46:01 1998 David S. Miller <davem@pierdol.cobaltmicro.com>
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(define_insn zero_extendsidi2_insn_sp32): New pattern and
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(define_insn zero_extendsidi2_insn_sp32): New pattern and
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assosciated forced split for it.
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assosciated forced split for it.
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* config/sparc/sparc.c (const64_operand, const64_high_operand):
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New predicates.
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* config/sparc/sparc.h: Declare them.
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(PREDICATE_CODES): Add them.
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* config/sparc/sparc.md (movdi_lo_sum_sp64_dbl,
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movdi_high_sp64_dbl, xordi3_sp64_dbl): Use them.
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Mon Aug 10 22:57:24 1998 John Carr <jfc@mit.edu>
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Mon Aug 10 22:57:24 1998 John Carr <jfc@mit.edu>
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* config/sparc/sparc.md (define_insn jump): Output ba,pt not b,pt
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* config/sparc/sparc.md (define_insn jump): Output ba,pt not b,pt
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@ -781,6 +781,36 @@ arith_operand (op, mode)
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return SPARC_SIMM13_P (val);
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return SPARC_SIMM13_P (val);
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}
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}
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/* Return true if OP is a CONST_INT or a CONST_DOUBLE which can fit in the
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immediate field of OR and XOR instructions. Used for 64-bit
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constant formation patterns. */
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int
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const64_operand (op, mode)
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rtx op;
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enum machine_mode mode;
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{
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return ((GET_CODE (op) == CONST_INT
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&& SPARC_SIMM13_P (INTVAL (op)))
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|| (GET_CODE (op) == CONST_DOUBLE
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&& CONST_DOUBLE_HIGH (op) == 0
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&& SPARC_SIMM13_P (CONST_DOUBLE_LOW (op)))
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|| GET_CODE (op) == CONSTANT_P_RTX);
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}
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/* The same, but considering what can fit for a sethi instruction. */
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int
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const64_high_operand (op, mode)
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rtx op;
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enum machine_mode mode;
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{
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return ((GET_CODE (op) == CONST_INT
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&& SPARC_SETHI_P (INTVAL (op)))
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|| (GET_CODE (op) == CONST_DOUBLE
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&& CONST_DOUBLE_HIGH (op) == 0
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&& SPARC_SETHI_P (CONST_DOUBLE_LOW (op)))
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|| GET_CODE (op) == CONSTANT_P_RTX);
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}
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/* Return true if OP is a register, or is a CONST_INT that can fit in a
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/* Return true if OP is a register, or is a CONST_INT that can fit in a
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signed 11 bit immediate field. This is an acceptable SImode operand for
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signed 11 bit immediate field. This is an acceptable SImode operand for
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the movcc instructions. */
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the movcc instructions. */
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@ -3201,7 +3201,9 @@ do { \
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{"uns_arith_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}}, \
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{"uns_arith_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}}, \
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{"clobbered_register", {REG}}, \
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{"clobbered_register", {REG}}, \
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{"input_operand", {SUBREG, REG, CONSTANT_P_RTX, CONST_INT, MEM}}, \
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{"input_operand", {SUBREG, REG, CONSTANT_P_RTX, CONST_INT, MEM}}, \
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{"zero_operand", {CONST_INT, CONSTANT_P_RTX}},
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{"zero_operand", {CONST_INT, CONSTANT_P_RTX}}, \
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{"const64_operand", {CONST_INT, CONST_DOUBLE, CONSTANT_P_RTX}}, \
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{"const64_high_operand", {CONST_INT, CONST_DOUBLE, CONSTANT_P_RTX}},
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/* The number of Pmode words for the setjmp buffer. */
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/* The number of Pmode words for the setjmp buffer. */
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@ -3240,6 +3242,8 @@ extern int arith_operand ();
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extern int call_operand_address ();
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extern int call_operand_address ();
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extern int input_operand ();
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extern int input_operand ();
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extern int zero_operand ();
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extern int zero_operand ();
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extern int const64_operand ();
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extern int const64_high_operand ();
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extern int cc_arithop ();
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extern int cc_arithop ();
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extern int cc_arithopn ();
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extern int cc_arithopn ();
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extern int check_pic ();
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extern int check_pic ();
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@ -2355,14 +2355,9 @@
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(define_insn "*movdi_lo_sum_sp64_dbl"
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(define_insn "*movdi_lo_sum_sp64_dbl"
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[(set (match_operand:DI 0 "register_operand" "=r")
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[(set (match_operand:DI 0 "register_operand" "=r")
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(lo_sum:DI (match_operand:DI 1 "register_operand" "r")
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(lo_sum:DI (match_operand:DI 1 "register_operand" "r")
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(match_operand:DI 2 "const_double_operand" "")))]
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(match_operand:DI 2 "const64_operand" "")))]
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"TARGET_ARCH64
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"TARGET_ARCH64"
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&& CONST_DOUBLE_HIGH (operands[2]) == 0"
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"or\\t%1, %%lo(%a2), %0"
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"*
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{
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operands[2] = GEN_INT (CONST_DOUBLE_LOW (operands[2]));
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return \"or\\t%1, %%lo(%a2), %0\";
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}"
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[(set_attr "type" "ialu")
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[(set_attr "type" "ialu")
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(set_attr "length" "1")])
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(set_attr "length" "1")])
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@ -2376,14 +2371,9 @@
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(define_insn "*movdi_high_sp64_dbl"
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(define_insn "*movdi_high_sp64_dbl"
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[(set (match_operand:DI 0 "register_operand" "=r")
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[(set (match_operand:DI 0 "register_operand" "=r")
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(high:DI (match_operand:DI 1 "const_double_operand" "")))]
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(high:DI (match_operand:DI 1 "const64_high_operand" "")))]
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"TARGET_ARCH64
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"TARGET_ARCH64"
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&& CONST_DOUBLE_HIGH (operands[1]) == 0"
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"sethi\\t%%hi(%a1), %0"
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"*
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{
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operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
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return \"sethi\\t%%hi(%a1), %0\";
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}"
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[(set_attr "type" "move")
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[(set_attr "type" "move")
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(set_attr "length" "1")])
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(set_attr "length" "1")])
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@ -5604,14 +5594,9 @@ movtf_is_ok:
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(define_insn "*xordi3_sp64_dbl"
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(define_insn "*xordi3_sp64_dbl"
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[(set (match_operand:DI 0 "register_operand" "=r")
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[(set (match_operand:DI 0 "register_operand" "=r")
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(xor:DI (match_operand:DI 1 "register_operand" "%r")
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(xor:DI (match_operand:DI 1 "register_operand" "%r")
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(match_operand:DI 2 "const_double_operand" "")))]
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(match_operand:DI 2 "const64_operand" "")))]
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"TARGET_ARCH64
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"TARGET_ARCH64"
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&& CONST_DOUBLE_HIGH (operands[2]) == 0"
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"xor\\t%1, %2, %0"
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"*
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{
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operands[2] = GEN_INT (CONST_DOUBLE_LOW (operands[2]));
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return \"xor\\t%1, %2, %0\";
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}"
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[(set_attr "type" "ialu")
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[(set_attr "type" "ialu")
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(set_attr "length" "1")])
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(set_attr "length" "1")])
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