mips.h (UNITS_PER_HWFPVALUE): Renamed from...
* config/mips/mips.h (UNITS_PER_HWFPVALUE): Renamed from... (UNITS_PER_FPVALUE): Defined as the width of a long double, or zero if no hardware floating point. (LONG_DUBLE_TYPE_SIZE): Set to 128 on N32 and N64. (MAX_FIXED_MODE_SIZE): Define to LONG_DOUBLE_TYPE_SIZE. (LIBGCC2_LONG_DOUBLE_TYPE_SIZE): Define. (BIGGEST_ALIGNMENT): Same as LONG_DOUBLE_TYPE_SIZE. (FUNCTION_VALUE_REGNO_P): Set for FP_RETURN+2 on N32 and N64. * config/mips/mips.c (mips_arg_info): Pass TFmode values in even FP registers on N32 and N64. (mips_setup_incoming_varargs): Use UNITS_PER_HWFPVALUE. (mips_va_start): Adjust alignment of ARG_POINTER_REGNUM. (mips_va_arg): Use UNITS_PER_HWFPVALUE. Impose additional even-register-like alignment to 128-bit arguments. (save_restore_insns): Use UNITS_PER_HWFPVALUE. (mips_function_value): Likewise. Return TFmode in $f0 and $f2 on N32 or N64. * config/mips/_tilib.c (__negti2, __ashlti3, __lshrti3): New. * config/mips/t-iris6 (LIB2FUNCS_EXTRA): Add _tilib.c. (TPBIT): Set to tp-bit.c. (tp-bit.c): Create out of fp-bit.c. From-SVN: r61945
This commit is contained in:
Alexandre Oliva
Alexandre Oliva
parent
2956f353ba
commit
8a3812735f
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@ -1,3 +1,27 @@
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2003-01-28 Alexandre Oliva <aoliva@redhat.com>
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* config/mips/mips.h (UNITS_PER_HWFPVALUE): Renamed from...
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(UNITS_PER_FPVALUE): Defined as the width of a long double, or
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zero if no hardware floating point.
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(LONG_DUBLE_TYPE_SIZE): Set to 128 on N32 and N64.
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(MAX_FIXED_MODE_SIZE): Define to LONG_DOUBLE_TYPE_SIZE.
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(LIBGCC2_LONG_DOUBLE_TYPE_SIZE): Define.
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(BIGGEST_ALIGNMENT): Same as LONG_DOUBLE_TYPE_SIZE.
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(FUNCTION_VALUE_REGNO_P): Set for FP_RETURN+2 on N32 and N64.
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* config/mips/mips.c (mips_arg_info): Pass TFmode values in
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even FP registers on N32 and N64.
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(mips_setup_incoming_varargs): Use UNITS_PER_HWFPVALUE.
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(mips_va_start): Adjust alignment of ARG_POINTER_REGNUM.
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(mips_va_arg): Use UNITS_PER_HWFPVALUE. Impose additional
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even-register-like alignment to 128-bit arguments.
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(save_restore_insns): Use UNITS_PER_HWFPVALUE.
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(mips_function_value): Likewise. Return TFmode in $f0 and $f2
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on N32 or N64.
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* config/mips/_tilib.c (__negti2, __ashlti3, __lshrti3): New.
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* config/mips/t-iris6 (LIB2FUNCS_EXTRA): Add _tilib.c.
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(TPBIT): Set to tp-bit.c.
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(tp-bit.c): Create out of fp-bit.c.
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2003-01-28 Gabriel Dos Reis <gdr@integrable-solutions.net>
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* c-parse.in: Remove '%expect 32' directive in objc mode.
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@ -4315,9 +4315,11 @@ mips_arg_info (cum, mode, type, named, info)
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is a double, but $f14 if it is a single. Otherwise, on a
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32-bit double-float machine, each FP argument must start in a
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new register pair. */
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even_reg_p = ((mips_abi == ABI_O64 && mode == SFmode) || FP_INC > 1);
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even_reg_p = (GET_MODE_SIZE (mode) > UNITS_PER_HWFPVALUE
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|| (mips_abi == ABI_O64 && mode == SFmode)
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|| FP_INC > 1);
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}
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else if (!TARGET_64BIT)
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else if (!TARGET_64BIT || LONG_DOUBLE_TYPE_SIZE == 128)
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{
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if (GET_MODE_CLASS (mode) == MODE_INT
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|| GET_MODE_CLASS (mode) == MODE_FLOAT)
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@ -4629,7 +4631,7 @@ mips_setup_incoming_varargs (cum, mode, type, no_rtl)
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rtx ptr = plus_constant (virtual_incoming_args_rtx, off);
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emit_move_insn (gen_rtx_MEM (mode, ptr),
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gen_rtx_REG (mode, FP_ARG_FIRST + i));
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off += UNITS_PER_FPVALUE;
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off += UNITS_PER_HWFPVALUE;
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}
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}
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}
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@ -4706,6 +4708,15 @@ mips_va_start (valist, nextarg)
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{
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const CUMULATIVE_ARGS *cum = ¤t_function_args_info;
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/* ARG_POINTER_REGNUM is initialized to STACK_POINTER_BOUNDARY, but
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since the stack is aligned for a pair of argument-passing slots,
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and the beginning of a variable argument list may be an odd slot,
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we have to decrease its alignment. */
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if (cfun && cfun->emit->regno_pointer_align)
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while (((current_function_pretend_args_size * BITS_PER_UNIT)
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& (REGNO_POINTER_ALIGN (ARG_POINTER_REGNUM) - 1)) != 0)
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REGNO_POINTER_ALIGN (ARG_POINTER_REGNUM) /= 2;
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if (mips_abi == ABI_EABI)
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{
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int gpr_save_area_size;
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@ -4903,9 +4914,9 @@ mips_va_arg (valist, type)
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off = build (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff);
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/* When floating-point registers are saved to the stack,
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each one will take up UNITS_PER_FPVALUE bytes, regardless
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each one will take up UNITS_PER_HWFPVALUE bytes, regardless
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of the float's precision. */
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rsize = UNITS_PER_FPVALUE;
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rsize = UNITS_PER_HWFPVALUE;
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}
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else
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{
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@ -4924,7 +4935,7 @@ mips_va_arg (valist, type)
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bytes (= PARM_BOUNDARY bits). RSIZE can sometimes be smaller
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than that, such as in the combination -mgp64 -msingle-float
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-fshort-double. Doubles passed in registers will then take
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up UNITS_PER_FPVALUE bytes, but those passed on the stack
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up UNITS_PER_HWFPVALUE bytes, but those passed on the stack
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take up UNITS_PER_WORD bytes. */
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osize = MAX (rsize, UNITS_PER_WORD);
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@ -4998,7 +5009,10 @@ mips_va_arg (valist, type)
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that alignments <= UNITS_PER_WORD are preserved by the va_arg
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increment mechanism. */
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if (TARGET_64BIT)
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if ((mips_abi == ABI_N32 || mips_abi == ABI_64)
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&& TYPE_ALIGN (type) > 64)
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align = 16;
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else if (TARGET_64BIT)
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align = 8;
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else if (TYPE_ALIGN (type) > 32)
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align = 8;
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@ -7080,7 +7094,7 @@ save_restore_insns (store_p, large_reg, large_offset)
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/* Pick which pointer to use as a base register. */
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fp_offset = cfun->machine->frame.fp_sp_offset;
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end_offset = fp_offset - (cfun->machine->frame.fp_reg_size
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- UNITS_PER_FPVALUE);
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- UNITS_PER_HWFPVALUE);
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if (fp_offset < 0 || end_offset < 0)
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internal_error
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@ -7133,7 +7147,7 @@ save_restore_insns (store_p, large_reg, large_offset)
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else
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emit_move_insn (reg_rtx, mem_rtx);
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fp_offset -= UNITS_PER_FPVALUE;
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fp_offset -= UNITS_PER_HWFPVALUE;
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}
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}
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}
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@ -8264,11 +8278,26 @@ mips_function_value (valtype, func, mode)
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}
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mclass = GET_MODE_CLASS (mode);
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if (mclass == MODE_FLOAT && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE)
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if (mclass == MODE_FLOAT && GET_MODE_SIZE (mode) <= UNITS_PER_HWFPVALUE)
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reg = FP_RETURN;
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else if (mclass == MODE_FLOAT && mode == TFmode)
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/* long doubles are really split between f0 and f2, not f1. Eek.
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Use DImode for each component, since GCC wants integer modes
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for subregs. */
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return gen_rtx_PARALLEL
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(VOIDmode,
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gen_rtvec (2,
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gen_rtx_EXPR_LIST (VOIDmode,
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gen_rtx_REG (DImode, FP_RETURN),
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GEN_INT (0)),
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gen_rtx_EXPR_LIST (VOIDmode,
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gen_rtx_REG (DImode, FP_RETURN + 2),
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GEN_INT (GET_MODE_SIZE (mode) / 2))));
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else if (mclass == MODE_COMPLEX_FLOAT
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&& GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE * 2)
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&& GET_MODE_SIZE (mode) <= UNITS_PER_HWFPVALUE * 2)
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{
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enum machine_mode cmode = GET_MODE_INNER (mode);
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@ -1517,8 +1517,14 @@ do { \
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the next available register. */
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#define FP_INC (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT ? 1 : 2)
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/* The largest size of value that can be held in floating-point registers. */
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#define UNITS_PER_FPVALUE (TARGET_SOFT_FLOAT ? 0 : FP_INC * UNITS_PER_FPREG)
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/* The largest size of value that can be held in floating-point
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registers and moved with a single instruction. */
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#define UNITS_PER_HWFPVALUE (TARGET_SOFT_FLOAT ? 0 : FP_INC * UNITS_PER_FPREG)
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/* The largest size of value that can be held in floating-point
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registers. */
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#define UNITS_PER_FPVALUE \
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(TARGET_SOFT_FLOAT ? 0 : (LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT))
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/* The number of bytes in a double. */
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#define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT)
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@ -1565,7 +1571,21 @@ do { \
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/* A C expression for the size in bits of the type `long double' on
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the target machine. If you don't define this, the default is two
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words. */
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#define LONG_DOUBLE_TYPE_SIZE 64
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#define LONG_DOUBLE_TYPE_SIZE \
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(mips_abi == ABI_N32 || mips_abi == ABI_64 ? 128 : 64)
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/* long double is not a fixed mode, but the idea is that, if we
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support long double, we also want a 128-bit integer type. */
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#define MAX_FIXED_MODE_SIZE LONG_DOUBLE_TYPE_SIZE
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#ifdef IN_LIBGCC2
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#if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
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|| (defined _ABI64 && _MIPS_SIM == _ABI64)
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# define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
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# else
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# define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
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# endif
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#endif
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/* Width in bits of a pointer.
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See also the macro `Pmode' defined below. */
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@ -1592,7 +1612,7 @@ do { \
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#define STRUCTURE_SIZE_BOUNDARY 8
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/* There is no point aligning anything to a rounder boundary than this. */
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#define BIGGEST_ALIGNMENT 64
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#define BIGGEST_ALIGNMENT LONG_DOUBLE_TYPE_SIZE
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/* Set this nonzero if move instructions will actually fail to work
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when given unaligned data. */
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@ -2654,7 +2674,9 @@ extern enum reg_class mips_char_to_class[256];
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On the MIPS, R2 R3 and F0 F2 are the only register thus used.
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Currently, R2 and F0 are only implemented here (C has no complex type) */
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#define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN)
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#define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN \
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|| (LONG_DOUBLE_TYPE_SIZE == 128 && FP_RETURN != GP_RETURN \
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&& (N) == FP_RETURN + 2))
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/* 1 if N is a possible register number for function argument passing.
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We have no FP argument registers when soft-float. When FP registers
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@ -18,3 +18,16 @@ CRTSTUFF_T_CFLAGS=-g1
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# This is only needed in the static libgcc as a band-aid until gcc correctly
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# implements the N32/N64 ABI structure passing conventions
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LIB2FUNCS_STATIC_EXTRA = $(srcdir)/config/mips/irix6-libc-compat.c
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LIB2FUNCS_EXTRA = $(srcdir)/config/mips/_tilib.c
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TPBIT = tp-bit.c
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tp-bit.c: $(srcdir)/config/fp-bit.c
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echo '#ifdef __MIPSEL__' > tp-bit.c
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echo '# define FLOAT_BIT_ORDER_MISMATCH' >> tp-bit.c
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echo '#endif' >> tp-bit.c
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echo '#if __LDBL_MANT_DIG__ == 106' >> tp-bit.c
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echo '# define TFLOAT' >> tp-bit.c
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cat $(srcdir)/config/fp-bit.c >> tp-bit.c
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echo '#endif' >> tp-bit.c
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