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[AArch64] Remove redundant SVE FADDA pattern

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*pred_fold_left_plus_<mode> could no longer match anything, since
UNSPEC_FADDA now takes three operands.  Predicated FADDAs should
now go through mask_fold_left_plus_<mode> instead.

2019-08-07  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
	* config/aarch64/aarch64-sve.md (*pred_fold_left_plus_<mode>): Delete.

From-SVN: r274186
This commit is contained in:
Richard Sandiford 2019-08-07 18:47:26 +00:00 committed by Richard Sandiford
parent cb18e86dd0
commit 8ad84de26e
2 changed files with 4 additions and 15 deletions
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4
gcc/ChangeLog
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@ -1,3 +1,7 @@
2019-08-07 Richard Sandiford <richard.sandiford@arm.com>
* config/aarch64/aarch64-sve.md (*pred_fold_left_plus_<mode>): Delete.
2019-08-07 Richard Sandiford <richard.sandiford@arm.com>
* config/aarch64/iterators.md (UNSPEC_COND_ADD): Rename to...

15
gcc/config/aarch64/aarch64-sve.md
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@ -3468,21 +3468,6 @@
"fadda\t%<Vetype>0, %3, %<Vetype>0, %2.<Vetype>"
)
;; Predicated form of the above in-order reduction.
(define_insn "*pred_fold_left_plus_<mode>"
[(set (match_operand:<VEL> 0 "register_operand" "=w")
(unspec:<VEL>
[(match_operand:<VEL> 1 "register_operand" "0")
(unspec:SVE_F
[(match_operand:<VPRED> 2 "register_operand" "Upl")
(match_operand:SVE_F 3 "register_operand" "w")
(match_operand:SVE_F 4 "aarch64_simd_imm_zero")]
UNSPEC_SEL)]
UNSPEC_FADDA))]
"TARGET_SVE"
"fadda\t%<Vetype>0, %2, %<Vetype>0, %3.<Vetype>"
)
;; =========================================================================
;; == Permutes
;; =========================================================================