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mn10300.md (addsi): `inc4' on address registers does not modify cc... 

* config/mn10300/mn10300.md (addsi): `inc4' on address
registers does not modify cc, but `inc' on an extended
register does.

From-SVN: r33363
This commit is contained in:
Alexandre Oliva 2000-04-23 23:28:39 +00:00 committed by Alexandre Oliva
parent 713f0303cc
commit 8b2cfbe6ea
2 changed files with 14 additions and 7 deletions
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6
gcc/ChangeLog
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@ -1,3 +1,9 @@
Sun Apr 23 20:16:49 2000 Alexandre Oliva <aoliva@cygnus.com>
* config/mn10300/mn10300.md (addsi): `inc4' on address
registers does not modify cc, but `inc' on an extended
register does.
Sun Apr 23 16:24:35 2000 Denis Chertykov <denisc@overta.ru>
* reload.c (find_equiv_reg): Checks all valueno regs

15
gcc/config/mn10300/mn10300.md
View File

@ -760,9 +760,9 @@
}")
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=dx,ax,ax,dax,xy,!dax")
(plus:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,dax")
(match_operand:SI 2 "nonmemory_operand" "J,J,L,daxi,i,dax")))]
[(set (match_operand:SI 0 "register_operand" "=dx,a,x,a,dax,xy,!dax")
(plus:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0,dax")
(match_operand:SI 2 "nonmemory_operand" "J,J,L,L,daxi,i,dax")))]
"TARGET_AM33"
"*
{
@ -772,11 +772,12 @@
case 1:
return \"inc %0\";
case 2:
return \"inc4 %0\";
case 3:
return \"inc4 %0\";
case 4:
return \"add %2,%0\";
case 5:
return \"add %2,%0\";
case 6:
{
enum reg_class src1_class, src2_class, dst_class;
@ -835,10 +836,10 @@
abort ();
}
}"
[(set_attr "cc" "set_zn,none_0hit,none_0hit,set_zn,none_0hit,set_zn")])
[(set_attr "cc" "set_zn,none_0hit,set_zn,none_0hit,set_zn,none_0hit,set_zn")])
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=dx,ax,ax,dax,xy,!dax")
[(set (match_operand:SI 0 "register_operand" "=dx,a,a,dax,xy,!dax")
(plus:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,dax")
(match_operand:SI 2 "nonmemory_operand" "J,J,L,daxi,i,dax")))]
""