re PR target/78967 (inserts are not effective)
target/78967 * config/i386/i386.md (UNSPEC_NOREX_MEM): New unspec. (*insvqi_1): New insn pattern. (*insvqi_1_mem_rex64): Ditto. (*insvqi_2): Ditto. (*insvqi_3): Rename from *insvqi. (*extzvqi_mem_rex64): Add UNSPEC_NOREX_MEM tag. testsuite/ChangeLog: PR target/78967 * gcc.target/i386/pr78967-1.c: New test. * gcc.target/i386/pr78967-2.c: Ditto. * gcc.target/i386/pr78967-3.c: Ditto. * gcc.target/i386/pr78904-2.c: Tighten scan-asm patterns. * gcc.target/i386/pr78904-4.c: Ditto. * gcc.target/i386/pr78904-6.c: Ditto. From-SVN: r244006
This commit is contained in:
parent
11627b814e
commit
8b7163c630
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@ -1,3 +1,14 @@
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2017-01-02 Uros Bizjak <ubizjak@gmail.com>
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PR target/78967
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* config/i386/i386.md (UNSPEC_NOREX_MEM): New unspec.
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(*insvqi_1): New insn pattern.
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(*insvqi_1_mem_rex64): Ditto.
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(*insvqi_2): Ditto.
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(*insvqi_3): Rename from *insvqi.
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(*extzvqi_mem_rex64): Add UNSPEC_NOREX_MEM tag.
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2017-01-02 Gerald Pfeifer <gerald@pfeifer.com>
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* doc/cfg.texi (Edges): Remove reference to Java.
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@ -114,6 +114,7 @@
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UNSPEC_STOS
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UNSPEC_PEEPSIB
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UNSPEC_INSN_FALSE_DEP
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UNSPEC_NOREX_MEM
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;; For SSE/MMX support:
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UNSPEC_FIX_NOTRUNC
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@ -2819,7 +2820,8 @@
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(subreg:QI
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(zero_extract:SI (match_operand 1 "ext_register_operand" "Q")
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(const_int 8)
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(const_int 8)) 0))]
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(const_int 8)) 0))
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(unspec [(const_int 0)] UNSPEC_NOREX_MEM)]
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"TARGET_64BIT && reload_completed"
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"mov{b}\t{%h1, %0|%0, %h1}"
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[(set_attr "type" "imov")
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@ -2862,11 +2864,13 @@
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(set (match_operand:QI 2 "norex_memory_operand") (match_dup 0))]
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"TARGET_64BIT
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&& peep2_reg_dead_p (2, operands[0])"
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[(set (match_dup 2)
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(subreg:QI
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(zero_extract:SI (match_dup 1)
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(const_int 8)
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(const_int 8)) 0))])
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[(parallel
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[(set (match_dup 2)
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(subreg:QI
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(zero_extract:SI (match_dup 1)
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(const_int 8)
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(const_int 8)) 0))
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(unspec [(const_int 0)] UNSPEC_NOREX_MEM)])])
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(define_expand "insv<mode>"
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[(set (zero_extract:SWI248 (match_operand:SWI248 0 "register_operand")
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@ -2916,7 +2920,59 @@
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(set_attr "type" "imov")
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(set_attr "mode" "QI")])
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(define_insn "*insvqi"
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(define_insn "*insvqi_1_mem_rex64"
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[(set (zero_extract:SI (match_operand 0 "ext_register_operand" "+Q")
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(const_int 8)
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(const_int 8))
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(subreg:SI
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(match_operand:QI 1 "norex_memory_operand" "Bn") 0))
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(unspec [(const_int 0)] UNSPEC_NOREX_MEM)]
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"TARGET_64BIT && reload_completed"
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"mov{b}\t{%1, %h0|%h0, %1}"
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[(set_attr "type" "imov")
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(set_attr "mode" "QI")])
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(define_insn "*insvqi_1"
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[(set (zero_extract:SI (match_operand 0 "ext_register_operand" "+Q,Q")
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(const_int 8)
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(const_int 8))
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(subreg:SI
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(match_operand:QI 1 "general_operand" "QnBc,m") 0))]
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""
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"mov{b}\t{%1, %h0|%h0, %1}"
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[(set_attr "isa" "*,nox64")
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(set_attr "type" "imov")
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(set_attr "mode" "QI")])
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(define_peephole2
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[(set (match_operand:QI 0 "register_operand")
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(match_operand:QI 1 "norex_memory_operand"))
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(set (zero_extract:SI (match_operand 2 "ext_register_operand")
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(const_int 8)
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(const_int 8))
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(subreg:SI (match_dup 0) 0))]
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"TARGET_64BIT
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&& peep2_reg_dead_p (2, operands[0])"
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[(parallel
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[(set (zero_extract:SI (match_dup 2)
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(const_int 8)
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(const_int 8))
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(subreg:SI (match_dup 1) 0))
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(unspec [(const_int 0)] UNSPEC_NOREX_MEM)])])
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(define_insn "*insvqi_2"
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[(set (zero_extract:SI (match_operand 0 "ext_register_operand" "+Q")
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(const_int 8)
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(const_int 8))
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(zero_extract:SI (match_operand 1 "ext_register_operand" "Q")
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(const_int 8)
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(const_int 8)))]
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""
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"mov{b}\t{%h1, %h0|%h0, %h1}"
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[(set_attr "type" "imov")
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(set_attr "mode" "QI")])
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(define_insn "*insvqi_3"
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[(set (zero_extract:SI (match_operand 0 "ext_register_operand" "+Q")
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(const_int 8)
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(const_int 8))
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@ -1,3 +1,14 @@
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2017-01-02 Uros Bizjak <ubizjak@gmail.com>
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PR target/78967
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* gcc.target/i386/pr78967-1.c: New test.
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* gcc.target/i386/pr78967-2.c: Ditto.
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* gcc.target/i386/pr78967-3.c: Ditto.
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* gcc.target/i386/pr78904-2.c: Tighten scan-asm patterns.
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* gcc.target/i386/pr78904-4.c: Ditto.
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* gcc.target/i386/pr78904-6.c: Ditto.
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2017-01-01 Jan Hubicka <hubicka@ucw.cz>
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PR middle-end/77674
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@ -18,7 +18,7 @@ struct S1 test_and (struct S1 a)
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return a;
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}
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/* { dg-final { scan-assembler "\[ \t\]andb\[^\n\r]*, %.h" } } */
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/* { dg-final { scan-assembler "\[ \t\]andb\[ \t\]+t\[^\n\r]*, %.h" } } */
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struct S1 test_or (struct S1 a)
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{
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@ -27,7 +27,7 @@ struct S1 test_or (struct S1 a)
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return a;
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}
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/* { dg-final { scan-assembler "\[ \t\]orb\[^\n\r]*, %.h" } } */
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/* { dg-final { scan-assembler "\[ \t\]orb\[ \t\]+t\[^\n\r]*, %.h" } } */
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struct S1 test_xor (struct S1 a)
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{
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@ -36,7 +36,7 @@ struct S1 test_xor (struct S1 a)
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return a;
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}
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/* { dg-final { scan-assembler "\[ \t\]xorb\[^\n\r]*, %.h" } } */
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/* { dg-final { scan-assembler "\[ \t\]xorb\[ \t\]+t\[^\n\r]*, %.h" } } */
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struct S1 test_add (struct S1 a)
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{
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@ -45,4 +45,4 @@ struct S1 test_add (struct S1 a)
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return a;
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}
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/* { dg-final { scan-assembler "\[ \t\]addb\[^\n\r]*, %.h" } } */
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/* { dg-final { scan-assembler "\[ \t\]addb\[ \t\]+t\[^\n\r]*, %.h" } } */
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@ -18,4 +18,4 @@ void foo (struct S1 a, size_t i)
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t[i] = a.val;
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}
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/* { dg-final { scan-assembler "\[ \t\]movb\[\t \]*%.h," } } */
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/* { dg-final { scan-assembler "\[ \t\]movb\[\t \]+%.h, t" } } */
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@ -18,4 +18,4 @@ void foo (struct S1 a, size_t i)
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t[i] = a.val;
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}
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/* { dg-final { scan-assembler "\[ \t\]movb\[\t \]*%.h," } } */
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/* { dg-final { scan-assembler "\[ \t\]movb\[\t \]*%.h, t" } } */
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@ -0,0 +1,21 @@
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/* PR target/78967 */
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/* { dg-do compile } */
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/* { dg-options "-O2 -masm=att" } */
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/* { dg-additional-options "-mregparm=3" { target ia32 } } */
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/* { dg-final { scan-assembler-not "movzbl" } } */
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struct S1
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{
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unsigned char pad1;
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unsigned char val;
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unsigned short pad2;
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};
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struct S1 foo (struct S1 a, struct S1 b)
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{
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a.val = b.val;
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return a;
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}
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/* { dg-final { scan-assembler "\[ \t\]movb\[ \t\]+%.h, %.h" } } */
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@ -0,0 +1,24 @@
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/* PR target/78967 */
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/* { dg-do compile } */
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/* { dg-options "-O2 -masm=att" } */
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/* { dg-final { scan-assembler-not "movzbl" } } */
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typedef __SIZE_TYPE__ size_t;
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struct S1
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{
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unsigned char pad1;
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unsigned char val;
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unsigned short pad2;
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};
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extern unsigned char t[256];
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struct S1 foo (struct S1 a, size_t i)
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{
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a.val = t[i];
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return a;
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}
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/* { dg-final { scan-assembler "\[ \t\]movb\[ \t\]+t\[^\n\r]*, %.h" } } */
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@ -0,0 +1,24 @@
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/* PR target/78967 */
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/* { dg-do assemble { target { ! ia32 } } } */
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/* { dg-options "-O2" } */
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typedef __SIZE_TYPE__ size_t;
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struct S1
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{
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unsigned char pad1;
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unsigned char val;
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unsigned short pad2;
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};
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extern unsigned char t[256];
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struct S1 foo (struct S1 a, size_t i)
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{
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register size_t _i __asm ("r10") = i;
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asm volatile ("" : "+r" (_i));
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a.val = t[_i];
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return a;
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}
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